JP3102164B2 - Destuff circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a backbone transmission system, a public network,
The present invention relates to a destuff circuit in a digital transmission / switching system used for a transmission system such as a subscriber system, and more particularly to a destuff circuit for performing destuff processing in byte units.

[0002]

2. Description of the Related Art In a digital transmission system, there is a stuff multiplex system as a system for performing synchronous transmission. For example, SO
NET (Synchronous Optical N)
ETwork) enables synchronous transmission by stuff multiplexing in byte units.

FIG. 3 is a configuration diagram of a receiving circuit in a conventional stuff multiplexing apparatus, that is, a destuffing circuit for performing a destuffing process. In the figure, reference numeral 301 denotes a reception data line for receiving the reception data S301, 302 denotes a reception clock line for receiving the reception clock S302, 303 denotes a destuff control line for receiving the destuff control signal S303, 304 denotes a write address generation circuit, and 307 denotes a buffer. memory,
308 is a phase comparator, 309 is a low-pass filter, 31
0 is a voltage controlled oscillator, 311 is a read address generation circuit, and 313 is an output data line for generating output data S313. Here, the reception data S301 and the reception clock S
Reference numeral 302 denotes a signal whose frequency and phase are synchronized. The destuff control signal S303 is "1" when the reception circuit receives the stuff information inserted in the reception data S301 at the time of the stuff in the transmission circuit (not shown) of the multiplexing device, and "0" when there is no stuff. It is assumed that As the stuffing method, there are a positive stuff (P stuff) that inserts dummy data into transmission data in the transmission circuit to delay a data signal and a negative stuff (N stuff) that advances transmission data.

Hereinafter, the P stuff control operation in byte units will be described with reference to FIG. P destuff processing
This is achieved by writing the reception data S301 excluding the dummy data inserted in the P stuff processing on the transmission circuit side to the buffer memory 307, and reading the buffer memory 307 at the correct clock frequency included in the reception data S301. In the destuff circuit, when the destuff control signal S303 is "0", the received data S301 is sequentially written into the buffer memory 307 in accordance with the write address generation circuit 304 controlled by the signal S303. Is “1”, 1
In order to delete the 1-byte dummy data inserted by the P stuffs, the receiving clock S302 is continuously skipped by eight clocks, and the dummy data buffer memory 307 is used.
This is achieved by prohibiting writing to The voltage controlled oscillator 310 is an oscillator for generating a clock signal having an accurate frequency of the received data S301. The read address generation circuit 311 generates a read timing (read address) of the buffer memory 307 based on an output clock signal of the voltage controlled oscillator 310.

[0005] The phase comparator 308 outputs 8
A phase comparison is made between the output of the write address generation circuit 304 and the output of the read address generation circuit 311, which include the continuous clock missing component. The low-pass filter 309 controls the oscillation frequency of the voltage controlled oscillator 310 with a signal from which the high frequency component of the output of the phase comparator 308 has been cut, and locks the oscillation frequency of the voltage controlled oscillator 310 to the correct data frequency of the received data S301. . By this control, the writing frequency and the reading frequency to and from the buffer memory 307 become equal, so that the destuffing process in byte units is realized. Further, even when destuffing occurs continuously, for example, when the destuffing control signal S303 becomes “1” for N consecutive times, destuffing processing can be performed by continuously skipping N × 8 clocks. It is possible.

[0006]

The destuffing circuit using the above-mentioned prior art generates continuous omissions in the received clock signal in order to delete the dummy data inserted by the stuffing, and controls the frequency of the read clock. Is performed based on the phase comparison between the continuous omission clock signal and the output of the voltage controlled oscillator, so that the frequency of the output clock of the voltage controlled oscillator fluctuates greatly during continuous omission, and the time variation of the output data, that is, There has been a problem that jitter increases rapidly.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve the above-described problems and suppress the occurrence of jitter in output data even during byte destuffing, and to enable a byte destuffing process that occurs continuously. It is to provide a circuit.

[0008]

SUMMARY OF THE INVENTION A destuff circuit of the present invention stores received data stuff multiplexed in byte units in byte units according to a write address and reads the written received data in byte units in accordance with a read address. A write address for generating the write address based on the destuff information in response to a memory and a receive clock synchronized with the receive data and a destuff control signal including destuff information indicating the presence or absence of destuff of the receive data; Generating means; receiving the destuffing control signal; and dispersing omission density control means for generating an omission density control signal for controlling omission generation density of the reception clock according to the amount of the destuffing; and the omission density control. Omission generating means for dispersing the reception clock in response to a signal A phase comparator that generates a clock control signal by comparing a phase between the read address and the dispersed toothless clock from the toothlessness generating means; and a voltage controller that controls the phase of an oscillation clock by the clock control signal. An oscillating means, and a read address generating means for generating the read address based on the oscillating clock, a destuff circuit for performing destuff processing in byte units , wherein the destuff circuit further comprises:
Address of the write address and the read address
Address phase comparing means for detecting the address phase difference.
The missing tooth generating means further includes the address phase difference detection
Controls the amount of omission of the dispersed omission clock also by the amount
And a certain range of the address phase difference detection amount.
Within the hysteresis characteristic
It is characterized by having means for providing

[0009]

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.

This destuff circuit is a receiving circuit in the stuff multiplexing device, and performs destuff processing. In the figure, reference numeral 101 denotes a reception data line for receiving the reception data S101, 102 denotes a reception clock line for receiving the reception clock S102, 103 denotes a destuff control line for receiving the destuff control signal S103, 104 denotes a write address generation circuit, and 105 denotes a distributed circuit. Tooth loss density control circuit, 106: tooth loss generation circuit, 107: buffer memory, 108: phase comparator, 109: low-pass filter, 110: voltage controlled oscillator, 111: read address generation circuit, 112: address phase comparison circuit, 113 Is an output data line for generating output data S113. Here, the reception data S101 and the reception clock S102 are signals synchronized in frequency and phase. The destuff control signal S103 is used for receiving data S10 at the time of stuff in a transmission circuit (not shown) of the multiplexer.
When the stuff information inserted into 1 is received by the receiving circuit side, it becomes "1", and when there is no stuff, it becomes "0".

Hereinafter, the P-stuff control operation in byte units will be described with reference to FIG. P destuff processing
This is achieved by writing the reception data S101 excluding the dummy data inserted in the P stuff processing on the transmission circuit side to the buffer memory 107 and reading out the buffer memory 107 at the correct clock frequency included in the reception data S101. In this destuff circuit, when the destuff control signal S103 is "0", the received data 101 is sequentially written into the buffer memory 107 in accordance with the write address generation circuit 104 controlled by the signal S303, while the destuff control signal S103 Is "1",
In order to delete one byte of dummy data inserted by one P stuff, the reception clock S102 is continuously skipped by eight clocks, and the dummy data buffer memory 10
By prohibiting the writing to the data 7, the writing of the data signal excluding the dummy data inserted into the reception data 101 due to the generation of the stuff into the buffer memory 107 is performed. On the other hand, in order to generate a read clock from the buffer memory 107, the buffer memory 107 having continuous omissions is required.
In addition to the write clock described above, a clock signal generated by the missing tooth generation circuit 106 based on the output of the missing tooth density control circuit 105 and having the missing teeth dispersed therein is used.

When the destuff control signal 103 is "0", the write address generation circuit 104
101 are sequentially written into the buffer memory 107. on the other hand,
When the destuff control signal S103 is "1", the circuit 104 receives the reception clock S102 in order to delete one byte of dummy data inserted by one P stuff.
For 8 clocks continuously, and the buffer memory 10
7 is prohibited. Further, the dispersion omission density control circuit 105 adaptively changes the dispersion omission density based on the destuff signal S103 supplied from the destuff control line 103 and the internal state, and
6 is controlled.

That is, the dispersion tooth omission density control circuit 105
When receiving the destuff signal S103 having the destuff information N times during the M frame, the reception clock S1
A dispersion (clock) omission control signal of 02 is generated at one clock cycle in the M / 8N frame. For example, when a single P destuff occurs during M frames, the control circuit 105 outputs eight clock omission control signals to M / 8.
In the case where two consecutive or two P destuffing processes occur during the M frames, 16 clock missing control signals are periodically generated every M / 16 frames. Occurs. Tooth omission generation circuit 106
Performs the missing tooth of the reception clock S102 based on the control signal from the missing tooth control circuit 105. As a result, the output signal of the toothless generation circuit 106 becomes a clock signal that is frequency-synchronized with the data signal obtained by removing the destuff signal from the received data signal S101. Phase comparator 10
8 compares the phase of the output of the read address generation circuit 111 (read address) with the output of the toothlessness generation circuit 106, and outputs the output of the voltage controlled oscillator 110 to the received data S101 by a signal whose high frequency component is cut off by the low-pass filter 109. Lock to the exact frequency of the The read address generation circuit 111 generates the read timing (read address) of the buffer memory 107 based on the output of the voltage controlled oscillator 110, and reads the output data signal S113 from the buffer memory 107.

The operation of the destuff circuit based on the frequency control (this state is referred to as a frequency control system) has been described above. With this control, the destuff circuit shown in FIG. Thus, it is possible to suppress the amount of jitter generated by the stuff in byte units.

Next, the writing / writing of the buffer memory 107 is performed.
The relationship between the read timing control and the jitter suppression control system will be described. When a memory slip occurs in the buffer memory 107, the reception data S101 cannot be normally received (stored). For this reason, it is necessary to control the write / read timing of the buffer memory 107. The address phase comparison circuit 112 compares the address phase difference between the output (write address) of the data write address 104 and the output of the read address 111 (read address) to the buffer memory 107. Based on the comparison result, the missing portion generation circuit 106 controls the amount of missing portion of the reception clock S102, and determines the phase difference between the write address and the read address with the memory size of the buffer memory 107 (=
X) is controlled so that the memory slip is prevented. When the omission amount control by the address phase comparison circuit 112 becomes dominant (this state is referred to as a phase control system), the amount of jitter increases. Therefore, from the viewpoint of suppressing the amount of jitter generation, this destuff circuit controls the frequency control. It is desirable to work in a system. Therefore, the missing portion generation circuit 106 switches the phase control system / frequency control system based on the address phase difference detected by the address phase control circuit 112.

FIG. 2 is a diagram showing the relationship between the phase difference between the write address and the read address and the phase / frequency control system in the destuff circuit of FIG.

In this destuffing circuit, a hysteresis characteristic is provided for the tooth loss (density) control amount of the reception clock S102 output from the tooth loss generation circuit 106 between the address phase differences ± Y and ± Z. That is, if the address phase difference is within ± Y, the control amount is set to a in order to make the frequency control by the toothless density control circuit 105 dominant,
If the value is ± Z or more, the above control amount is set to b (which is sufficiently larger than a) to make the phase control by the address phase comparison circuit 112 dominant. Since the control amount is significantly different at the switching point of the phase difference / frequency control, large jitter occurs when the address phase difference fluctuates at the switching point of the phase difference / frequency control. This phenomenon is a phenomenon that is sufficiently assumed in the frequency pull-in process. The hysteresis given to the tooth omission control amount suppresses the generation of jitter in the pulling process. X, Y, and Z serving as switching conditions for the phase / frequency control are predetermined setting parameters.

As described above, the omission density control circuit 105
Is properly performed, the destuff circuit operates as a frequency control system, so that jitter can be suppressed. In addition, when the line clock of the reception data line 101 is switched and the stuff ratio changes suddenly, or when the learning of the omission density control circuit 105 is not completed at the time of turning on the power, the circuit operates as a phase control system, thereby preventing a memory slip. It is possible to do.

[0021]

As described above, according to the present invention, the use of the frequency control system control circuit generates a missing clock corresponding to the destuff amount of the received data and writes the missing clock to the phase comparator. Therefore, the amount of jitter generated by the destuffing process in units of bytes can be suppressed, and there is an effect that it is possible to cope with the continuously generated destuffing process.

Further, by using a phase control system control circuit having a hysteresis characteristic in combination, a memory slip may occur even when the frequency control system control circuit has not completed the learning of the dispersion missing period or when the stuff ratio changes suddenly. There is an effect that it is possible to prevent and suppress the jitter generated in the pull-in process.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between a phase difference between a write address and a read address and a phase / frequency control system in the destuff circuit of the embodiment of FIG.

FIG. 3 is a configuration diagram of a conventional destuff circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 101 reception data line 102 reception clock line 103 destuff control line 104 write address generation circuit 105 dispersion missing density control circuit 106 missing tooth generation circuit 107 buffer memory 108 phase comparator 109 low pass filter 110 voltage controlled oscillator 111 read address generation circuit 112 Address phase comparison circuit 113 Output data line 301 Receive data line 302 Receive clock line 303 Destuff control line 304 Write address generation circuit 307 Buffer memory 308 Phase comparator 309 Low pass filter 310 Voltage controlled oscillator 311 Read address generation circuit 313 Output data line

Continuation of the front page (56) References JP-A-4-257133 (JP, A) JP-A-4-196937 (JP, A) JP-A-6-85778 (JP, A) JP-A-5-14304 (JP, A) JP-A-5-175930 (JP, A) JP-A-5-75563 (JP, A) JP-A-4-269029 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB Name) H04J 3/00 H04L 7/00

Claims (1)

(57) [Claims] 1. A memory for storing received data stuff-multiplexed in byte units in byte units according to a write address, reading out the written received data in byte units in accordance with a read address, and a reception clock synchronized with the received data. Write address generation means for generating the write address based on the destuff information in response to a destuff control signal including destuff information indicating the presence or absence of destuff of the received data;
A distributed omission density control means for receiving the destuff control signal and generating an omission density control signal for controlling the omission generation density of the reception clock in accordance with the amount of the destuff, and responsive to the omission density control signal; Omission generating means for dispersing the received clock, a phase comparator for performing a phase comparison between the read address and the dispersed omission clock from the omission generating means to generate a clock control signal, and the clock A voltage-controlled oscillating means for controlling the phase of an oscillation clock by a control signal, and a read-address generation means for generating the read address based on the oscillation clock ; The destuffing circuit further includes the write address
Address phase difference between the read address and the read address
Address phase comparing means, wherein the toothlessness generating means further comprises the address phase difference detecting means.
The omission amount of the dispersed omission clock is also controlled by the output amount.
And a certain range of the address phase difference detection amount.
Within the box, there is a hysteresis characteristic
A destuffing circuit characterized by having means for imparting characteristics.