JP3348840B2 - Low-speed transmission signal output method when switching clocks in the device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical transmission communication apparatus, and more particularly, to an apparatus clock generator for generating an apparatus clock signal, wherein a phase comparator is provided in the apparatus clock generator. The present invention relates to a low-speed transmission signal output method at the time of clock selection switching.

[0002]

2. Description of the Related Art A low-speed transmission signal output system for switching the internal clock of an apparatus of this type to which the present invention is applied is particularly intended for synchronizing an internal clock signal of an optical transmission communication apparatus with an external clock signal. It is configured.

In the technique disclosed in Japanese Patent Laid-Open Publication No. Hei 5-83238, which is a first conventional example of this kind of technique, the first synchronization timing used as a source of a system clock signal of a synchronization network is determined. When a failure occurs, by providing a holdover unit that maintains the synchronization timing immediately before the failure and by providing the control unit with a function to control the holdover unit, it is usually possible to receive a normal synchronization timing. When you have a normal PL
L performs the same operation as L, but when the first synchronization timing becomes an obstacle, and when switching from the first synchronization timing to the second synchronization timing, the holdover unit controls the integrator by the control from the control unit. The signal level transmitted from the phase comparator via the phase comparator is maintained in the state of the signal level immediately before the obstacle, and is locked as it is. Therefore, since the output control voltage sent to the voltage controlled oscillator is locked at the same voltage, the clock signal generated by the voltage controlled oscillator is locked at the same frequency.

When the second synchronization timing is input to the switching unit at the next timing, the lock of the holdover unit is released under the control of the control unit, and the holdover unit returns to the normal PLL operation again. In this way, it is possible to suppress the frequency fluctuation due to the instantaneous interruption of the synchronization timing at the time of switching. In addition, the first synchronization timing and the second synchronization timing
Even when both of the synchronization timings are disconnected, the frequency immediately before the disconnection can be maintained.

A technique disclosed in Japanese Patent Application Laid-Open No. Hei 9-321614, which is a second conventional example, is disclosed in
(Delay Locked Loop) device.

A DLL device delays an external clock by a variable delay circuit for a time slightly less than one clock period, and cancels a delay generated by a clock driver or the like, thereby substantially keeping the external clock substantially in phase. Is a device for supplying an internal clock. By adding a delay slightly shorter than one clock cycle and a delay generated by a clock driver or the like, the operation is performed so as to be exactly one clock cycle, so that it looks as if the internal clock is supplied without delay.

[0007] Also, among the various device parts receiving the supply of the clock, there are cases where some operate at the rising edge of the clock and some operate at the falling edge. In this case, the duty ratio of the clock is preferably 50%. As an example of this, an edge-triggered flip-flop and a macro block such as a RAM (for example, a circuit block that has a considerably large hardware scale and realizes a specific function, such as a RAM, a FIFO, or an ALU) are mixed. There are cases.

The above-mentioned second conventional example has a function of compensating for a phase shift of a clock and a waveform shaping function, whereby the operating speed of a device receiving the clock can be increased. And a waveform shaping device suitable for the clock supply device.

[0009]

However, in such a low-speed transmission signal output method at the time of switching the clock in the device, there is generally no control over the output of the low-speed transmission signal. Jitter and wander are output too much.

At this time, if the low-speed transmission signal is connected to another device, there is a possibility that main signal data may not pass due to the influence of jitter and wander.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances, and has been made to solve the above-mentioned disadvantages inherent in the prior art. By the transmission signal output method, jitter of low-speed transmission signal generated when switching clock selection in the device,
It is an object of the present invention to provide a new low-speed transmission signal output method at the time of switching the clock selection in the device, which can automatically suppress the wander output.

[0012]

In order to achieve the above-mentioned object, according to the present invention, a low-speed transmission signal output system at the time of switching between clocks in a device is adapted to output several clock signals coming from outside the optical transmission communication device. A device clock selecting unit for inputting and selecting one clock signal to be used as a device clock from among the clock signals, and a selected clock signal input from the device clock selecting unit for inputting the selected clock signal from the device clock selecting unit; An optical transmission communication device comprising: a device clock generation unit including a PLO that performs phase control by an internal clock signal; and a low-speed transmission signal generation unit connected to an output of the device clock generation unit to generate a low-speed transmission signal. A selection clock output from the device clock selection unit is transmitted to a device clock generation unit that generates the device clock signal.
Clock signal and a device clock signal output from the PLO
Phase difference by detecting the presence or absence of a phase difference
The result of the DPLL in the low-speed transmission signal generation unit is obtained using the result.
A phase comparison means for changing and controlling the filter value is provided.

The phase comparing means compares the phase of the device clock signal output from the PLO with the phase of the selected clock signal output from the device clock selector, and outputs "1" in the phase lock state. It is characterized in that a phase comparison result of outputting "0" is generated upon completion.

The phase comparing means receives a device clock signal output from the PLO and divides the frequency by 2 and a first flip-flop which receives a selected clock signal from the device clock selector and divides the frequency by two. A second flip-flop, an exclusive-OR circuit that receives the outputs of the first and second flip-flops and outputs the result as an exclusive-OR, and an output of the exclusive-OR circuit. A third flip-flop in which the signal is input to the set terminal, the ground is input to the D terminal, and the device clock signal from the PLO is input to the C terminal, and the output of the exclusive-OR circuit is input to the set terminal and the third flip-flop is input to the third terminal. And a fourth flip-flop in which the Q output from the flip-flop is input to the D terminal and the device clock signal from the PLO is input to the C terminal, and the output of the exclusive-OR circuit is set. It is characterized by having a fifth flip-flop input were input to the child inputs the Q output of the fourth flip-flop to the D terminal equipment clock signal from the PLO to the C terminal.

The low-speed transmission signal generator performs demultiplexing of an externally high-speed SDH high-speed transmission signal of 51.84 Mb / s or more mainly by using the internal clock signal, and only generates a clock for the overhead part of the SDH frame format. To generate and output missing clock and missing data without overhead data only
The MUX unit, the missing clock coming from the DMUX unit, the missing data, the clock from the reference OSC, and the like.
A destuffing unit that receives a phase comparison result from the device clock generation unit , performs destuffing processing to suppress jitter and wander , and generates a smoothed clock and data, and a destuffing unit. And a U / B unit for performing a unipolar / bipolar conversion process using a smoothed clock and data that suppresses jitter and wander from the data.

The destuff unit inputs the missing clock and the missing data coming from the DMUX unit as a write clock and write data, reads data stored in a memory by a read clock from a DPLL, and reads the read data. A buffer memory to be output and a missing clock coming from the DMUX unit are input, and phase control is performed on the reference OSC to perform jitter and jitter.
And wander are suppressed, and
Input the phase comparison result and filter value of DPLL
To change the amount of jitter and wander suppression, and
And a DPLL for generating a smoothing clock serving as a reading clock of the buffer memory .

[0017]

FIG. 1 shows a low-speed transmission signal output method at the time of switching the clock selection in the device according to the present invention.

An apparatus clock selecting unit 1 for inputting several clock signals arriving from outside the optical transmission communication apparatus, selecting one of the clock signals to be used as an apparatus clock, and outputting the selected clock signal; According to the present invention, a configuration having a Phase Locked Oscillator (hereinafter abbreviated as PLO) 2 for receiving a selected clock signal from the device clock selecting unit 1 and performing phase control by the selected clock signal and the device internal clock signal is provided according to the present invention. In the low-speed transmission signal output method when the internal clock is selected, a phase comparison unit 3 is provided in a device clock generation unit 10 that generates a device clock signal.

The phase comparator 3 compares the phase of the device clock signal output from the PLO 2 with the phase of the selected clock signal output from the device clock selector 1, and outputs "1" at the time of phase pull-in. Upon completion, a phase comparison result of outputting "0" is generated.

Therefore, the digital phase in the low-speed transmission signal generator 20 is calculated using the phase comparison result.
Locked Loop (hereinafter abbreviated as DPLL)
By changing the filter values of (1) and (2), it is possible to reduce jitter and wander output from the low-speed transmission signal.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a preferred embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment according to the present invention.

[Structure of Embodiment] Referring to FIG.
FIG. 1 shows a block configuration of an optical transmission communication device according to an embodiment of the present invention.

The configuration of the optical transmission communication device according to the present invention includes a device clock generator 10 and a low-speed transmission signal generator 20.

The device clock generator 10 receives several clock signals arriving from outside the optical transmission communication device, selects a clock signal to be used as a device clock from the clock signals, and outputs the selected clock signal. Phase Locke, which receives the selection clock signal output from the selection unit 1 and the device clock selection unit 1 and controls the phases of the selected clock signal and the internal clock signal.
d Oscillator (hereinafter abbreviated as PLO)
2, and a phase comparison unit 3 that receives the device clock signal output from the PLO 2 and the selected clock signal output from the device clock selection unit 1, performs a phase comparison, and outputs a phase comparison result.

The low-speed transmission signal generation unit 20 mainly receives the DeH of the SDH high-speed transmission signal of 51.84 Mb / s or more from the outside.
multiplex processing, destuff processing, Unipo
The lar / Bipolar conversion process is performed using the internal clock signal.

FIG. 2 is a circuit block diagram showing one embodiment of the phase comparator shown in FIG.

Referring to FIG. 2, the phase comparator 3 of FIG. 1 is configured as follows. That is, a device clock signal from the PLO 2 is input, a flip-flop (hereinafter abbreviated as FF) A4 for dividing the frequency by two, and a selected clock signal from the device clock selecting unit 1 are input and divided by two. EX-NOR7 which outputs each output of FFB4 and FFB5 by exclusive-OR, and EX-NOR7
The output from the NOR7 is input to the FF SET, the ground is input to the FF D, the device clock signal from the PLO2 is input to the FF C, and the output from the EX-NOR7 is input to the FF SET. , The F output from the FFC 8 to the D of the FF, the FFD 9 for inputting the device clock signal from the PLO 2 to the C of the FF, and the output from the EX-NOR 7 to the SET of the FF, and the Q output from the FFD 9 And an FFE 10 for inputting to the D of the FF and inputting the device clock signal from the PLO 2 to the C of the FF.

FIG. 3 is a circuit block diagram of the low-speed transmission signal generator shown in FIG.

Referring to FIG. 3, the low-speed transmission signal generator 20 shown in FIG. 1 is configured as follows. That is, SDH of 51.84 Mb / s or more mainly from outside
A DMUX unit 21 for performing a Demultiplexing process on a high-speed transmission signal by using a clock signal in the apparatus, generating and outputting an intermittent clock having no clock only in an overhead portion of the SDH frame format and intermittent data having no data only in an overhead portion, A destuffing clock which receives a missing clock, missing data and a clock from a reference oscillator (hereinafter abbreviated as a reference OSC) coming from the DMUX unit 21 and performs a destuffing process to generate a smoothed clock and data Unit 22 and the smoothed clock and data from the destuff unit 22
U / B that performs nipolar / Bipolar conversion processing
It has a part 23.

The destuff unit 22 receives the missing clock and the missing data coming from the DMUX unit 21 as a write clock and write data, reads the data stored in the memory by the read clock from the DPLL 25, and reads the read data. Output buffer memory 2
4 and a DPLL 25 that receives the missing clock coming from the DMUX unit 21, performs phase control on the reference OSC, and generates a smoothed clock.

The DPLL used here is the DPLL disclosed in Japanese Patent Application Laid-Open No. 8-84071 filed by the same applicant as the present application. However,
In the above publication, the time constant of the primary / secondary random walk filter is switched by the output signal of the timer. However, in the present invention, the primary / secondary random walk filter is switched when the phase comparison result signal is being pulled in (“1”). The time constant of the secondary random walk filter is longer, and the time constant of the primary / secondary random walk filter is shorter when the pull-in is completed ("0") (this is the normal state).

[Operation of the Embodiment] Next, the operation of the embodiment according to the present invention will be described.

FIGS. 4 and 5 are timing charts showing an example of the operation of the phase comparison section 3, of which FIG. 4 is a timing chart at the time of phase pull-in and FIG. 5 is a timing chart at the time of phase pull-in completion.

Referring to FIGS. 2 and 4, in the phase lock state, the EX-NOR 7 keeps outputting a set signal because a square wave having a 50% duty ratio is not output. Then, the Q output of each of the FFC8, FFD9, and FFE10 continues to output “1”.

Next, referring to FIG. 5, if the phase pull-in is completed, the EX-NOR 7 does not output a set signal because a square wave having a 50% duty ratio is output.
In the FFC 8, the D input becomes valid, and the Q output becomes “O” at the rise of the selected clock from the device clock selection unit 1. FFD9 receives the "O" output and FF
E10 also continues to output "O" as the Q output.

Referring to FIG. 3, the DPLL 25 has a DM
It has a function of smoothing a clock and suppressing jitter and wander of a low-speed transmission signal with respect to a missing clock coming from the UX unit 21. That is, the phase difference between the missing clock and the read clock coming from the DMUX unit 21 is detected, phase control information is output by filtering the detection result, and the phase control information is controlled with respect to the reference OSC. The result is a read clock. By increasing the time constant of the filter that filters this detection result at the time of phase pull-in and making it small at the completion of phase pull-in, the jitter and wander can be suppressed because the time constant of the filter is large at the time of phase pull-in. Becomes possible.

[0038]

As described above, according to the present invention,
With respect to the optical transmission communication device, in particular, in a device clock generation unit for generating a device clock signal, a low-speed transmission signal output method characterized by providing a phase comparison unit in the device clock generation unit can be obtained.

That is, in the present invention, several clock signals arriving from outside the optical transmission communication device are input,
A device clock selecting unit 1 for selecting and outputting one clock signal to be used as a device clock from among these clock signals, and inputting a selected clock signal from the device clock selecting unit 1 In contrast to the configuration having a PLO 2 that performs phase control by a clock signal, according to the present invention, in this device clock phase pull-in state monitoring method, a phase comparison unit 3 is provided in a device clock generation unit 10 that generates a device clock signal.

The phase comparator 3 compares the phase of the device clock signal output from the PLO 2 with the phase of the selected clock signal output from the device clock selector 1, and outputs "1" in the phase lock state. When the pull-in is completed, a phase comparison result of outputting "0" is generated.

Therefore, the jitter and wander output from the low-speed transmission signal can be reduced by changing the filter value of the DPLL in the low-speed transmission signal generation unit 20 using the phase comparison result. The effect is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment according to the present invention.

FIG. 2 is a circuit block diagram showing one embodiment of a phase comparison unit shown in FIG. 1;

FIG. 3 is a circuit block diagram showing one embodiment of a low-speed transmission signal generator shown in FIG. 1;

FIG. 4 is a timing chart illustrating an operation example (at the time of phase pull-in) of the phase comparison unit illustrated in FIG. 2;

FIG. 5 is a timing chart showing an operation example of the phase comparison section shown in FIG. 2 (when phase pull-in is completed);

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Device clock selection part 2 ... PLO 3 ... Phase comparison part A4, B5, C8, D9, E10 ... Flip-flop 7 ... Exclusive non-OR circuit 10 ... Device clock generation part 20 ... Low-speed transmission signal generation part 21 ... DMUX part 22: Destuff section 23: U / B section 24: Buffer memory 25: DPLL

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-8-265211 (JP, A) JP-A-5-83238 (JP, A) JP-A-9-321614 (JP, A) 84071 (JP, A) JP-A-2000-295207 (JP, A) JP-A-7-202868 (JP, A) JP-A-11-17669 (JP, A) (58) Fields investigated (Int. Cl. ⁷⁾ H04L 7/00 H04J 3/06 H04L 7/033

Claims (5)

(57) [Claims] An apparatus clock selecting unit for inputting several clock signals arriving from outside the optical transmission communication apparatus, selecting one of the clock signals to be used as an apparatus clock, and outputting the selected clock signal; A P which receives a selected clock signal from the device clock selecting unit and performs phase control using the selected clock signal and the device clock signal
An optical transmission communication device comprising: a device clock generation unit having an LO; and a low-speed transmission signal generation unit connected to an output of the device clock generation unit to generate a low-speed transmission signal. Before the clock generator
Selected clock signal output from the device clock selector
And the phase of the device clock signal output from the PLO
The presence or absence of a phase difference is detected by comparison, and the phase comparison result is used.
And a filter value of a DPLL in the low-speed transmission signal generator.
A low-speed transmission signal output method at the time of clock selection switching in the apparatus, wherein a phase comparison means for changing and controlling the transmission is provided. 2. The phase means compares the phase of a device clock signal output from the PLO with the phase of a selected clock signal output from the device clock selector, and outputs "1" in a phase lock state. 2. The low-speed transmission signal output method according to claim 1, further comprising generating a phase comparison result of outputting "0" when the pull-in is completed. 3. The phase comparison means receives a device clock signal output from the PLO and divides the frequency by two, and a second flip-flop receives a selected clock signal from the device clock selection unit and divides the frequency by two. A second flip-flop that divides the frequency, an exclusive-OR circuit that inputs the outputs of the first and second flip-flops and outputs an exclusive-OR operation, A third flip-flop in which the output is input to the set terminal, the ground is input to the D terminal, and the device clock signal from the PLO is input to the C terminal, and the output of the exclusive non-OR circuit is input to the set terminal; A fourth flip-flop in which the Q output from the third flip-flop is input to the D terminal and the device clock signal from the PLO is input to the C terminal, and the output of the exclusive-OR circuit is set. 5. The fifth flip-flop further comprising a fifth flip-flop having a terminal, a Q output of the fourth flip-flop being inputted to a D terminal, and a device clock signal from the PLO being inputted to a C terminal. 3. The low-speed transmission signal output method at the time of the clock selection switching in the device according to any one of 2. 4. An SDH frame format overhead part, wherein the low-speed transmission signal generation unit performs demultiplexing of an externally high-speed SDH high-speed transmission signal of 51.84 Mb / s or more using the internal clock signal. D which generates and outputs a missing clock with no clock and missing data without data only in the overhead part
MUX unit, missing clock, missing data coming from DMUX unit, clock from reference OSC and previous
Serial device phase comparison result suppressing rows have jitter and wander the destuffing processing by entering the smoothed clock from the clock generator, and a destuffing unit for generating data, jitter and wander from the destuffing unit 2. The low-speed transmission signal output method according to claim 1, further comprising: a U / B unit that performs a unipolar / bipolar conversion process using a clock and data smoothed by suppressing the above. 5. The destuffing unit inputs a missing clock and a missing data coming from the DMUX as a write clock and write data, and reads data stored in the memory by a read clock from a DPLL to be described later. A buffer memory for outputting data and a missing clock coming from the DMUX section are input to perform phase control on the reference OSC to control jitter and jitter.
And wander are suppressed, and
Input the phase comparison result and filter value of DPLL
To change the amount of jitter and wander suppression, and
5. The low-speed transmission signal output method according to claim 4, further comprising a DPLL that generates a smoothed clock serving as a read clock of the buffer memory .