JP2840569B2 - Clock synchronization circuit between stations - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inter-station clock synchronizing circuit for synchronizing clock signals of a local station and another station in digital communication.

[0002]

2. Description of the Related Art In the recent communication field, digitalization of communication lines has been progressing. In such digital communication, in order to reduce the communication amount as much as possible for the purpose of reducing the communication cost, the transmitting station generally does not transmit the clock, but adopts a method of reproducing the received clock from the received data. .

FIG. 3 is a block diagram showing the configuration of a conventional clock recovery circuit of this type. In the figure, reference numeral 1 denotes an oscillator used for both a transmission clock and a reception clock;
Reference numeral 2 denotes a 1 / N fixed frequency dividing circuit having a frequency dividing ratio N, 3 denotes a variable frequency dividing circuit, 4 denotes a phase comparator, and 5 denotes an edge detecting circuit. The output of the oscillator 1 is a 1 / N fixed frequency divider 2 and a variable frequency divider 3
The output from the 1 / N fixed frequency divider 2 is used as a transmission clock, and the output from the variable frequency divider 3 is output as a reception clock.

Since the received clock is reproduced from the received data, the received data is input to the edge detection circuit 5 to detect the edge of the received data, and the phase comparator 4 calculates the phase difference from the received clock. The phase difference is input to the variable frequency dividing circuit 3, and the frequency dividing ratio of the variable frequency dividing circuit 3 is controlled.
However, in the clock recovery circuit shown in FIG. 3, the transmission clock and the reception clock are not synchronized, and clock synchronization between stations cannot be ensured. Therefore, there is an inter-station clock synchronization circuit configured to synchronize the transmission clock and the reception clock as shown in FIG.

FIG. 4 is a block diagram showing the configuration of a conventional inter-station clock synchronization circuit. In the figure, the same reference numerals as those in FIG. 3 denote the same or corresponding parts, 6 denotes a low-pass filter, 7 denotes a phase comparator, Reference numeral 10 denotes a voltage controlled oscillator. The inter-station clock synchronization circuit shown in FIG. 4 compares the phase of the transmission clock divided by the 1 / N fixed frequency dividing circuit 2 with the phase of the received clock output from the variable frequency dividing circuit 3 by the phase comparator 7,
A so-called analog PLL circuit that inputs the phase difference as an analog voltage to the voltage controlled oscillator 1 via the low-pass filter 6 and controls the oscillation frequency to synchronize the output of the oscillator 1 with a received clock reproduced from received data. Incorporated.

[0006]

The above-mentioned conventional clock synchronization circuit between stations requires a phase comparator as an analog PLL circuit, which is an obstacle to miniaturization and high density in configuring communication equipment. There was a problem of becoming.

The present invention has been made to solve such a problem, and an object of the present invention is to provide an inter-station clock synchronous circuit which can realize a synchronous circuit equivalent to a conventional circuit while simplifying the circuit configuration. .

[0008]

According to the present invention, there is provided an inter-station clock synchronizing circuit for obtaining a transmission clock from an output of a voltage controlled oscillator via a frequency dividing circuit, and a variable frequency dividing circuit for outputting the output of the voltage controlled oscillator. A PLL that variably controls the frequency dividing ratio of the variable frequency dividing circuit based on the phase difference between the divided output and the edge detection timing obtained from the received data by the edge detecting circuit.
A circuit, means for obtaining a reception clock from the output of the variable frequency dividing circuit, and a case where the frequency dividing ratio is varied in the variable frequency dividing circuit. A period of logic "L" (or a period of logic "H") of the received clock. Means for using a variable frequency dividing circuit for controlling any one of them, means for controlling the oscillation frequency of the voltage-controlled oscillator with an output voltage obtained by smoothing the reception clock, and means for synchronizing the transmission clock with the reception clock. It is characterized by.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention.
In the figure, the same reference numerals as those in FIG. 4 indicate the same or corresponding parts, and reference numeral 30 denotes a variable frequency dividing circuit in the present embodiment. FIG.
FIG. 3 is a diagram showing an output waveform of the variable frequency dividing circuit 30 shown in FIG. 1A. In the variable frequency dividing circuit 30, when the frequency dividing ratio is varied by the phase difference in the phase comparator 4, A frequency divider circuit that controls one of the L (or H) periods of the received clock to vary the frequency division ratio is used, and the frequency divider circuit 30 and the phase comparator 4 constitute a so-called digital PLL circuit.

For example, the oscillating frequency of the voltage controlled oscillator 10 is now divided by 8 by the variable frequency dividing circuit 30, and the "H" period of the received clock is four pulses and the "L" period is four.
If the number of pulses is equal to the number of pulses, the voltage-controlled oscillator 10 fluctuates and the oscillation frequency becomes slower. As a result, if the edge timing from the received data is earlier, the phase comparator 4 adjusts the timing. The frequency division number of the variable frequency dividing circuit 30 becomes 7 due to the generated phase difference. In this case, the period of the reception clock “H” is 4 pulses and the period of the “L” is 3
Control is performed so as to be equivalent to a pulse. When the oscillation frequency increases, the frequency division number of the variable frequency dividing circuit 30 becomes nine. In this case, the period of “H” of the received clock is four.
Control is performed such that the period of “L” for the pulse is 5 pulses.

A part of the received clock is input to the low-pass filter 6, smoothed by the low-pass filter 6, and input as a control voltage to the voltage-controlled oscillator 10, and the oscillation frequency from the voltage-controlled oscillator 10 is controlled and transmitted. When the clock is slower than the reception clock, the oscillation frequency of the voltage controlled oscillator 10 is increased to synchronize, and when the transmission clock is faster than the reception clock, the oscillation frequency of the voltage controlled oscillator 10 is decreased to be synchronized with the transmission clock. Synchronization with the reception clock can be achieved.

In the above embodiment, when the variable frequency dividing circuit 30 changes the frequency division ratio, an example is shown in which the "L" period of the received clock is controlled. However, the "H" period of the received clock is controlled. Needless to say, the present invention can be similarly implemented by using a variable frequency divider circuit having a negative control voltage characteristic for the voltage controlled oscillator.

[0013]

As described above, the inter-station clock synchronizing circuit of the present invention can form a synchronizing circuit equivalent to the conventional one while simplifying the circuit configuration, and can reduce the size, density, and cost of communication equipment. There is an effect that it becomes possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of the embodiment shown in FIG. 1;

FIG. 3 is a block diagram illustrating an example of a conventional clock recovery circuit.

FIG. 4 is a block diagram showing an example of a conventional inter-station clock synchronization circuit.

[Explanation of symbols]

 2 Fixed frequency divider 4 Phase comparator 5 Edge detector 6 Low-pass filter 10 Voltage controlled oscillator 30 Variable frequency divider

Claims (1)

(57) [Claims] 1. An inter-station clock synchronization circuit for regenerating a reception clock from reception data and synchronizing a transmission clock with the reception clock, means for obtaining a transmission clock from an output of a voltage controlled oscillator via a frequency dividing circuit, A PLL circuit that variably controls the frequency division ratio of the variable frequency divider circuit based on the phase difference between the output obtained by dividing the output of the control oscillator by the variable frequency divider circuit and the edge detection timing obtained from the received data by the edge detection circuit. Means for obtaining a reception clock from the output of the variable frequency dividing circuit; and in the case where the frequency dividing ratio is varied in the variable frequency dividing circuit, any one of a logic "L" period (or a logic "H" period) of the reception clock. Means using a variable frequency divider circuit for controlling one of the above, controlling the oscillation frequency of the voltage controlled oscillator with an output voltage obtained by smoothing the reception clock, and raising the transmission clock. Inter-station clock synchronization circuit, characterized in that it comprises a means for synchronizing the receive clock.