JPH08335932A - Inter-station clock synchronization circuit - Google Patents

Abstract

PURPOSE: To simplify circuit configuration by controlling a voltage controlled oscillator with phase comparison information of a digital PLL circuit controlling a frequency division ratio from received data to recover a received clock. CONSTITUTION: When a variable frequency divider circuit 30 varies a frequency division ratio based on a phase difference by a phase comparator 4, the frequency division ratio is varied by controlling the period of logic 'L' or the period of logic 'H' of a reception clock. Part of the received clock is inputted to an LPF 6, in which the signal is smoothed and inputted to a voltage controlled oscillator 10 as its control voltage. When the speed of the transmission clock is slower than the speed of the reception clock, the oscillating frequency of the oscillator 10 is increased and when the speed of the transmission clock is faster than the speed of the reception clock, the oscillating frequency of the oscillator 10 is decreased to synchronize the transmission clock and the reception clock. Thus, a phase comparator as an analog PLL circuit is not required, and the circuit configuration is simplified to make a communication equipment small, to attain high density and low cost or the like.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inter-station clock synchronization circuit for ensuring synchronization of clock signals of its own station and other stations in digital communication.

[0002]

2. Description of the Related Art In the field of communication in recent years, the digitization of communication lines is advancing. In such digital communication, in order to reduce the communication cost as much as possible in order to reduce the communication cost, it is general to adopt a method of recovering the received clock from the received data without transmitting the clock at the transmitting station. .

FIG. 3 is a block diagram showing the structure of a conventional clock recovery circuit of this type. In FIG. 3, 1 is an oscillator used for both a transmission clock and a reception clock,
Reference numeral 2 is a 1 / N fixed frequency dividing circuit having a frequency dividing ratio N, 3 is a variable frequency dividing circuit, 4 is a phase comparator, and 5 is an edge detecting circuit. The output of the oscillator 1 is the 1 / N fixed frequency dividing circuit 2 and the variable frequency dividing circuit 3
The output from the 1 / N fixed frequency dividing circuit 2 is used as a transmission clock, and the output from the variable frequency dividing circuit 3 is output as a reception clock.

Since the received clock is regenerated from the received data, the received data is input to the edge detection circuit 5 to detect the edge of the received data, and the phase comparator 4 takes the phase difference from the received clock. The phase difference is input to the variable frequency dividing circuit 3 and the frequency dividing ratio of the variable frequency dividing circuit 3 is controlled.
However, in the clock recovery circuit shown in FIG. 3, the transmission clock and the reception clock are not synchronized, and clock synchronization between stations cannot be ensured. Therefore, there is an inter-station clock synchronization circuit configured to synchronize the transmission clock and the reception clock as shown in FIG.

FIG. 4 is a block diagram showing the structure of a conventional inter-station clock synchronization circuit. In the figure, the same symbols as those in FIG. 3 indicate the same or corresponding parts, 6 is a low-pass filter, 7 is a phase comparator, Reference numeral 10 is a voltage controlled oscillator. The inter-station clock synchronization circuit shown in FIG. 4 compares the phases of the transmission clock divided by the 1 / N fixed frequency dividing circuit 2 and the reception clock output from the variable frequency dividing circuit 3 with the phase comparator 7,
A so-called analog PLL circuit that inputs the phase difference as an analog voltage to the voltage controlled oscillator 1 through the low-pass filter 6 and controls the oscillation frequency thereof to synchronize the output of the oscillator 1 with the reception clock reproduced from the reception data is provided. Incorporated.

[0006]

The conventional inter-station clock synchronization circuit as described above requires a phase comparator as an analog PLL circuit, which is an obstacle to miniaturization and high density in composing communication equipment. There was a problem that became.

The present invention has been made to solve the above problems, and an object of the present invention is to provide an inter-station clock synchronizing circuit which can realize a synchronizing circuit equivalent to a conventional circuit while simplifying the circuit configuration. .

[0008]

An inter-station clock synchronizing circuit according to the present invention is a means for obtaining a transmission clock from an output of a voltage controlled oscillator via a frequency dividing circuit, and an output of the voltage controlled oscillator by a variable frequency dividing circuit. A PLL that variably controls the frequency division ratio of the variable frequency dividing circuit based on the phase difference between the frequency-divided output and the edge detection timing obtained from the received data by the edge detection circuit.
A circuit, a means for obtaining a reception clock from the output of the variable frequency dividing circuit, and a case where the frequency dividing ratio is varied in the variable frequency dividing circuit, the period of the logic "L" of the reception clock (or the period of the logic "H"). Means using a variable frequency divider circuit for controlling either one, means for controlling the oscillation frequency of the voltage controlled oscillator by an output voltage obtained by smoothing the reception clock, and synchronizing the transmission clock with the reception clock Is characterized by.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.
In the figure, the same reference numerals as those in FIG. 4 indicate the same or corresponding portions, and 30 is a variable frequency dividing circuit in this embodiment. Figure 2
FIG. 3 is a diagram showing an output waveform of the variable frequency dividing circuit 30 shown in FIG. 1A. In the variable frequency dividing circuit 30, when the frequency dividing ratio is varied by the phase difference in the phase comparator 4, A frequency dividing circuit that controls one of the L (or H) periods of the reception clock to change the frequency dividing ratio is used. The frequency dividing circuit 30 and the phase comparator 4 constitute a so-called digital PLL circuit.

For example, the oscillation frequency of the voltage controlled oscillator 10 is now divided by 8 by the variable frequency dividing circuit 30, and the period of "H" of the reception clock is 4 pulses and the period of "L" is 4 times.
In the case of the number of pulses, the voltage controlled oscillator 10 fluctuates and the oscillation frequency becomes slower. As a result, when the edge timing from the received data becomes earlier, the phase comparator 4 adjusts to this timing. Due to the generated phase difference, the frequency division number of the variable frequency dividing circuit 30 becomes 7. In this case, the period of the reception clock “H” is 4 pulses and the period of “L” is 3 pulses.
Control is performed so that the number of pulses is increased. Further, when the oscillation frequency becomes faster, the frequency division number of the variable frequency dividing circuit 30 becomes 9. In this case, the period of "H" of the reception clock is 4
The control is performed so that the period of "P" and the period of "L" are 5 pulses.

A part of the received clock is input to the low-pass filter 6, smoothed by the low-pass filter 6 and input as a control voltage to the voltage-controlled oscillator 10, the oscillation frequency from the voltage-controlled oscillator 10 is controlled, and transmission is performed. When the clock becomes slower than the reception clock, the oscillation frequency of the voltage controlled oscillator 10 is increased to synchronize with it, and when the transmission clock becomes faster than the reception clock, the oscillation frequency of the voltage controlled oscillator 10 is decreased to become the transmission clock. It can be synchronized with the reception clock.

In the above embodiment, when the variable frequency dividing circuit 30 varies the frequency division ratio, the example in which the period of "L" of the reception clock is controlled is shown. However, the period of "H" of the reception clock is controlled. It goes without saying that the same operation can be performed by using a variable frequency divider circuit having a negative control voltage characteristic as the voltage controlled oscillator.

[0013]

As described above, the inter-station clock synchronizing circuit of the present invention can form a synchronizing circuit equivalent to the conventional one while simplifying the circuit configuration, and downsizing, high density, low cost of communication equipment, etc. There is an effect that it becomes possible.

[Brief description of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of the embodiment shown in FIG.

FIG. 3 is a block diagram showing an example of a conventional clock recovery circuit.

FIG. 4 is a block diagram showing an example of a conventional inter-station clock synchronization circuit.

[Explanation of symbols]

 2 fixed frequency divider circuit 4 phase comparator 5 edge detection circuit 6 low pass filter 10 voltage controlled oscillator 30 variable frequency divider circuit

Claims (1)

[Claims] 1. An inter-station clock synchronization circuit for recovering a reception clock from reception data and synchronizing the transmission clock with the reception clock, a means for obtaining a transmission clock from an output of a voltage controlled oscillator through a frequency dividing circuit, A PLL circuit for varying and controlling the frequency division ratio of the variable frequency dividing circuit based on the phase difference between the output of the controlled oscillator divided by the variable frequency dividing circuit and the edge detection timing obtained from the received data by the edge detecting circuit. A means for obtaining a reception clock from the output of the variable frequency dividing circuit, in the case where the frequency dividing ratio is varied in the variable frequency dividing circuit, any one of the logic "L" period (or the logic "H" period) of the reception clock A means using a variable frequency divider circuit for controlling one of the two, controlling the oscillation frequency of the voltage controlled oscillator with an output voltage obtained by smoothing the reception clock, and increasing the transmission clock. Inter-station clock synchronization circuit, characterized in that it comprises a means for synchronizing the receive clock.