JPH0267034A - Bit synchronizing circuit - Google Patents

Abstract

PURPOSE:To shorten a time required for the establishment of synchronism by resetting a variable frequency divider by detecting the start pulse of an NRZ(Non-Return-to-Zero) signal. CONSTITUTION:The variable frequency divider 5 outputs a reproducing clock by frequency-dividing the output signal of an oscillator 3, however, a start puls detector 7 resets the variable frequency divider 5 when detecting the start pulse of the NRZ signal from a terminal 1, and the variable frequency divider 5 starts the frequency division of the output signal of the oscillator 3 after being reset, then, outputs the reproducing clock. A phase comparator 2 output the reproducing clock and the phase difference signal of the NRZ signal inputted from the terminal 1, and a controller 4 controls the frequency division ratio of the variable frequency divider 5 so as to reduce the phase difference, and takes the synchronism of the reproducing clock. Therefore, since micro initial phase difference exists between the repoducing clock and the NRZ signal compared by the phase comparator 2, the time required for the establishment of the synchronism can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is applicable to TDMA (Time Division).
MultipleAccess) It relates to a t-period circuit used in digital communications, etc.

Conventionally, this type of bit threat period circuit divides the output signal of an oscillator 3 by a variable frequency divider 6 to obtain a recovered clock, as shown in FIG. 1
NRZ (Non-Return-1o-Z) input from
ero ) signal is obtained by a phase comparator 2, and a controller 4 controls the frequency division ratio of a variable frequency divider 5 so that this phase difference is reduced, thereby synchronizing the reproduced clock. ing.

In other words, this type of bit synchronization circuit uses digital P
It is composed of an LL (Phase Locked Loop) circuit.

Problems to be Solved by the Invention However, in the above conventional bit synchronization circuit, the NRZ
Since the initial phase difference between the signal and the recovered clock is not uniform, the time it takes to establish synchronization of the recovered clock is not uniform. TDM that requires synchronization of
There is a problem that it cannot be applied to A communication.

SUMMARY OF THE INVENTION In view of the above conventional problems, an object of the present invention is to provide a bit synchronization circuit that can shorten the time required to establish synchronization.

Means for Solving the Problems In order to achieve the above object, the present invention provides a
The variable frequency divider is reset by detecting the start pulse.

Effect of the present invention With the above configuration, the initial phase difference between the reproduced clock output from the variable frequency divider and the NR and Z signals is small.
The time required to establish synchronization can be reduced.

EXAMPLES Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a bit synchronization circuit according to the present invention, and the same components as those shown in FIG. 2 are given the same reference numerals.

In FIG. 1, 1 is the terminal to which the NRZ signal is input, 2
is a phase comparator that outputs a phase difference signal between the N-Z signal from the terminal 1 and the recovered clock from the variable frequency divider 6, which will be described later;
3 is an oscillator that generates a reference frequency signal; 5 is a variable frequency divider that variably divides the signal from the oscillator 3 to generate a reproduced clock; and 4 is a phase comparator 2; A controller 7 controls the division ratio of the variable frequency divider 5 so that the phase difference signal from the terminal 1 is reduced, and a start controller 7 detects the start pulse of the NRZ signal from the terminal 1 and resets the variable frequency divider 6. It is a pulse detector.

Next, the operation of the above embodiment will be explained.

In FIG. 1, the variable frequency divider 6 divides the frequency of the output signal of the oscillator 3 and outputs a reproduced clock, but when the start pulse detector 7 detects the start pulse of the NRZ signal from the terminal 1, the variable frequency divider Resetting the frequency generator 5 and thus
After being reset, the variable frequency divider 5 starts dividing the output signal of the oscillator 3 and outputs a reproduced clock.

The phase comparator 2 outputs a phase difference signal between this reproduced clock and the NRZ signal input from the terminal 1, and the controller 4 controls the division ratio of the variable frequency divider 6 so that this phase difference is reduced, and the reproduction Synchronize the clocks.

Therefore, the recovered clock that the phase comparator 2 compares with N
Since the initial phase difference of the Z signal is minute, the time required to establish synchronization can be shortened.

As described in detail, the present invention detects the start pulse of the NRZ signal and resets the variable frequency divider. The phase difference is reduced, and therefore the time required to establish synchronization can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a bit synchronization circuit according to the present invention, and FIG. 2 is a block diagram showing a conventional bit synchronization circuit. 2... Phase comparator, 3... Oscillator, 4... Controller, 6... Variable frequency divider, 7... Start pulse detector.

Claims (1)

[Claims] A variable frequency divider generates a recovered clock by variably dividing a reference frequency, and a phase difference between the NRZ signal and the recovered clock from the variable frequency divider is compared, and the variable frequency divider is adjusted so that the phase difference is reduced. A bit synchronization circuit comprising means for controlling a frequency division ratio of a frequency divider, and means for detecting a start pulse of an NRZ signal and resetting the variable frequency divider.