JPH0631795Y2 - Digital signal synchronization circuit - Google Patents

Description

The present invention relates to a digital signal synchronizing circuit, and more particularly to a PCM.
The present invention relates to a bit synchronization circuit for a PCM signal in PCM demodulation of a communication device or the like.

[Conventional technology]

Conventionally, as shown in FIG. 4, a bit synchronizing circuit for a digital signal of this type has a clock synchronized with an input signal n using a phase locked loop including a phase comparator 20, a loop filter 21, a VCO 22 and a frequency divider 23. A signal is generated, the waveform shaping circuit 24 shapes the waveform of the input signal n by this clock, and the output signal S which is a demodulated PCM signal and a clock signal synchronized with this signal are sent.

[Problems to be solved by the invention]

Since the conventional digital bit synchronization circuit described above uses the standard phase-locked loop that controls the VCO 22 in an analog manner by the amount of phase delay / advance with respect to the reference point of the internal clock, the PCM signal The clock cannot be used unless the clock is synchronized with the input signal n. Therefore, there is a drawback that data is lost from the start of PCM signal input to the completion of synchronization, and if there are few change points between 1 and 0 of the input signal n, it is impossible to synchronize, or even if synchronized, it is immediately lost. Also, since the loop filter circuit 21 is required, the circuit becomes complicated.

[Means for solving problems]

The digital signal synchronizing circuit of the present invention includes a change point detection circuit for detecting a change point of an input signal of a digital signal, a first clock having a frequency N times that of the input signal, and a frequency higher than the first clock. A clock oscillation circuit that outputs a second clock; a counter that normally counts the first clock; a multiphase clock generation circuit that is connected to the counter and that generates a multiphase clock synchronized with the input signal; The counter counts the second clock from the change point when the change point of the input signal enters within the first period defined by the multi-phase clock to the first time point defined by the multi-phase clock. To reduce the time width of the multi-phase clock to count the input signal change point within a second period other than the first period. A phase difference detection circuit for synchronizing the first time point defined for the multi-phase clock and a timing adjustment circuit for synchronizing the input signal with a second time point defined by the multi-phase clock. Composed.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. The change point detection circuit 1 detects a change point between "1" and "0" of the input signal n of the PCM. The clock oscillator 2 oscillates a clock (second clock) having a frequency 80 times the frequency of the input terminal n, and the binary counter 7 inputs the clock of the clock oscillator 2 and has a frequency 40 times the frequency of the input signal n. The clock (first clock) is output. The counter 3 is a clock of the clock oscillator 2 via the AND circuit 11 and the third circuit 13 or 2 via the AND circuit 12 and the OR circuit 13.
This is a decimal counter that counts the clock of the decimal counter 7. The counter 4 is a quaternary counter that inputs the output of the counter 3, and the decoder (multi-phase clock generation circuit) 5 decodes the output of the counter 4 to generate the 4-phase clocks C _{0 to} C _3.
Is output. The clocks C _{0 to} C ₃ are counters 4 respectively.
When the value of the output of 0 is 0 to 3, it is output correspondingly.

The AND circuit 15 inputs the clock C ₂ and the signal output by the counter 3 when the count value is 5 to 9, and the OR circuit 1
4 receives the output of the AND circuit 15 and the clock C ₃ . The output of the AND circuit 8 which receives the output of the change point detection circuit 1 and the output of the OR circuit 14 resets the counter 3 to the count value 0 and presets the counter 4 to the count value 3.
The output of the change point detection circuit 1 and the output of the AND circuit 10 that receives the output of the OR circuit 14 via the inverter 9 set the flip-flop 16, and the clock C ₃ resets the flip-flop 16. The OR circuit 11 inputs the output Q of the flip-flop 16 and the clock of the clock starter 2, and the OR circuit 12 inputs the inverted output of the flip-flop 16 and the clock of the binary counter 7. The flip-flop circuit 16 and the AND circuit 8 constitute a phase difference detection circuit.

FIG. 2 is a timing chart showing the operation principle of this embodiment. As shown in FIG. 2 (a), the four-phase clock C ₀
First half cycle of -C ₁ and C ₂ when the change point of the "1" and "0" of the input signal n enters the (first period) in, from the change point rise until the clock C _3, an input The counter 3 counts the clock of the clock oscillator 2 having a frequency of 80 times the signal and shortens it to 1/2 time (compared to the case where the counter 3 counts the clock of the binary counter 7).
When containing the changing point of the input signal n in the second view (b) are shown as the second half cycle -C ₃ cycles of clock C ₂ (the second period), the cycle of the clock C ₃ from the change point To start. That is, the rising edge (first time point) of the clock C ₃ is synchronized with the changing point of the input signal n. The bit signal of the output signal S is output from the timing adjusting circuit 6 in time with the rising edge (second time point) of the clock C ₀ .

FIG. ₃ is a timing chart showing the input signal n, the four-phase clocks C _{0 to} C ₃ and the output signal S until the fourth layer clocks C _{0 to} C ₃ are synchronized with the input signal n. As shown, when the change point 31 of the input signal n there during the clock _{C 0,} the transition points 31 rise until the clock _{C 3} shortened to the clock _C 0 -C ₂ having a width of 1/2 To be done. The next change point 32 enters the clock C ₁ and the width of the clock is shortened to ½ even from the next change point 32 to the rise of the clock C ₃ . The next change point 33 is the clock C ₂
Since the latter half cycle of the clock C ₃ is entered, the change point 33 is preset so that the rising edge of the clock C ₃ comes. From then on, the changing point of the input signal n is synchronized with the rising edge of the clock C ₃ .

In the timing chart of FIG. 3, the rising edge of C ₀ of the 4-phase clock is 1 during the 1-bit period of the input signal n.
It appears only once, and it always appears once. Therefore, the timing of the input signal is re-adjusted by the rise of the clock C ₀ , so that the four-phase clocks C _{0 to} C ₃ are input signal n
Even when not synchronized with, the PCM signal synchronized with the four-phase clocks C _{0 to} C ₃ is output.

Of course, the 1-bit width of this output signal is 4 phase clock C ₀
Which vary according to the length of ~C _3.

In this embodiment, the period of clocks C _{0 to} C ₂ is delayed with respect to the change point of the input signal n of “1” and “0” with respect to the rising edge of the clock C ₃ to accelerate the frequency of the 4-phase clock. , The period of the clock C ₃ is advanced, the start of the period of the clock C ₃ is adjusted to the changing point of the input signal n, and the phase adjustment is performed only in the period in which the changing point of the input signal n is matched. P transmitted in bursts
It is possible to perform bit demodulation on the CM signal without loss of 1 bit.

[Effect of device]

INDUSTRIAL APPLICABILITY As described above, according to the present invention, it is possible to demodulate a PCM signal transmitted in bursts without bit loss of 1 bit, and by using an internal oscillation frequency that matches the input signal frequency. Even if it is "1" or "0" for a long period of time, out-of-synchronization is unlikely to occur, and because it is composed entirely of digital circuits, if only the oscillation frequency is made variable, it can be used for a wide range of input frequencies. However, there is an effect that demodulation is possible and an effect that the circuit is simplified because a loop filter is not used.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing chart showing the operation of the embodiment shown in FIG.
FIG. 3 is a timing chart for explaining the operation leading to the synchronization between the input signal n and the four-phase clock in the embodiment shown in FIG. 1, and FIG. 4 is a block diagram of a conventional digital signal synchronizing circuit. 1 ... Change point detection circuit, 2 ... Clock oscillator, 3, 4
...... Counter, 5 …… Decoder, 6 …… Timing adjustment circuit, 7 to binary counter, 16 …… Flip-flop,
20 ... Phase comparator, 21 ... Loop filter, 22 ...
... VCO, 23 ... frequency divider, 24 ... waveform shaping circuit.

Claims (1)

[Scope of utility model registration request] 1. A change point detection circuit for detecting a change point of an input signal of a digital signal, a first clock having a frequency N times that of the input signal, and a second clock having a frequency higher than the first clock. A clock oscillating circuit that outputs a clock, and a counter that normally counts the first clock,
A multi-phase clock generation circuit connected to this counter for generating a multi-phase clock synchronized with the input signal, and the change when the change point of the input signal enters within a first period defined by the multi-phase clock. From the point to the first time point defined by the multi-phase clock, the second clock is caused to count by the counter to shorten the time width of the multi-phase clock and the second period other than the first period. A phase difference detection circuit that presets the counter when the change point of the input signal is within and synchronizes the first time point defined for the multiphase clock, and the input signal is defined by the multiphase clock. And a timing adjusting circuit for synchronizing with a second time point.