JPH10206570A - Time synchronizing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize accurate time synchronization with a simple synchronizing control without providing highly stable oscillator. SOLUTION: A time synchronizing system is constituted so that a time synchronizers 10 and 20 performing synchronizing control based on a reference clock are connected face to face via a transmission path 30 and the facing time synchronizers 10 and 20 and is used in a digital synchronizing net. Without containing a reference clock oscillation circuit generating reference clock in each time synchronizer 10 and 20, a reference clock forming means 11 and 21 forming reference clock signals S11 and S21 based on the clock from digital clock suppliers 40 and 50 used for synchronizing the digital synchronizing net is provided. By this, highly accurate reference pulse S11 and S21 can be obtained with a simple constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time synchronization system having a time synchronization device which can be used for time synchronization between distributed stations connected by a wide area digital synchronization network. More specifically, the present invention relates to a time synchronization system that performs time synchronization using a clock from a digital clock supply device that is used as a standard in current digital synchronization networks.

[0002]

2. Description of the Related Art Conventionally, this kind of time synchronization system has been used for time synchronization between distributed stations connected by a wide area digital synchronization network. As this time synchronization system, a system in which time synchronization is performed between two time synchronization devices connected to each other via a transmission line or a plurality of time synchronization devices connected to a transmission line There is known a device in which time synchronization devices are synchronized. By applying such a time synchronization system, time synchronization or timing synchronization is achieved between remote communication stations.

Incidentally, a time synchronization device used in these time synchronization systems needs to incorporate a reference clock oscillation circuit having a certain degree of stability according to an allowable synchronization error. Further, in order to further reduce the time synchronization error between the communication stations, replace the reference clock oscillation circuit with a more stable oscillator, or frequently perform synchronization control based on signal transmission between the communication stations. Needed.

[0004]

According to such a conventional time synchronization system, when a highly stable oscillator is built in the time synchronization apparatus in order to reduce the time synchronization error between communication stations. However, there is a drawback that the apparatus configuration is duplicated with a high-stable frequency synchronization clock oscillator (network synchronization clock oscillator) in the current digital synchronization network, which is uneconomical and complicated in operation.

Further, in a conventional time synchronization system,
When frequent synchronization control is performed, it is necessary to increase the capacity of a signal transmission circuit between communication stations, and in addition, there is a disadvantage that synchronization control is complicated.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a time synchronization system capable of performing highly accurate time synchronization with a simple synchronization control without providing a highly stable oscillator.

[0007]

To achieve the above object, a time synchronization system according to the first aspect of the present invention comprises:
A time synchronizer that includes a reference clock oscillating circuit that oscillates a reference clock and that performs synchronization control based on the reference clock from the reference clock oscillating circuit is connected to each other via a transmission line so that time is synchronized between the opposed time synchronizers. A time synchronization system used in a digital synchronization network in which synchronization or a plurality of time synchronization devices are connected to a transmission line so that time synchronization is performed between the time synchronization devices. Instead of the reference clock oscillation circuit, reference clock forming means for forming a reference clock signal based on a clock from a digital clock supply device used for synchronization of a digital synchronization network is provided.

Therefore, according to the first aspect of the present invention, the reference clock forming means inside the time synchronizing device receives the highly stable oscillation clock of the digital clock supply device, and generates the reference clock signal depending on the clock. Form.

According to a second aspect of the present invention, the digital clock supply device of the time synchronization system according to the first aspect is a cesium atomic oscillator, a rubidium oscillator, or a digital phase locked loop controlled crystal oscillator. Things.

Further, in the invention according to claim 3, the reference clock forming means compares the phase of the input clock from the digital clock supply device with the phase of a feedback signal formed based on the reference clock signal to control the control voltage. And means for forming a reference clock signal based on the control voltage.

Further, in the invention according to claim 4, the reference clock forming means is a feedback signal formed by mixing an input clock from the digital clock supply device with a reference clock signal and an oscillation frequency of an offset crystal oscillator. And a means for forming a control voltage by comparing the phase with the control voltage and forming a reference clock signal based on the control voltage.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of the present invention will be described below in detail based on an embodiment shown in the drawings.

FIG. 1 shows an embodiment of a time synchronization system according to the present invention. The time synchronization system of this embodiment is of a mutual synchronization type, in which time synchronization devices 10 and 20 are connected to each other via a transmission line 30 and time synchronization between the time synchronization devices 10 and 20 is established. Synchronize the time by transmitting the reference pulse, measuring the time from transmitting the pulse of the own station to receiving the pulse of the partner station, and controlling the pulse transmission timing so that the measured times of both stations match. It is configured as follows.

[0014] To further explain, the time synchronization system comprises:
Time synchronization devices 10 and 20 and a transmission line 30 are provided, and the time synchronization device 10 is connected to the time synchronization device 20 via the transmission line 30. In addition, the time synchronization devices 10 and 20 include:
From each digital clock supply device 40, 50 used in the external digital synchronous network, a network synchronous clock S1 is output.
0 and S20 are provided. Note that the digital clock supply devices 40 and 50
Cesium atomic oscillator (frequency accuracy 10-12 or less),
Ruby oscillator (frequency accuracy of 10-9 or less) or digital phase locked loop (PLL; Phase-Locked L)
oop) A clock dependent on the master clock from a control crystal oscillator or the like can be supplied.

Here, the time synchronizer 10 includes a reference clock forming means 11, a transmitting circuit 12, a receiving circuit 13,
It consists of a time interval counter 14 and is connected as follows.

The reference clock forming means 11 is provided so as to receive the network synchronization clock S10 from the digital clock supply device 40. The reference clock forming means 11 forms the reference time clock S11 based on the network synchronization clock S10. The output of the reference clock forming means 11 is connected to the input terminals of the transmission circuit 12 and the time interval counter 14, and the reference time clock S11 is provided so as to be input thereto. The transmission circuit 12 transmits the reference time clock S11 and the measured time data S14 to the transmission signal S based on the reference time clock S11.
12 is provided so that it can be transmitted to the receiving circuit 23 of the partner station 20 via the transmission line 30. The receiving circuit 13
Time pulse S2 of the other station based on reference time clock S11
2 is provided. The time interval counter 14 is provided so as to measure the measurement time (measured transmission delay time) from the reference time clock S11 and the time pulse S22 of the partner station to obtain the measurement time data S14.

The time synchronizing device 20 includes a reference clock forming means 21, a transmitting circuit 22, a receiving circuit 23, a time interval counter 24, an arithmetic circuit 25, and a phase control circuit 26. Have been.

The reference clock forming means 21 is configured to be supplied with the network synchronization clock S20 from the digital clock supply device 50. The reference clock forming means 21 is provided so as to form a reference time clock S21 from the network synchronization clock S20. An output terminal of the reference clock forming means 21 is connected to an input terminal of the phase control circuit 26. The phase control circuit 26 can control the phase of the reference time clock S21 from the reference clock forming means 21. Phase control circuit 26
Output terminal is a transmission circuit 22 and a time interval counter 24.
, And is provided so that the time pulse S26 from the phase control circuit 26 is supplied. Transmission circuit 2
2 is a time pulse S synchronized with the reference time clock S21.
The transmission signal S22 is provided so as to be able to be transmitted based on the transmission signal S26. The receiving circuit 23 forms a reference time pulse S23 from the transmission data S12. Then, the reference time pulse S2
3 so that measurement time data S14 measured by the time synchronization device 10 can be obtained. The time interval counter 24 is provided so as to obtain a measured time data S24 by measuring a delay time (measured transmission delay time) from the reference time pulse S26 and the reference time pulse S23 of the partner station. The arithmetic circuit 25 includes the measurement time data S14 measured by the time synchronization device 10 and the measurement time data S24 measured by the time interval counter 24.
The control signal S25 can be formed on the basis of the above and supplied to the phase control circuit 26. In the phase control circuit 26,
By controlling the phase of the reference clock S21 from the reference clock forming means 21 based on the control signal S25, it is possible to obtain a time pulse S26 which has the same measurement time and is synchronized with the reference time.

The configuration and operation of the reference clock forming means 11 and 21 will be described later.

The operation of the embodiment configured as described above will be described.

First, in the time synchronizer 10 serving as a time reference station (upper station), a time pulse synchronized with the reference phase (reference time) of the reference time pulse S11 output from the reference clock forming means 11 is input to the transmission circuit 12. I do. The time pulse S11 from the reference clock forming means 11 is input to the time interval counter 14, and the time pulse S11
The operation of the time measurement is performed according to.

A transmission line 30 is transmitted from the opposing time synchronizer 20.
The transmission signal S2 of the time pulse S26 transmitted through
2 is received by the receiving circuit 13 of the time synchronization device 10.
The receiving circuit 13 obtains a reception pulse S13 from the transmission signal S22 and outputs it. This reception pulse S1
3 is input to the time interval counter 14. The time interval counter 14 measures the time interval (transmission delay) between the time pulse S11 and the reception pulse S13 from the opposing time synchronization device 20.

The measurement time data S 14 measured by the time interval counter 14 is input to the transmission circuit 12. The transmission circuit 12 transmits the measurement time data S14 together with the time pulse S11 to the opposing time synchronization device 20 via the transmission line 30 as a transmission signal S12.

On the other hand, in the time synchronizer 20 serving as a dependent station, the time pulse S26 from the phase control circuit 26 is transmitted by the transmission circuit 22 to the opposing time synchronizer 10 through the transmission line 30 as a transmission signal S22. At the same time, a time pulse S26 is input to the time interval counter 24.

The receiving circuit 23 of the time synchronizing device 20 receives the transmission data S12 sent from the opposing time synchronizing device 10. The reception circuit 23 forms a reception pulse S23 from the transmission data S12 and obtains measurement time data S14. This reception pulse S23 is
It is input to the time interval counter 24. Same counter 24
Is the time interval (transmission delay) between its own time pulse S26 and the received pulse S23 from the opposing time synchronizer 10.
Is measured. The measurement time data S24 measured by the time interval counter 24 is input to the arithmetic circuit 25.

In the arithmetic circuit 25, its own time synchronizing device 2
The measured time data S24 measured at 0 is compared with the measured time data S14 measured at the opposing time synchronization device 10, and a control signal S25 corresponding to the difference between them is formed. This control signal S25 is input to the phase control circuit 26.

The phase control circuit 26 controls the phase of the time pulse S21 from the reference clock forming means 21 in accordance with the control signal S25, so that the opposing time synchronization device 1
A pulse S26 synchronized with the zero reference time pulse S11 can be obtained.

Therefore, the time synchronizing device 10 can output the reference time pulse S11, and the time synchronizing device 20 can output the pulse S26 synchronized with the reference time of the reference time pulse S11.

As described above, in the present embodiment, the digital clock supply device 4 used in the digital synchronous network is used.
The network synchronization clocks S10 and S20 of 0 and 50 are taken into the time synchronization devices 10 and 20, and the reference clock forming means 11 and 21 in the time synchronization devices 10 and 20 generate reference time pulses S11 and S11 based on the network synchronization clocks S10 and S20. Since S21 is formed, there is no need to provide a highly stable oscillator inside the time synchronization devices 10 and 20, and a device that overlaps with a highly stable frequency synchronization clock oscillator (network synchronization clock oscillator) in a digital synchronization network. It does not become a configuration,
It has the advantage of being economical and easy to operate.

Further, according to the above time synchronization system, it is not necessary to perform frequent synchronization control, there is no need to increase the capacity of the transmission circuit, and the synchronization control is simplified.

Therefore, a highly accurate time synchronization system can be provided even with a time synchronization device having a simple configuration.

Next, FIG. 2 and FIG. 3 show examples of the configuration of the reference clock forming means when the network synchronization clock and the internal reference clock are integral multiples of each other. In the following description, only the configuration of the reference clock forming unit 11 of the time synchronization device 10 will be described, and the description of the reference clock generation unit 21 of the time synchronization device 20 will be omitted since the configuration is the same.

FIG. 2 shows that the frequency of the network synchronization clock S10 inputted to the reference clock forming means 11 is higher than the frequency of the reference time clock S11 outputted from the reference clock forming means 11, and that both clocks S10 and S11 are mutually connected. 5 shows a circuit capable of outputting a reference time clock S11 having a relationship of an integral multiple.

In this figure, reference clock forming means 1
1 is a phase detector 111, a loop filter 112,
A voltage controlled oscillator 113 and a frequency divider 114 are provided.

That is, the network synchronization clock S10 from the digital clock supply device 40 is supplied to the input terminal of the phase detector 111. The phase detector 111 is provided so that the phase between the network synchronization clock S10 and the feedback signal Fs can be detected. The phase detector 111 is connected to the loop filter 112, and the output is input to the loop filter 112. The loop filter 112 can form a voltage signal from the phase detected by the phase detector 111. The output terminal of the loop filter 112 is connected to the voltage controlled oscillator 113. The voltage controlled oscillator 113
It is provided so that a pulse can be formed based on the voltage signal from the loop filter 112. This voltage controlled oscillator 1
13 is connected to a comparison terminal of the phase detector 111, so that the feedback signal F is sent to the phase detector 111.
s can be supplied. The output of the voltage controlled oscillator 113 is also connected to the frequency divider 114. This frequency divider 114 can output a reference time clock S11.

According to the reference clock forming means 11,
It works as follows. Digital clock supply device 40
Is supplied to the phase detector 111. In the phase detector 111, the clock S10 from the digital clock supply device 40 and the voltage-controlled oscillator 113
The phase difference from the feedback signal Fs is detected.
The phase difference output detected by the phase detector 111 forms a voltage signal by the loop filter 112. The output voltage from the loop filter 112 is supplied to a voltage controlled oscillator 113. The voltage controlled oscillator 113 forms a pulse based on the voltage signal from the loop filter 112. This pulse is input to the comparison terminal of the phase detector 111 as a feedback signal Fs. This pulse is converted into a reference time pulse S11 by the frequency divider 114.

Next, referring to FIG.
a is lower than the frequency of the reference time clock S11 output from the reference clock forming means 11a, and both clocks S10, S
11 are reference time clocks S1 having an integer multiple relationship with each other
1 shows a circuit capable of outputting 1.

The reference clock forming means 11a shown in FIG.
The voltage-controlled oscillator 113 is connected to the comparison terminal of the phase detector 111 via the frequency divider 115,
13 is input to the phase detector 111 via the frequency divider 115. This reference clock forming means 11a
The frequency divider 114 is omitted, and the other configuration is the same as the circuit configuration of FIG.

According to the reference clock forming means 11a, the frequency of the network synchronization clock S10 input to the reference clock forming means 11a is
Can output a reference time clock S11 whose frequency is lower than the frequency of the reference time clock S11 output from the CPU and the two clocks S10 and S11 are in an integer multiple of each other.

FIGS. 4 and 5 show examples of the configuration of the reference clock forming means 11b when the network synchronization clock S10 and the internal reference clock do not become integral multiples of each other. In the following, only the configuration of the reference clock forming means 11 of the time synchronization device 10 will be described.
The description of the reference clock forming means 21 is omitted because it has the same configuration.

FIG. 4 shows that the frequency of the network synchronization clock S10 input to the reference clock forming means 11b is the same as the reference time clock S1 output from the reference clock forming means 11b.
1 shows a circuit that can output a reference time clock S11 higher than the frequency of 1 and both clocks S10 and S11 do not have an integral multiple relationship with each other.

In FIG. 4, reference clock forming means 11
b is a phase detector 111, a loop filter 112,
Voltage-controlled oscillator 113, frequency divider 114, mixer 1
16 and an offset crystal oscillator 117, and are configured as follows.

The network synchronization clock S 10, which is an output signal of the digital clock supply device 40, is provided so as to be supplied to the phase detector 111. The phase detector 111 detects the phase between the network synchronization clock S10 from the digital clock supply device 40 and the feedback signal Fs. The output terminal of the phase detector 111 is connected to the loop filter 112. Also, the loop filter 112
Is provided to convert the phase detected by the phase detector 111 into a voltage signal. Furthermore, loop filter 1
The output terminal 12 is connected to the input terminal of the voltage controlled oscillator 113. The voltage controlled oscillator 113 is provided so as to form a pulse based on the voltage signal from the loop filter 112. This voltage controlled oscillator 113
Are connected to the input terminals of the mixer 116 and the frequency divider 114, respectively. The mixer 116 is provided so as to form a feedback signal Fs by mixing a reference clock from the voltage controlled oscillator 113 and a clock from the offset crystal oscillator 117. The output terminal of the mixer 116 is connected to the comparison terminal of the phase detector 111, so that the feedback signal Fs generated by the mixer 116 can be supplied to the phase detector 111.

According to the reference clock forming means 11b, the following operation is performed. The clock S10 from the digital clock supply device 40 is supplied to the phase detector 111. The phase detector 111 detects a phase difference between the clock S10 from the digital clock supply device 40 and the feedback signal Fs from the mixer 116. The phase difference output detected by the phase detector 111 is converted into a voltage signal by the loop filter 112. This output voltage is supplied to the voltage controlled oscillator 113. The voltage control oscillator 113 forms a time pulse based on the voltage signal from the loop filter 112, and
16 respectively.

In the mixer 116, the voltage controlled oscillator 11
3 and the clock from the offset crystal oscillator 117 are mixed to form a feedback signal Fs. This feedback signal Fs is supplied to the phase detector 111
Is supplied to the comparison terminal of

According to the reference clock forming means 11b, the frequency of the network synchronization clock S10 inputted to the reference clock forming means 11b is
The reference time clock S11, which is higher than the frequency of the reference time clock S11 output from the CPU 1 and in which the two clocks S10 and S11 do not have an integer multiple relationship with each other, can be obtained.

FIG. 5 shows the reference clock forming means 11.
c, the frequency of the network synchronization clock S10 is lower than the frequency of the reference time clock S11 output from the reference clock forming means 11c, and both clocks S10, S10
11 are reference time clocks S1 that are not integral multiples of each other
1 shows a circuit capable of outputting 1.

The reference clock forming means 11c shown in FIG.
Is connected to the comparison terminal of the phase detector 111 via the frequency divider 115, and the output of the mixer 116 is input to the phase detector 111 via the frequency divider 115.
This reference clock forming means 11c is provided with the frequency divider 11 shown in FIG.
4 is omitted, and the other configuration is the same as the circuit configuration of FIG.

According to the reference clock forming means 11c, the frequency of the network synchronization clock S10 input to the reference clock forming means 11c is
Can output a reference time clock S11 that is lower than the frequency of the reference time clock S11 output from the CPU and that the two clocks S10 and S11 do not have an integral multiple relationship with each other.

The above embodiment is an example of a preferred embodiment of the present invention, but the present invention is not limited to this, and various modifications can be made without departing from the gist of the present invention. For example, in each embodiment, the time synchronization device 10 and the time synchronization device 20 have mainly been described as being opposed to each other.
The present invention is not limited to this, and a configuration in which a plurality of time synchronizers are connected to the transmission path 30 and time synchronization is performed among the plurality of time synchronizers may be adopted.

[0051]

As described above, according to the time synchronization system according to the first aspect of the present invention, the network synchronization clock of the digital clock supply device currently used in the digital synchronization network is taken into the time synchronization device. Since the reference time pulse is formed based on the network synchronization clock by the reference clock formation means in the time synchronization device, the following effects are obtained.

(A) It is not necessary to provide a high-stable oscillator, and the apparatus configuration is not duplicated with a high-stable frequency synchronization clock oscillator (digital synchronization network clock oscillator) in a digital synchronous network. Becomes easier.

(B) It is not necessary to perform frequent synchronization control, and it is not necessary to increase the capacity of the transmission circuit.
Synchronization control is simplified.

(C) A highly accurate time synchronization system can be provided even with a time synchronization device having a simple configuration.

According to the second aspect of the present invention, since a clock formed by using a cesium atomic oscillator, a rubidium oscillator, or a digital PLL controlled crystal oscillator is used as a digital clock supply device, a highly accurate clock can be obtained. Can be obtained.

According to the third aspect of the present invention, the reference clock signal is formed based on the control voltage formed by comparing the phase of the input clock from the digital clock supply device with the phase of the feedback signal formed based on the reference clock signal. Therefore, it is possible to obtain a reference clock signal in which the input clock from the digital clock supply device and the reference clock signal have an integer multiple of each other.

According to the present invention, the control clock formed by comparing the phases of the input clock from the digital clock supply device and the feedback signal formed by mixing the oscillation frequency of the reference clock signal and the oscillation frequency of the offset crystal oscillator. Since the reference clock signal is formed based on the voltage, it is possible to obtain a reference clock signal in which the input clock from the digital clock supply device and the reference clock signal do not have an integer multiple relationship with each other.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a first configuration example of a reference clock forming means used in the embodiment.

FIG. 3 is a block diagram showing a second configuration example of the reference clock forming means used in the embodiment.

FIG. 4 is a block diagram showing a third configuration example of the reference clock forming means used in the embodiment.

FIG. 5 is a block diagram showing a fourth configuration example of the reference clock forming means used in the embodiment.

[Explanation of symbols]

10, 20 time synchronizer 11, 11a, 11b, 11c, 21 reference clock forming means 12, 22 transmitting circuit 13, 23 receiving circuit 14, 24 time interval counter 25 arithmetic circuit 26 phase control circuit 111 phase detector 112 loop filter 113 Voltage controlled oscillator 114, 115 Divider 116 Mixer 117 Offset crystal oscillator 30 Transmission line 40, 50 Digital clock supply device

Claims (4)

[Claims] 1. A time synchronization device comprising a reference clock oscillation circuit for oscillating a reference clock and performing synchronization control based on a reference clock from the reference clock oscillation circuit is connected to each other via a transmission line and connected to each other. A time synchronization system used in a digital synchronization network in which time synchronization is performed between devices, or in which a plurality of the time synchronization devices are connected to a transmission path and time synchronization is performed between the time synchronization devices, Each time synchronizer is provided with reference clock forming means for forming a reference clock signal based on a clock from a digital clock supply device used for synchronization of a digital synchronization network, instead of the reference clock oscillation circuit. The time synchronization system characterized by the above. 2. The time synchronization system according to claim 1, wherein said digital clock supply device is a cesium atomic oscillator, a rubidium oscillator, or a digital phase locked loop controlled crystal oscillator. 3. The reference clock forming means compares a phase of an input clock from the digital clock supply device with a phase of a feedback signal formed based on the reference clock signal to form a control voltage, and generates the control voltage. 2. A time synchronization system according to claim 1, further comprising means for forming a reference clock signal based on the time synchronization signal. 4. The reference clock forming means compares the phase of an input clock from the digital clock supply device with the phase of a feedback signal formed by mixing the reference clock signal and the oscillation frequency of an offset crystal oscillator. 2. A time synchronization system according to claim 1, further comprising means for forming a control voltage and forming a reference clock signal based on said control voltage.