KR100560434B1 - Apparatus for providing system clock synchronized to network universally - Google Patents

Abstract

A network synchronizer reference signal generator for receiving at least one reference signal from a communication network according to the present invention, selecting one of the divided reference signals, and dividing them to output a network synchronizer reference signal; A network synchronizer that receives the reference signal for the network synchronizer and the first clock pulse, and outputs a first control voltage for synchronizing the first clock pulse with the reference signal for the network synchronizer; An OVCXO outputting the first clock pulse whose phase and frequency are changed in accordance with the first control voltage; A system synchronization reference signal generator for outputting a system synchronization reference signal for synchronizing the system clock by dividing the first clock signal after receiving the first clock signal; A system synchronous control unit which receives the system synchronization reference signal and a system clock and outputs a second control voltage for synchronizing the system clock with the system synchronization reference signal; A VCO outputting a second clock pulse whose phase and frequency are changed according to the second control voltage; And a system clock generating unit for dividing the second clock pulse after receiving the second clock pulse to output the system clock, and using a commercial OVCXO without using an OVCXO having a system specific frequency characteristic. Can be applied to all systems that need it.

Network Sync, System Sync, OVCXO, VCO, Universal System Clock Supply

Description

Apparatus for providing system clock synchronized to network universally}

1A to 1B are diagrams illustrating a configuration of a conventional network synchronization system clock supply device.

Figure 2 is a block diagram showing a block of a general-purpose network synchronization system clock supply apparatus according to the present invention.

3 is a block diagram illustrating a detailed configuration of a network synchronization controller in the configuration of FIG. 2.

4 is a block diagram illustrating a detailed configuration of the system synchronization controller of FIG. 2.

<< Explanation of symbols for main part of drawing >>

210: network reference signal generator for generating a network synchronization reference signal

220: network synchronization control unit

230: Ovenized Voltage Controlled Crystal Oscillator (OVCXO)

240: System synchronization reference signal generator for generating a system synchronization reference signal

250: system synchronization control unit

260: Voltage Controlled Crystal Oscillator (VCO)

270 system clock generator

310: first comparison signal generator for generating a comparison signal for network synchronization

320: digital phase and frequency detector

330: DPRAM

340: control unit consisting of a microprocessor

350: Digital to Analog Converter (DAC)

410: system synchronization comparison signal generation unit for generating a system synchronization comparison signal

420: analog phase and frequency difference detector

430 low pass filter (LPF)

The present invention relates to an apparatus for supplying a general-purpose network synchronization system clock which is applied to all systems operating in synchronization with a network, and supplies a system clock synchronized with the network.

The system clock supply apparatuses of a system operating in conjunction with a conventional network are configured as shown in FIG. 1A to directly supply a system clock to a network reference signal received from an external network, and separately provided when a network reference signal fails. The system clock was supplied to the system by synchronizing the system clock to a backup clock source (a general purpose oscillator that satisfies the accuracy and stability of the clocks per network level) .However, the quality of the system clock greatly depends on the external environmental factors of the network. By operating independently from the reference signal, data loss occurs when a network reference signal fails.

In order to compensate for this, as shown in FIG. 1B, a backup clock source (general-purpose OVCXO that satisfies the accuracy and stability of clocks per network level) having a system inherent frequency characteristic is manufactured and used for system clock generation, that is, a backup clock. The system clock is generated by synchronizing the source directly with the network reference signal received from the external network, and when the network reference signal fails, the oscillation frequency of the backup clock source in normal operation is maintained so that the network reference signal fails. In this case, data loss does not occur for a certain period of time.

However, this case also did not solve the problem that the design of the network synchronization controller is independent from system to system, and the system development period is lengthened in that a separate clock source for each system has to be manufactured due to the difference in system specific frequency characteristics. There was a disadvantage in that the system cost increased.

The technical problem to be achieved by the present invention is to solve the conventional problems as described above, instead of a backup clock source having a system-specific frequency characteristics 10MHz or 5MHz frequency characteristics and 1X10 ^-7 widely used in communication and measurement equipment, etc. System clock synchronized with a network synchronizer using a universal OVCXO with high accuracy characteristics up to 5X10 ^-10 as a backup clock source and a system synchronizer using a multi-GHz VCO with a wide frequency range of 1X10 ^-3 or more The present invention provides a general-purpose network synchronization system clock supply device configured to supply a system clock synchronized to a network by configuring a supply device and applying it to all systems operating in synchronization with the network.

In order to achieve the above technical problem, the general-purpose network-synchronized system clock supply apparatus according to the present invention receives at least one reference signal from a communication network, selects one of them, divides it, and generates a reference signal for the network synchronizer to output a reference signal for the network synchronizer. part; A network synchronizer that receives the reference signal for the network synchronizer and the first clock pulse, and outputs a first control voltage for synchronizing the first clock pulse with the reference signal for the network synchronizer; An OVCXO outputting the first clock pulse whose phase and frequency are changed in accordance with the first control voltage; A system synchronization reference signal generator for outputting a system synchronization reference signal for synchronizing a system clock by receiving the first clock signal differently according to an operating system; A system synchronous control unit which receives the system synchronization reference signal and a system clock and outputs a second control voltage for synchronizing the system clock with the system synchronization reference signal; A VCO outputting a second clock pulse whose phase and frequency are changed according to the second control voltage; And a system clock generator for outputting the system clock by dividing the second clock pulse after receiving the second clock pulse.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. 2 is a block diagram showing the configuration of a general-purpose network synchronization system clock supply apparatus according to the present invention, and FIG. 3 is a block diagram showing the detailed configuration of the network synchronization control unit in the configuration of FIG. 4 is a block diagram illustrating a detailed configuration of the system synchronization controller of FIG. 2.

First, the network reference signal generator 210 receives a plurality of network reference signals from a communication network, selects and divides one of them, and generates and outputs a network synchronization reference signal. Here, Korean Patent No. 64907 for a network synchronization reference clock board assembly, Korean Patent No. 89836 for a network synchronization input reference clock selection and divider circuit of an electronic exchange, and Korean Patent No. 126856 for a synchronization input reference clock selection device. See.

As shown in FIG. 2, the network synchronizer controller 220 includes a comparison signal generator 310 for a network synchronizer, a digital phase and frequency difference detector 320, a controller 340, and a DAC 350. The network synchronizer control unit 220 receives a network synchronization reference signal from the network synchronizer reference signal generator 210, receives a clock pulse generated and output by the OVCXO 230 below, and applies the reference signal to the network synchronization reference signal. The OVCXO 230 generates and outputs an OVCXO control voltage for synchronizing the clock pulses generated.

That is, the network synchronization comparison signal generator 310 receives the clock pulses generated and output by the following OVCXO 230 and the divider setting values provided by the controller 340, and divides the clock pulses. Generates and outputs a network synchronization comparison signal.

The digital phase and frequency difference detector 320 outputs a network synchronization reference signal output from the network synchronization reference signal generator 210 and a network synchronization comparison signal output from the network synchronization comparison signal generator 310. Each input unit detects and outputs a phase and frequency difference of a network synchronization comparison signal to a network synchronization reference signal as digital values.

The DPRAM 330 records the phase and frequency difference of the network synchronization reference signal with respect to the network synchronization reference signal represented by the digital value output from the digital phase and frequency difference detection unit 320, and then controls the following. Output the recorded value as required by.

Preferably, the controller 340 is implemented as a microprocessor. The controller 340 determines the digital value of the phase and frequency difference received by requesting the DPRAM 330, so that the value is " 0 " A digital voltage value for controlling the OVCXO 230 is generated and output in a direction such that the phase and frequency of the network synchronization reference signal and the network synchronization comparison signal coincide with each other. In addition, the divider set value is provided to the network synchronization comparison signal generator 310.

In addition, the DAC 350 receives a digital voltage value for controlling the OVCXO 230 from the controller 340 and converts the digital voltage value into an analog voltage value for controlling the OVCXO 230 and outputs the same. The OVCXO 230 control voltage for generating and outputting a clock pulse generated by the following OVCXO 230 to the reference signal is generated and output. Korean Patent No. 55805 for the fine phase difference correction circuit and control method, Korean Patent No. 55873 for the slip detection apparatus and method, Korean Patent No. 68841 for the network synchronization and clock supply apparatus of the all-electronic exchange, For the jitter absorption method of the network synchronizer, Korean Patent No. 89837, Korean Patent No. 115667, US Patent No. 5525935, Japanese Patent No. 2653642, and Synchronization Time and Synchronization Korean Patent No. 123067 for digital frequency detectors for adjusting the degree, Korean Patent No. 194805 for digital phase difference detectors using frequency deviation, and Korean Patent No. 0262945 for synchronous control algorithms for digital phase locked loops using transition mode. Reference may be made.

On the other hand, OVCXO 230 is a commercial OVCXO widely used in communication and measurement equipment, has a frequency characteristic of 5MHz or 10MHz and has an accuracy of 1X10 ^-7 to 5X10 ^-10 depending on the position of the system in the network. According to the OVCXO 230 control voltage received from the network synchronization controller 220 generates and outputs a clock pulse whose phase and frequency are changed.

The system synchronization reference signal generator 240 receives a clock pulse generated and output by the OVCXO 230, divides it, and generates and outputs a system synchronization reference signal for synchronizing the system clock according to a system. do. That is, in the case of a voice exchange system, a system synchronization signal of 2.048 MHz or 1.544 MHz frequency series, an 155.520 MHz frequency series in an ATM system, and a 125 MHz frequency series in an Ethernet system is generated and output.

The system synchronization controller 250 includes a system synchronization comparison signal generator 410, an analog phase and frequency difference detector 420, and a low pass filter 430, as shown in FIG. The VCO 260 control voltage for receiving the system synchronization reference signal output from the 240 and the system clock output from the system clock generator 270 described below is input to the system synchronization reference signal. Create and print

That is, the system synchronization comparison signal generator 410 receives the system clock output by the system clock generator 270 below, divides the system clock, and generates and outputs a system synchronization comparison signal.

The analog phase and frequency difference detector 420 is a system synchronization reference signal output from the system synchronization reference signal generator 240 and a system synchronization comparison signal output from the system synchronization comparison signal generator 410. Are respectively input, and detect and output the phase and frequency difference of the system synchronization comparison signal to the system synchronization reference signal as analog values.

The low pass filter 430 operates in such a manner as to output only the low frequency components including direct current by low-pass filtering or integrating the output of the analog phase and frequency difference detection unit 420 to the system synchronization reference signal. The VCO 260 generates and outputs a VCO control voltage for synchronizing clock pulses generated and output.

내지

정도의 주파수 변위폭을 가지며, 상기 시스템 동기 제어부(250)로부터 입력받는 VCO 제어용 전압에 따라 위상 및 주파수가 변경되는 클럭 펄스를 발생시켜 출력한다.VCO 260 is a general-purpose VCO widely used in communication systems and has a frequency characteristic of several GHz.

To

It generates a frequency pulse width of approximately, and generates and outputs a clock pulse whose phase and frequency are changed according to the VCO control voltage received from the system synchronization controller 250.

The system clock generator 270 receives and divides a clock pulse output from the VCO 260 and generates a system clock. The system clock generator 270 is equipped with the system synchronization controller 250 and the clock generator according to the present invention. Output each to the system.

The apparatus for supplying a network synchronization clock according to the present invention described above is not limited to the description of the above-described configuration and the accompanying drawings, and various substitutions, modifications, and changes can be made without departing from the spirit of the present invention. It will be clear.

As described above, the general-purpose network synchronous clock supply apparatus according to the present invention does not use the OVCXO having the system inherent frequency characteristic, but uses the commercial OVCXO having the frequency characteristic of 10 MHz or 5 MHz widely used in communication and measurement equipment. The system can be applied to all systems requiring synchronization, and the system development time and system development cost can be reduced by reducing the time and cost required for OVCXO production and network synchronization. Can be.

In addition, the same VCO can be used for all systems, resulting in price competitiveness through mass production of VCOs.                     

Finally, semiconductor integration is possible so that the volume of the system can be reduced by the integration of system hardware.

Claims (5)

A network synchronizer reference signal generator which receives at least one reference signal from a communication network, selects one of them, divides the signal, and outputs a network synchronizer reference signal; A network synchronizer that receives the reference signal for the network synchronizer and the first clock pulse, and outputs a first control voltage for synchronizing the first clock pulse with the reference signal for the network synchronizer; An OVCXO outputting the first clock pulse whose phase and frequency are changed in accordance with the first control voltage; A system synchronization reference signal generator for outputting a system synchronization reference signal for synchronizing a system clock by receiving the first clock signal differently according to an operating system; A system synchronous control unit which receives the system synchronization reference signal and a system clock and outputs a second control voltage for synchronizing the system clock with the system synchronization reference signal; A VCO outputting a second clock pulse whose phase and frequency are changed according to the second control voltage; And And a system clock generator for outputting the system clock by dividing the second clock pulse after receiving the input of the second clock pulse. According to claim 1, wherein the network synchronizer control unit A comparator comparison signal generator for receiving the first clock pulse and a predetermined divider setting value and dividing the first clock pulse according to the divider setting value to output a comparison signal for a network synchronizer; A digital phase and frequency difference detector which receives the reference signal for the network synchronizer and the comparison signal for the network synchronizer, detects and outputs a phase and frequency difference between the network synchronizer reference signal as a digital value; A DPRAM for recording the phase and frequency difference and outputting the signal at the request of a controller; A controller for requesting and receiving the phase and frequency difference, and outputting the OVCXO control digital voltage value such that the phase and frequency of the network synchronizer reference signal and the network synchronization comparison signal coincide with each other; And And a DAC configured to receive the OVCXO control digital voltage value and convert the digital voltage value to the first control voltage. According to claim 1, wherein the system synchronization control unit A system synchronization comparison signal generation unit which divides the system clock after receiving the system clock and outputs a predetermined system synchronization comparison signal; An analog phase and frequency difference detector for receiving the system synchronization reference signal and the system synchronization comparison signal and detecting and outputting a phase and frequency difference of the system synchronization comparison signal to the system synchronization reference signal as an analog value; ; And a low pass filter for outputting the second control voltage by low pass filtering or integrating the phase and frequency difference. The method of claim 1, wherein the OVCXO Universal network synchronization, characterized in that the accuracy of 1x10 ^-7 to 1x10 ^-10 according to the frequency characteristics of 5MHz to 10MHz and the network hierarchy of the system equipped with the universal network synchronization system clock synchronizer System clock synchronizer. The method of claim 1, wherein the VCO is A general-purpose network synchronization system clock synchronizer having a frequency characteristic in units of gigahertz (GHz) and a frequency shift range of 1x10 ^-3 to 1x10 ^-4 .

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