KR100291004B1 - Frequency offset detection device of input reference signal - Google Patents

Abstract

end. FIELD OF THE INVENTION The present invention relates to a communication system.

I. The technical problem to be solved by the present invention is to provide a frequency offset detection device that can improve the reliability and quality of the device clock by improving the stability of the SDH device clock by detecting the frequency offset of the reference signal input to the digital phase synchronization loop in advance. have.

All. Summary of the Invention: An apparatus for detecting a frequency offset of an input reference signal using a phase-locked loop, in which an input reference signal and an internal oscillation clock are divided into a main clock and a target to be compared with the input reference signal during phase detection. A clock generator for generating and outputting a clock signal, a phase detection controller for generating and outputting signals for controlling phase detection of the input reference signal based on the main clock, and a control signal input from the phase detection controller A phase detector for counting the main clock to detect and output phase error data of the input reference signal, and low-pass filtering the phase error data during an operation cycle period inputted from the phase detection controller, The filtered data is compared with the lock range tolerance of the phase locked loop. T and is characterized in that the filter and for outputting a fault status bit, which consists of a fault detector for a threshold time to input the phase error data and the fault status bits are the input reference signal is detected whether or satisfy a phase-locked condition.

la. Important uses of the invention: It can be used in communication systems such as SDH devices.

Description

Frequency offset detection device of input reference signal

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission system, and more particularly, to a frequency offset detection device for detecting whether a reference signal input to a phase synchronization loop in a clock generation circuit has a value within a phase synchronization loop lock allowable range.

In general, a transmission system incorporates a clock generation circuit as a circuit for matching synchronization timing signals of each node (for example, between switches or nodes). A phase locked loop (PLL) provided in a conventional clock generation circuit is designed in an analog manner, and the PLL designed in the analog manner is used in a pleiochronous digital hierarchy (PDH) scheme or a synchronous digital layer. Hierarchy (hereinafter referred to as "SDH"). And today, digitally designed digital processing phase-locked loops are widely used in SDH devices.

FIG. 1 illustrates an exemplary pulse detection circuit using multivibrator logic. The pulse detection circuit of FIG. 1 using a multivibrator detects the presence or absence of a pulse of a reference signal (hereinafter referred to as an input reference signal) input to the clock generation circuit by setting the time constants of the resistor R1 and the capacitor C1. As described above, in order to detect the presence of the pulse of the input reference signal (8KHz) using the multivibrator, the values of the capacitor C1 and the resistor R1 should be determined first. Each device value range recommended in the data sheet ranges from 1000 [pF] for capacitor C1 and 15 [KΩ] for resistor R1. And the calculation of the time constant used at this time is defined by the following equation (1).

tW = 0.45 × C _EXT × R _EXT

Therefore, half cycle of 8KHz input reference signal with 50% duty is 62.5μsec. Accordingly, in order to detect the presence of the pulse of the 8KHz input reference signal, the time constant must be greater than at least 62.5 μsec. Also consider the tolerances of each device.

FIG. 2 illustrates an operation timing diagram for FIG. 1. In the circuit configuration set by Equation 1, when the input reference signal is applied to the multivibrator 10 in the form of a pulse in section A as shown in Fig. 2, a logic level ″ high ″ is output from the output terminal Q, and B When there is no input reference signal as in the section, a logic level ″ low ″ is output after a set time (D point) from the last pulse of the input reference signal. This operation shows a large difference in accuracy since the output signal is determined at the time when the voltage charged in the capacitor C1 is completely discharged depending on how the time constants of the resistor R1 and the capacitor C1 are set.

However, it is not a problem if only the presence of the pulse of the input reference signal input to the phase synchronization loop in the clock generation circuit using the pulse detection circuit shown in FIG. 1 is not a problem, but the frequency of the input reference signal using the pulse detection circuit is shown. It is not possible to detect the offset. This is because the digital processing phase-locked loop of the transmission system using the SDH method is equipped with a high-voltage VCXO (Voltage Controlled Crystal Oscillator) inside, and the oscillator with such high stability has a lock range of the phase-locked loop. Since it cannot be enlarged, it is necessary to check whether the input reference signal has a value within the lock range allowable range. The lock range of the phase locked loop refers to a frequency range of an input signal in which an output signal of the phase locked loop can be kept synchronized with the input signal.

That is, if an input reference signal outside the lock range is applied to the phase-locked loop of the clock generation circuit, the phase-locked loop loses the lock and performs only the phase capture operation. Therefore, the frequency of the internal oscillator (VCXO) changes rapidly. Accordingly, the transmission system using the SDH method causes an error in data, thereby increasing jitter and slip. Therefore, in order to supply a stable clock frequency to the transmission system, it is necessary to detect in advance whether the frequency of the input reference signal input to the phase synchronization loop in the clock generation circuit is within the lock range allowable range of the phase synchronization loop.

Accordingly, an object of the present invention is to provide a frequency offset detection apparatus capable of checking whether a reference signal input to a phase synchronization loop in a clock generation circuit has a value within a lock range allowable range of the phase synchronization loop.

It is still another object of the present invention to provide a frequency offset detection apparatus capable of increasing the stability of a clock frequency for matching synchronization timing signals between nodes in a transmission system.

It is still another object of the present invention to provide a frequency offset detection device that can improve the reliability and quality of a device clock by detecting the frequency offset of a reference signal input to the digital phase locked loop in advance to increase the stability of the SDH device clock. .

In the present invention for achieving the above object, in the frequency offset detection device of the input reference signal using a phase synchronization loop,

A clock generator for dividing an input reference signal and an internal oscillation clock, respectively, and generating and outputting a main clock and a clock signal to be compared with the input reference signal during phase detection;

A phase detection controller for generating and outputting signals for controlling phase detection of the input reference signal based on the main clock;

A phase detector for controlling an operation according to a control signal input from the phase detection controller and counting the main clock to detect and output phase error data of the input reference signal;

A filter for low-pass filtering the phase error data during an operation cycle period input from the phase detection controller, and outputting a fault status bit by comparing the filtered data with a lock range tolerance of the phase-locked loop;

And a fault detector for inputting the phase error data and the fault status bit to detect whether the input reference signal satisfies a phase fixed condition during a threshold time period.

1 illustrates a pulse detection circuit using multivibrator logic.

2 is an operation timing diagram for FIG. 1.

Figure 3 is a block diagram of a frequency offset detection apparatus according to an embodiment of the present invention.

4 is a detailed configuration diagram of the clock generator 200 of FIG. 3.

5 is a detailed configuration diagram of the phase detection controller 300 in FIG. 3.

6 is a detailed configuration diagram of the phase detector 400 of FIG. 3.

7 is a detailed block diagram of the digital low pass filter 500 of FIG. 3.

8 is a detailed configuration diagram of the fault detector 600 in FIG. 3.

9 is an operation timing diagram of a frequency offset detection apparatus according to an embodiment of the present invention.

Hereinafter, an operation according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram of a frequency offset detection apparatus according to an exemplary embodiment of the present invention, and FIGS. 4 to 8 are detailed block diagrams of respective functional blocks of FIG. 3.

4 to 8 will be described in detail the configuration and interaction of each of the functional blocks constituting the frequency offset detection device according to an embodiment of the present invention in detail.

First, the configuration and operation of the clock generator 200 will be described with reference to FIG. 4. The clock generator 200 located at the input terminal of the frequency offset detection device includes three counters 220, 240, and 260, and a reference clock of 8 KHz and an internal oscillator. Dispense the oscillation clock of 8.192MHz generated at. That is, the counter 3 260 divides 8 KHz reference clocks into 8 KHz reference clocks and outputs the reference clocks of 1 KHz. Each of the counter 1 220 and the counter 2 240 each outputs 2048 of 8.192 MHz clock pulses output from the internal oscillator. The 4KHz and 128KHz clock pulses generated by the division and the 64 division are output to the phase detection controller 30. As such, the 4KHz clock pulse generated from the clock generator 200 is used as a signal to be compared with the reference signal during phase detection, and the 128KHz clock pulse is used as a counter clock constituting the phase detector 400.

Meanwhile, the main clock in the phase detection controller 300 is 128 KHz, and all signal processing is performed based on the main clock of 128 KHz. In the phase detection controller 300, the signals LOAD and STOP for controlling the start and end of the operation of the counter 410 constituting the phase detector 400, and the signals Proce0, which determine the operation cycle of the LPF 500, are determined. Proce1, Proce2: P0, P1, P2 below) and the write signal (write) to control the data to be written to the external D / A converter to generate and output. In more detail, first, the load signal LOAD indicating the start of the operation of the counter 410 constituting the phase detector 400 has a 128KHz reference signal rising edge of 1KHz as shown in FIG. 5. It detects with the main clock and outputs the pulse signal type (logic ″ high ″) for one main clock cycle. The stop signal STOP indicating the end of the operation of the counter 410 detects the rising edge of the 4KHz signal divided from the internal clock pulse as the main clock of 128KHz, as shown in FIG. If the signal LOAD is valid, a logic ″ high ″ pulse is generated for one cycle of the main clock, and after this pulse is generated, a stop signal STOP with logic ″ high ″ during the period in which the input reference signal becomes a logic ″ low ″. Is made.

The signals P0, P1, and P2, which determine the operation cycle of the LPF 500, are delayed by three cycles of the main clock in each of the three D flip-flops 318, 320, and 322 after the stop signal STOP is generated. . Finally, the write signal indicates a logic ″ low ″ in a signal delayed by one cycle of the main clock after the P2 signal transitions to rising, and a pulse signal type that becomes logic ″ high ″ when delayed by two cycles of the main clock. Is made with.

On the other hand, the phase detector 400 includes a loadable 6-bit up counter as shown in FIG. 6 and uses a 128 KHz clock pulse as the main clock. The phase detector 400 operates according to the load signal LOAD and the stop signal STOP output from the phase detection controller 300 to generate and output 6-bit signed data pd. That is, in the phase detector 400, while the load signal LOAD is at the logic ″ high ″, up counting operation of the initial data 16 by +1 is performed by the main clock of 128 KHz, and the stop signal STOP is logic. ″ High ″ keeps the previous value even if the main clock is still entered. The output of these counters is represented by 6-bit signed data pd0 to pd5, and their output values range from -16 to +16. The sign data pd is used as basic data of the LPF 500.

Meanwhile, the LPF 500 illustrated in FIG. 3 is composed of a phase error detector 510, an accumulator 520, a multiplier 530, an adder 540, and a comparator 550 as shown in FIG. 7. Is about 1 Hz. And the signals shown in Figure 7 will be defined as follows.

First, the signal phasedif represents 6-bit signed data, and the signal pd_int represents an integer range (0 to 63). The integral, integral_int, amplifier, adcdata, and cur_val represent the sine data downcounted from 16 to 0, and the signal amp_int represents the integer range from 0 to 65535. The signal adc_uns also represents unsigned data down from 15 to zero.

Hereinafter, the operation according to each configuration of the LPF 500 as the phase detection filter will be described. First, the 6-bit sign data pd is input from the phase detector 400, which is the value counted by the main clock. . When counting as the main clock, an undefined region E is generated between the clock rising edge 0 of the last count value and the next rising edge +1 as shown in FIG. 9. This area also occurs when it is positive. Therefore, an operation is required to eliminate the undefined area E. For this operation, the phase error detector 510 is used to reduce one count value. In defining positive and negative count values, if the reference is made to ″ 0 ″, there is still an undefined area, so the count value ″ 0 ″ is eliminated and the value is increased by +1 for a value greater than ″ 0 ″. give. This limits the reference point for positive and negative values to the rising edge of the count clock.

That is, when the operation cycle signal P0 is ″ 1 ″, the phase error detector 510 increases the sine data pdout by +1 and outputs it to the phasedif port when the sine data pdout is greater than ″ 0 ″, and the sine data pdout is ″. If it is smaller than 0 ″, the input sign data pdout is outputted as phasedif. As a result, the undefined region E shown in FIG. 9 is lost.

Meanwhile, 6-bit sign data outputted to the phasedif port of the phase error detector 510 is applied to the accumulator 520. The operation of the accumulator 520 will be described below. First, when the operation cycle signal P1 is ″ 1 ″, 6-bit sign data input to the phasedif port is integer-converted and output as pd_int, and phasedif and integral_int are added to output as integral. Accumulate sign data.

On the other hand, the multiplier 530 multiplies the input pd_int by 1024 when the operation cycle signal P2 is ″ 1 ″ and sets it to amp_int, and sets integral_int to integral_int as it is when the pulse-on signal is logic ″ high ″. In a situation, set integral to integral_int. The signal cur_val in the multiplier 530 is a value of integral + amplifier, and the value of the amplifier represents a value converted to data wrapped with amp_int. Accordingly, the multiplier 530 amplifies and outputs the sine data output from the accumulator 520 at a predetermined amplification ratio.

Referring to the operation of the adder 540 below, the adder 540 is set to 16 # 8000 # + integral when the pulse ON signal is ″ 1 ″ and 16 # 8000 # + cur_val under other conditions. . That is, the accumulated value and the amplified value are added by the adder 540 and added to the center value 8000 hex of the internal oscillator VCXO and output as data (A / D data) for final A / D conversion.

In addition, the comparator 550 checks whether the input reference signal is within the allowable range. The allowable range may vary depending on the capture range of the internal oscillator, and the input allowable range is set to 85% of the capture range. If the input reference signal is within the allowable range, the status bit is output as logic ″ high ″, and if it is outside the allowable range it is output as logic ″ low ″. That is, the comparator 550 shown in FIG. 7 converts 16-bit adcdata output from the adder 540 into unsigned data, sets it to adc_uns, and the adc_uns is greater than or equal to 16 # e800. If the status bit (fault) is set to ″ 0 ″, or if adc_uns is less than or equal to 16 # 1800 #, then set the status bit to ″ 0 ″; otherwise, set the status bit to ″ 1 ″. do. On the other hand, since the status bit is affected by the glitch caused by the timing delay of the internal logic, the status bit should be retimed and output to the main clock.

Finally, the detailed configuration of the fault detector 600 constituting the frequency offset detection apparatus according to an embodiment of the present invention is as shown in FIG. The fault detector 600 shown in FIG. 8 includes two counters 610 and 620 and a plurality of gate elements. First, the fault detector 600 includes a status bit (fault) output from the LPF 500 and an input pulse status bit (externally input). P _ON ), The sign data pd input from the phase detector 400, and the write signal write from the phase detection controller 300 are used.

Looking at the operation below, the input pulse status bit ( P _ON Indicates " 1 ", indicating that no pulse is present, and the fault detector 600 outputs a fault state (normal = o) by this signal and a status fault. However, there is a pulse P _ON If the status bit (fault) that is the output of the LPF 500 indicates a steady state (fault = 1), the threshold time (1 second) under the phase lock condition (pdout = ″ 111111 ″ or pdout = ″ 0 ″). If it is maintained for, it outputs the normal state (normal = 1). Therefore, it is possible to confirm whether the input reference signal is within the lock range of the clock generation circuit by the logic level of the normal bit.

As described above, the present invention measures the frequency offset of the input reference signal and transfers the input reference signal to the internal phase-locked loop according to the measurement result, so that the hold-over mode before the phase-locked loop of the SDH device clock loses lock. There is an advantage that can be shifted to stabilize the frequency of the SDH device clock. It is also possible to minimize the occurrence of pointer justification inside the SDH device.

Claims (1)

An apparatus for detecting a frequency offset of an input reference signal using a phase locked loop, A clock generator for dividing an input reference signal and an internal oscillation clock, respectively, and generating and outputting a main clock and a clock signal to be compared with the input reference signal during phase detection; A phase detection controller for generating and outputting signals for controlling phase detection of the input reference signal based on the main clock; A phase detector for controlling an operation according to a control signal input from the phase detection controller and counting the main clock to detect and output phase error data of the input reference signal; A filter for low-pass filtering the phase error data during an operation cycle period input from the phase detection controller, and outputting a fault status bit by comparing the filtered data with a lock range tolerance of the phase-locked loop; And a fault detector for inputting the phase error data and the fault status bit to detect whether the input reference signal satisfies a phase fixing condition during a threshold time period.