KR100564242B1 - Apparatus and Method for Clock Stabilization of Synchronous System - Google Patents

Abstract

The present invention relates to a synchronous clock stabilization apparatus and a method of the synchronization system, the synchronous clock stabilization apparatus of the synchronization system generates a reference clock and temporarily stores the generated clock, the reference clock generated in the clock generator And a phase compensator for compensating for a clock that has been changed or delayed based on the output of the phase comparator and a phase comparator comparing the clock fed back from the circuit stage and maintaining the clock continuously when the reference clock is lost. At least one clock compensator, a micro-control unit which determines the clock delay at each circuit stage and controls the phase and delay of the entire system clock, and is individually interlocked with each circuit stage to adjust the clock delay of each circuit stage differently. It includes a clock control unit consisting of one or more skew control unit.

Description

Apparatus and Method for Clock Stabilization of Synchronous System

1 illustrates a typical clock supply flow within a synchronized system.

2 is a block diagram of a preferred embodiment of a synchronous clock stabilization apparatus of a synchronization system according to the present invention;

3 is a block diagram of a DPLL circuit, which is a preferred embodiment of a clock compensator according to the present invention;

* Description of the symbols for the main parts of the drawings *

20: clock generator 21: clock buffer

22: digital phase locked loop (DPLL) 23: skew control unit

24: micro control unit 220: phase comparison unit

221 loop filter 223 voltage controlled oscillator (VCO)

224 Divider

The present invention relates to an apparatus and method for stabilizing a synchronous clock of a synchronization system, and more particularly, to an apparatus and method for stabilizing a synchronous clock of each circuit in a system in a synchronization system such as a communication system or a digital computer. .

An abnormal or unstable clock signal in a digital device can cause system malfunction. In the case of a mobile phone, crosstalk is caused, and distortion of data transmitted from a fax is mostly caused by instability of a clock signal.

As the clock used as the operation source of the digital circuit acts as the heart of the circuit, the accuracy and stability of the frequency are required, and its importance is increasing day by day as the high speed operation and the high speed processing are required. Moreover, in a field where reliability is required such as communication equipment, even if a problem occurs in one clock source, the role is important enough to use a redundant or multiplexed clock to perform normal operation.

1 illustrates a typical clock feed flow in a synchronized system.

As shown in FIG. 1, in a synchronized system, a system and a circuit operate according to a clock for synchronizing. The clock generator 100 includes a clock generator 101 and a clock buffer 102. A synchronous clock is generated by the clock generator 101 generating the clock and supplied to each circuit through the clock buffer 102. . Since synchronization must be made between circuits in the system, the clock generator 101 is one and the same synchronization clock is supplied to each system. Circuits [1, 2 ... n] operate in synchronization with the clock supplied to the system, and each circuit communicates with each other according to the clock.

One example of a conventional digital system is a digital computer system. Digital computer systems have a number of subsystems, such as central processing units (CPUs), random access memory (RAM), and input / output control circuitry for controlling peripherals such as printers and floppy drives. A system clock generator, typically located adjacent to the CPU, generates a global or master clock signal from which multiple synchronous system clock signals are derived. These system clock signals are provided to each subsystem, eg, CPU or RAM. The system clock generator also provides a peripheral clock signal to drive the I / O control circuit.

In such a synchronized system, when the synchronous clock is lost or the synchronous clock of each circuit stage is not matched, data loss occurs because the transmitter or the receiver does not correctly recognize the data. Also, if only one bit is lost in each circuit stage, system operation stops or system malfunctions. That is, in the case where the same synchronous clock is supplied to several circuit terminals in one system, there is a problem that signal distortion and system failure occur due to phase mismatch between system clocks.

In order to solve the problems of the prior art as described above, the present invention provides a more stable system operation by matching the synchronization of the clock supplied to each circuit stage by disposing a clock compensation device between the clock generator and each circuit stage. An object of the present invention is to provide a synchronous clock stabilization apparatus and a method thereof for a synchronization system.

The present invention provides an apparatus and method for synchronizing a clock of a system in supplying a clock of a synchronization system including a plurality of circuit stages.

Synchronous clock stabilization apparatus of the synchronization system according to an aspect of the present invention generates a reference clock and temporarily stores the generated clock, the reference clock generated from the clock generator and the individual clock supplied to each circuit stage And a clock compensator for compensating a clock by comparing a phase difference with the clock signal and a clock controller for controlling an individual clock phase of each circuit stage.

The clock generator is composed of a clock generator which is present in the synchronized system as a single unit and supplies a reference clock in the system and a clock buffer which temporarily stores the clock generated by the clock generator. The reference clock generated by the clock generator may have a delayed clock phase or a lost clock when supplied to each circuit terminal. This problem is solved by compensating the clock phase in a clock compensator such as a DPLL circuit. The DPLL circuit compares the reference clock generated by the clock generator with the clock fed back from each circuit stage to compensate for the changed or delayed clock and maintains the clock continuously when the reference clock is lost. The clock compensator compensates for a clock supplied to each circuit according to a value set by the clock controller. The clock controller includes a skew controller and a micro controller. The skew control unit may control the skew control unit by determining a clock delay degree at each circuit unit by interlocking with the skew control unit under the control of the micro control unit. It will play a role.

In the synchronization clock stabilization method of a synchronization system according to another aspect of the present invention, in a clock supply method of a synchronization system including a plurality of circuits, a clock generation step of generating a reference clock as a reference for system synchronization, the generated reference clock A clock compensation step of compensating the clock by comparing the phase difference between the reference clock and the individual clocks supplied to each circuit stage is received as an input, and a clock control step of controlling the phase of the individual clocks supplied to each circuit stage. In the clock control step, the phases of the clocks supplied to the circuit stages may be set differently from each other so that the characteristics of the circuit stages may be different.

Hereinafter, a synchronous clock stabilization apparatus of a system according to the present invention will be described in detail with the drawings.

2 is a block diagram of a preferred embodiment of a synchronous clock stabilization apparatus of a synchronized system according to the present invention.

The synchronous clock stabilization apparatus shown in FIG. 2 is largely comprised of a clock generator consisting of a clock generator 20 and a clock buffer 21, a clock compensating portion consisting of a DPLL 22, and a skew control portion 23 and a microcontroller 24. It can be divided into a clock control unit including a).

The synchronized system in Figure 2 has several circuits synchronized in the system, but only one clock generator 20 is used. As the clock generator 20, a crystal oscillator or a phase locked loop (PLL) clock generator may be used. A crystal oscillator generates electronic pulses with regular intervals generated by accurate and regular vibrations and uses them as clock pulses or timing signals to synchronize all the operations of each component in the system. The phase locked loop (PLL) clock generator is composed of a phase locked circuit, a first divider, a plurality of output buffers, and the like, and operates by maintaining a reference clock signal and a feedback clock signal at the same frequency and phase.

The clock generated from the clock generator 20 is temporarily stored in the clock buffer 21 and input to the DPLL 22 as a reference clock. Digital Phase Locked Loop (DPLL) is a popular circuit in modern integrated circuit design. Its function is to generate a clock signal synchronized to the input signal to the circuit. The DPLL is recently used as a means for generating a built-in clock of a microprocessor, and its operating frequency has been widened and high frequency according to the application of the microprocessor. In the present invention, the DPLL 22 compares the reference clock and the phase of the clock fed back from each circuit stage to supply a clock having a phase suitable for each circuit stage. The clock fed back to the DPLL 22 is adjusted according to the phase value of the skew control unit 23 interlocked with each circuit terminal.

The skew control unit 23 shown in FIG. 2 is a circuit for synchronizing and controlling a plurality of clocks by removing skew which is a time phase difference between clocks. Although the clock generated by the same clock generator 20 in the system is divided into a plurality of clocks through the clock buffer 21 and is input to each circuit stage, some clocks have problems such as phase delay and signal loss. The phenomenon that the phases of the clocks do not match occurs. This creates a major disruption to system-wide synchronization. For example, when handling voice data, the voice is distorted, and when the control data is exchanged, a fatal failure occurs in the system.

In order to prevent this phenomenon, a circuit for removing skew, which is a phase difference between clocks, is introduced. The skew control unit 23 is individually linked to each circuit terminal to control only the corresponding circuit terminal, and the whole is controlled by the micro control unit 24. Since the difference from the reference clock is different for each clock supplied to each circuit terminal, one skew control unit 23 is provided for each circuit. In addition, since the microcontrol unit 24 controls the clock compensation in each circuit stage, the phase and delay of the clock in each circuit stage may be set differently.

The micro control unit 24 constituting the clock control unit together with the skew control unit 23 is interlocked with the skew control unit 23 to adjust the phase and delay of each circuit stage, thereby mutually interrelating the skew control unit 23. To control. Thus, when different phase clocks and delays are used in each circuit, the clock at each circuit stage can be changed only by changing control values on the micro control unit 24 without the user controlling each skew control unit 23. Can be changed.

3 is a block diagram of a DPLL circuit, which is a preferred embodiment of a clock compensator according to the present invention. That is, FIG. 3 illustrates the DPLL 22 shown in FIG. 2 in more detail.

As shown in FIG. 3, the DPLL 22 includes a phase comparison unit 220 for comparing the reference clock and the feedback clock, a loop filter 221 for filtering out noise frequencies, and voltage control for outputting a desired oscillation frequency from an applied voltage. An oscillator 223 and a divider 224 for lowering the frequency of the signal output from the voltage controlled oscillator 223 is included.

The phase comparator 220 is a demodulator for demodulating a phase modulated wave. The phase comparator 220 compares an input signal and a reference signal to generate an output voltage having a change in amplitude and polarity from a phase difference between the input signal and the reference signal. The signal output from the phase comparator 220 is filtered by the loop filter 221 and is used as an input signal of the voltage controlled oscillator (VCO) 223. The loop filter is mainly composed of a low pass filter (LPF) structure to filter out various ambient noise frequencies generated during loop operation, and to change the voltage of the VCO control terminal through a change in the amount of charge accumulated using a capacitor.

Voltage Controlled Oscillator (VCO) is a device that outputs the specific oscillation frequency desired by the user according to the input voltage applied from the outside. To become the main cause.

The signal output from the voltage controlled oscillator 223 is converted into a low frequency signal by a divider 224. In the case of phase comparison between the reference clock and the feedback clock without the divider 224, since the output frequency of the VCO is too high to compare the two signals, the output frequency of the VCO is divided by an appropriate ratio to make the frequency suitable for comparison with the reference clock. To give. The divider 224 has a structure such as a digital counter, and also plays a role of allowing the output frequency of the PLL structure to be varied by complexly changing the division ratio.

The signal whose frequency is lowered by the divider 224 is fed back to the input of the phase comparator 220, and the phase comparator 220 is again subjected to a process of comparing the phase of the reference clock and the feedback clock. This is repeated.

The synchronization clock stabilization apparatus and method of the inventors of the present invention solve the problem of synchronization clock loss and synchronization mismatch in the synchronization system by stabilizing a clock that plays an important role in the operation of the synchronization system by additionally configuring a DPLL and a skew control unit. . In addition, when a clock having a different synchronization is used in each circuit stage, it is possible to operate the system clock more easily by adjusting the phase value of the skew control unit by changing the control value on the micro control unit.

Claims (10)

In the clock supply apparatus of a synchronization system which is interoperable with a plurality of driving circuits, A clock generator which generates a reference clock for operating the plurality of driving circuits; A clock compensator for compensating a clock by comparing a phase difference between a reference clock generated from the clock generator and an individual clock supplied to each driving circuit; Synchronization clock stabilization apparatus of a synchronization system including a clock control unit for adjusting the individual clock phase supplied to each driving circuit according to a predetermined phase value. The method of claim 1, The clock generator, A clock generator for generating a reference clock; and And a clock buffer for temporarily storing the generated reference clock. The method of claim 2, The clock generator, Synchronous clock stabilization apparatus of a synchronization system, characterized in that the crystal oscillator (Phase Locked Loop) clock generator. The method of claim 1, The clock compensation unit, A phase comparison unit for comparing a phase of a reference clock generated by the clock generator with a phase of an individual clock fed back from each driving circuit; Compensating the phase of the clock according to the phase comparison result of the phase comparator, and if the reference clock is lost, Synchronous clock stabilization apparatus of a synchronization system, characterized in that it comprises a phase compensator for maintaining the clock continuously. The method of claim 1, The clock compensation unit, A synchronous clock stabilization device for a synchronization system, characterized in that it is a digital phase locked loop (DPLL) circuit. The method of claim 5, The digital phase locked loop, A phase comparison unit comparing the reference clock and a clock fed back from the driving circuit; A loop filter to remove various ambient noise frequencies occurring during a loop operation among the output signals of the phase comparator; A voltage controlled oscillator for outputting a specific oscillation frequency according to the signal voltage input through the loop filter; And And a divider for dividing an output frequency of the voltage controlled oscillator by an appropriate ratio to generate a frequency suitable for comparison with a reference clock and providing it to the phase comparator. The method of claim 1, The clock control unit, A micro control unit which determines a clock delay degree in each driving circuit to control a phase and a delay of the entire system clock; And at least one skew control unit which is individually linked to each driving circuit and which is controlled under the control of the micro control unit to adjust clock delays of the driving circuits differently from each other. In the clock supply method of a synchronization system interlocked with a plurality of driving circuits, A clock generation step of generating a reference clock as a reference for system synchronization; A clock compensation step of receiving a generated reference clock as an input and compensating a clock by comparing a phase difference between the reference clock and the individual clocks supplied to the respective driving circuits; And a clock control step of controlling a phase of an individual clock supplied to each driving circuit according to a preset phase value. The method of claim 8, The clock compensation step, A phase comparison step of comparing a phase of a reference clock generated in the clock generation step with a phase of an individual clock fed back from each driving circuit; Compensating the phase of the clock according to the phase comparison result of the phase comparison step, and if the reference clock is lost, the phase of the synchronization clock stabilization method of a synchronization system including a phase compensation step. The method of claim 8, The clock control step, A method of stabilizing a synchronous clock of a synchronization system, characterized in that the phases of the respective driving circuits can be changed by setting phases of the individual clocks supplied to the respective driving circuits differently.

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