KR200242921Y1 - System Clock Redundancy - Google Patents

Abstract

The present invention relates to a redundancy device for a system clock and / or a synchronous clock in a redundant system, comprising unit A and unit B, each of which generates one or more system clocks and a synchronous clock while performing an operation state and a standby state alternately. In one redundancy system, each unit includes a feedback loop circuit for dividing a reference frequency, a phase control unit for correcting a phase error of a basic system clock, a system clock distribution unit for dividing an output of the phase control unit to form a system clock, and a basic synchronization unit. A position control unit corrects a position error of a clock, and a synchronization clock distribution unit for dividing an output of the position control unit to generate a synchronization clock.

The present invention corrects the phase error and / or position error for the system clock and the synchronous clock of the operating unit in the standby unit, so that the system clock and the synchronous clock of each of the two units are matched. Therefore, when the standby unit is switched to the operation unit, the clock phase error and / or position error does not occur, it is possible to prevent the system failure due to such clock mismatch in advance.

Description

System Clock Redundancy

The present invention relates to a redundancy system, and more particularly, to a redundancy device for a system clock and / or a synchronous clock of each of two units in a redundancy system including an operation unit and a standby unit.

In general, a redundant system has two identical systems in the unit, and if a problem occurs in the system currently in operation, the process is automatically carried out to the other waiting. Such a redundancy system is to improve the reliability of the system, and particularly, a system requiring real-time processing, for example, has been applied to an online system or a communication exchange system of a bank. On the other hand, in the case of a system employing multiple system clocks (or synchronous clocks), multiple clocks are generated by dividing the fundamental frequency from the outside. In the case of a redundant system, each of the system clock generators is provided in the operating unit and the spare unit as well.

1 is a block diagram of a conventional system clock redundancy apparatus.

Referring to FIG. 1, Units A and B which receive a reference frequency from the outside and generate necessary system clocks and sync clocks are illustrated.

The unit A outputs the outputs of the phase comparator 11a and the phase comparator 11a for comparing the phases of the fed back signal with the output signal of the first divider 10a for dividing the reference frequency. A loop filter 12a for converting an analog signal, a voltage controlled oscillator 13a (hereinafter referred to as a VCXO) for oscillating a voltage by a crystal oscillator according to the output of the loop filter 12a, and a VCXO 13a And a second divider 14a which divides the output of the feedback signal and feeds the feedback to the phase comparator 11a. In addition, the output of the second divider 14a is synchronized with the third divider 15a for making the system clock, the system clock divider 17a, and the fourth divider 16a for making the synchronous clock. It consists of a clock divider 18a.

The first divider 10a is designed with a divider value having a maximum common divisor of the reference frequency and the frequency required by the system. The second divider 14a is designed with a divider value having a greatest common divisor for feeding back the output of the VCXO 13a.

As a result, the output frequencies of the two dividers 10a and 14a are input to the phase comparator 11a, and the phase comparator 11a divides the reference frequency and the frequency in the VCXO 13a by N (the second divider ( Compared with (a) of 14a) to keep the phase difference constant. At this time, if the phase difference becomes constant, the VCXO 13a generates a constant frequency. The phenomenon in which the external frequency and the internal oscillator frequency coincide is called phase locked.

The output of the phase comparator 11a may be represented by Equation 1 below, and the output voltage has a linear characteristic due to a phase difference.

Where K _d is the gain of the phase comparator, θ _r is the phase of the reference frequency, and θ _s is the phase of the output signal divided by N by the VCXO output.

When the phase is locked by the feedback control by the phase comparator, loop filter, VCOX and the like, the output of the VCXO 13a is provided to the third divider 15a for the system clock and divided. The output of the third divider 15a is divided at a frequency required by the system through the system clock divider 17a to generate a plurality of system clocks SYS_C. In addition, the output of the third divider 15a generates a plurality of sync clocks SYNC_C required for the system through the fourth divider 16a for the sync clock and the sync clock divider 18a. Here, the system clock distribution unit 17a and the synchronous clock distribution unit 18a are activated or deactivated by external enable control.

Since the configuration and function of the UNIB are exactly the same as that of the unit A, the description of the unit B is omitted below. In particular, UNIA and Unit B are separated from each other and perform the above functions independently.

For example, suppose that Unit A is initially activated and Unit B is inactive. At any moment, if unit A is deactivated according to any switching condition and UNIB is activated, unit A and unit B generate system clocks and sync clocks independently of each other. Can be.

Therefore, when switching from unit A to unit B, the phases of the system clocks of the unit A and the unit B and the positions of the synchronization clocks do not coincide, which causes a serious system error and a problem.

Therefore, the present invention was devised to solve the above problems, and the present invention is a phase error between the system clocks generated in the two units and / or the position error between the synchronous clocks in the unit switching in the redundant system including the operation unit and the spare unit. It is an object of the present invention to provide a system clock redundancy device for minimizing the number.

The apparatus for achieving the above object is a redundancy system having a unit A and a unit B for generating one or more system clocks and a synchronous clock, while alternately operating and standby states, wherein the unit A, A first feedback loop circuit for generating a first basic clock by dividing a reference frequency, and divides the first basic clock in the operating state, while in the standby state, the divided signal of the first basic clock and the corresponding divided signal of the unit B. A first phase control unit for correcting a phase error with the first basic system clock to generate a first basic system clock, and a first system clock distribution unit for dispensing the first basic system clock to form a system clock; And divides the position error between the divided signal of the first basic system clock and the corresponding divided signal of the unit B, and generates a basic synchronous clock. A position control unit, and a first synchronization clock distribution unit for dividing the first basic synchronization clock to create a synchronization clock; The unit B divides the reference frequency into a second feedback loop circuit for generating a second basic clock, and divides the second basic clock in the operating state, while the division signal of the second basic clock and the unit are in the standby state. A second phase control unit for correcting a phase error with the corresponding divided signal of A to generate a second basic system clock, and a second system clock distribution unit for dividing the second basic system clock to form a system clock; The second position control unit divides the second basic system clock and, in the standby state, corrects a position error between the divided signal of the second basic system clock and the corresponding divided signal of the unit A, thereby generating a second basic synchronous clock. And a second synchronous clock distributor which divides the basic synchronous clock to generate a synchronous clock.

The present invention corrects the clock of the standby unit using the basic clock and the intermediate clock of the currently operating unit among the unit A and the unit B, so as to match the clock of the operating unit side.

1 is a block diagram of a conventional system clock redundancy apparatus,

2 is a block diagram of a system clock redundancy apparatus according to the present invention,

3 is a signal timing diagram for the phase error of the system clock of FIG.

4 is a graph showing data values of measuring phase error of the system clock of FIG.

5 is a signal timing diagram for the position error of the synchronization clock of FIG.

<Description of the symbols for the main parts of the drawings>

210,310: feedback loop circuit 220,320: phase control unit

230,330: System clock distribution unit 240,340: Position control unit

250,350: Synchronous clock distribution unit

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention.

2 is a block diagram of a system clock redundancy apparatus according to the present invention, which is provided with a reference frequency from the outside to generate one or more system clocks SYS_C and one or more synchronization clocks SYNC_C, respectively. It consists of unit A and unit B. Unit A and unit B are composed of the same elements as shown in Fig. 2, and have the same function. Units A and B alternate between operating and standby states by ENABLE control.

The unit A includes a first feedback loop circuit 210, a first phase controller 220, a first system clock divider 230, a first position controller 240, and a first synchronous clock divider 250. .

In the first feedback loop circuit 210, the first divider 211 is designed as a divided value (N) having a maximum common divisor of a reference frequency and a frequency required by the system, and an external input reference frequency Dispense. The phase comparator 212 compares the output signal of the first divider 211 with the phase of the fed back signal. The loop filter 213 converts the digital output of the phase comparator 212 into an analog signal and provides it to the VCXO 214. The VCXO 214 outputs an oscillation signal according to the output voltage of the loop filter 213, and the second divider 215 divides the output of the VCXO 214 and feeds it back to the phase comparator 212. The second divider 215 is designed with a divider value M having a greatest common divisor for feeding back the output value of the VCXO 214. The loop filter 213 may include a charge pump.

As a result, the first feedback loop circuit 210 performs feedback control so that the phase difference between the divided signal obtained by dividing the reference frequency provided from the outside through the phase comparator 212 and the output signal of the VCXO 214 is constant. Ensure that the phase of the signal is locked.

Here, the VCXO 214 outputs a first basic clock B_CLK1.

In the first phase controller 220, the first variable frequency divider 221 receives the first basic clock B_CLK1 and divides it into a predetermined value. The phase detector 222 receives the output of the first variable divider 221 and the corresponding clock signal (that is, the output of the phase detector 322 of the unit B) to detect the phase error between the two signals. The first division controller 223 adjusts the division value of the first variable divider 221 according to the detection signal of the phase detector 222.

As a result, the first phase controller 220 detects a phase error between the divided signal obtained by dividing the first basic clock B_CLK1 of the VCXO 214 and the corresponding clock signal provided by the unit B, and accordingly the first variable divider. A division value of 221 is readjusted to correct a phase error. Here, the first variable divider 221 outputs the first basic system clock BS1.

The first system divider 230 receives the first basic system clock BS1 from the first variable divider 221 and divides the first system divider 230 to generate a plurality of system clocks SYS_C1 to C4.

In the first position controller 240, the second variable frequency divider 241 receives the first basic system clock BS1 and divides it into a predetermined value. The position error detector 242 receives the output of the second variable frequency divider 241 and the corresponding division signal (that is, the output of the position error detector 342 of the unit B) to detect the position error of the two signals. do. The second division controller 243 adjusts the division value of the second variable frequency divider 241 according to the detection signal of the position error detector 242.

As a result, the first position controller 240 detects a position error between the divided signal obtained by dividing the first basic system clock BS1 of the first variable divider 221 and the corresponding divided signal in the unit B, and the position. In response to the error, the division value of the second variable frequency divider 241 is readjusted to correct a position error. Here, the second variable divider 241 outputs the first basic synchronous clock BC1.

The first sync clock distributor 250 receives the first basic sync clock BC1 to generate a plurality of sync clocks SYNC_C1 to C2 required by the system.

The unit B includes a second feedback loop circuit 310, a second phase controller 320, a second system clock divider 330, a second position controller 340, and a second synchronous clock divider 350. . Each component of the unit B is the same as the corresponding element of the unit A and its detailed configuration is omitted below.

However, the difference is that in the second phase controller 320 of the unit B, the phase detector 322 is provided with the output of the third variable frequency divider 321 and the output of the phase detector 222 of the unit A to phase the two signals. Detect errors In addition, in the second position controller 340, the position error detector 342 receives the output of the fourth variable frequency divider 341 and the output of the position error detector 242 of the unit A to detect the position error of the two signals. do.

As described above, the unit A and the unit B mutually correct the phase error of the basic system clocks BS1 and BS2 independently generated, and mutually correct the position error of the basic synchronization clocks BC1 and BC2. As a result, the main system clock and the basic synchronous clock of the current operating unit are used as the main clocks to control the clock generation of the standby unit to match the clock of the operating unit side. That is, the clock of the standby unit is generated dependently by the operation unit.

Hereinafter, the operation and effect of the present embodiment will be described with reference to FIGS. 2 to 5. This embodiment starts by setting unit A as the operation unit and unit B as the standby unit.

Referring to FIG. 2, in the first feedback control circuit 210, the phase comparator 212 divides a reference signal with a frequency signal obtained by dividing a reference frequency into a divided value N by the first divider 211, and the oscillation of the VCXO 214. A frequency signal obtained by dividing the frequency into the divided value M by the second divider 215 is received. The phase comparator 212 compares two input signals and detects a phase error in a digital form. The loop filter 213 controls the VCXO 214 by filtering the phase error in the digital form and converting the average error in the analog form. The VCXO 214 outputs an oscillation frequency having a number corresponding to the phase error provided from the loop filter 213 and feedbacks it to the second divider 215. In this way, feedback control is performed to keep the phase error between the external reference frequency and the internal oscillation frequency constant at all times. When the phase error is constant, the oscillation frequency of the VCXO 214 is constantly output. This phenomenon is called phase lock. Phase lock is important for keeping the system in synch with the outside world. When phase locked, the VCXO 214 outputs the first basic clock B_CLK1.

The first basic clock B_CLK1 is divided by the first variable divider 221 of the first phase controller 220 to be converted into a first basic system clock BS1, and the first basic system clock BS1. Is provided to the first system clock distribution unit 230.

Here, the first phase detector 222 in the unit A (operation state) detects the phase of the first basic system clock BS1 and provides it to the second phase detector 322 in the unit B (standby state). Then, in unit B, the second phase detector 322 detects the phase error by comparing the phase of the second basic system clock BS2 divided in its third variable divider 321 with the phase provided in unit A. Do it. This phase error is input to the third frequency division controller 321 to adjust the frequency division value of the third variable frequency divider 321. For example, the phase of the system clock can be changed by changing the division value of the third variable frequency divider 321 to 'N-n'.

Therefore, the phase of the system clock of the unit B in the standby state can be matched to the phase of the system clock provided in the unit A in the operating state.

3 is a signal timing diagram for the phase error of the system clock of FIG. 2, (a) is a system clock of the unit A in operation (ACTIVE_SYS_CLK), and (b) is a system clock of the unit B in standby (STANBY_SYS_CLK). (C) is the phase error signal PHASE_ERP of (a) and (b) detected by the second phase detector 322 of unit B. In (c) of FIG. 3, a 90 ° phase error occurs between the system clocks of two units. That is, the phase error may be measured according to the 'high' level interval of the output signal of the second phase detector 322.

4 is a graph illustrating data values of measuring phase errors of the system clock of FIG. 2. In FIG. 4, it can be seen that the error data value increases from 0 to π, has a maximum value from π, and then decreases to 2π.

As a result, in the third division controller 323 of the unit B, the phase of the system clock is changed while changing the division value of the variable frequency divider 321 until the phase error value of the second phase detector 322 becomes zero. Change and correct. In this way, the waiting unit B can generate a system clock having the same phase as the operating unit A.

On the other hand, the position error correction process of the sync clock works similarly to the system clock correction process, which will be described below.

In the unit A in the operating state, the first basic system clock BS1 is divided through the second variable divider 241 of the first position controller 240 to be converted into a second basic synchronous clock BC1, and 1 is provided to the synchronous clock distribution unit 250. The first sync clock distributor 250 generates a plurality of sync clocks required for the system and distributes the same to the corresponding block.

Here, the first basic synchronous clock BC1 signal in the unit A (operation state) becomes the main signal, and the second position error detector 342 of the unit B (standby state) is passed through the first position error detector 242. Is provided. Then, the second position error detector 342 in the unit B in the standby state is divided into the second basic synchronous clock BC2 divided by the fourth variable divider 341 of the unit B and the first position error detector of the unit A. The first basic synchronization clock BC1 provided from 242 is compared to detect the position error of the two signals. The position error data is input to the fourth frequency divider 343 to adjust the frequency division value of the fourth variable frequency divider 341. For example, the phase of the synchronous clock can be changed by changing the division value of the fourth variable divider 341 to 'N-n'. That is, the position of the sync clock of the unit B in the standby state can be matched to the position of the sync clock provided from the unit A in the operating state.

FIG. 5 is a signal timing diagram for the position error of the synchronization clock of FIG. 2, (a) is a synchronization clock (ACTIVE_SYNC_CLK) of unit A in an operational state, and (b) is a synchronization clock (STANDBY_SYNC_CLK) of a unit B in a standby state. to be. In FIG. 5B, a position error POSITION_ERR has occurred between the synchronization clocks of two units.

Here, the position error detector 342 of the unit B may be implemented using a counter.

For example, when the main synchronization clock ACTIVE_SYNC_CLK of unit A is 'high' as shown in FIG. 5A, the count starts. When the standby synchronization clock STANDBY_SYNC_CLK of unit B is input as shown in FIG. Stop and generate error data using the count up to this point.

As a result, the fourth division controller 342 changes the division value of the fourth variable frequency divider 341 until the position error data value of the second position error detector 342 becomes '0', thereby synchronizing clocks. Correct by changing the position of.

Accordingly, the waiting unit B can generate a synchronization clock having the same position as the operating unit A.

Although the embodiment of the present invention has been described by setting unit A as an operation unit and unit B as a standby unit, even if unit A is set as a standby unit and unit B as an operation unit, the same operation as described above.

In summary, the present invention corrects the phase error using the system clock of the operating unit in the standby unit, and corrects the position error using the synchronous clock of the operating unit, thereby adjusting the phase and position of the system clock and the synchronization clock of the two units. Always match.

The present invention is not limited to the embodiments described above, and various changes and modifications can be made by those skilled in the art, which are included in the spirit and scope of the present invention as defined in the appended claims.

As described above, in the related art, since the operation unit and the standby unit independently generate the system clock and the synchronous clock, the phase and / or the position of the system clock and the synchronous clock do not coincide. It may cause a disorder.

The present invention corrects the phase error and / or position error based on the system clock and the synchronous clock of the operating unit in the standby unit, so that the system clock and the synchronous clock of each of the two units coincide. Therefore, when the standby unit is switched to the operation unit, the clock phase error and / or position error does not occur, it is possible to prevent the system failure due to such clock mismatch in advance.

Claims (8)

In a redundancy system having unit A and unit B, which generate one or more system clocks and a synchronous clock, while alternately operating and standby, the unit A divides a reference frequency to generate a first basic clock. A first feedback loop circuit; In operation, the first basic clock is divided, while in the standby state, a phase error between the division signal of the first basic clock and the corresponding division signal of the unit B is corrected to generate a first basic system clock. A phase control unit; A first system clock distribution unit that divides the first basic system clock to form a system clock; The first basic system clock is divided in the operating state, while the standby state corrects the position error between the divided signal of the first basic system clock and the corresponding divided signal of the unit B, thereby generating the basic synchronous clock. Position control unit; And a first synchronous clock distribution unit for dividing the first basic synchronous clock to generate a synchronous clock; The unit B includes: a second feedback loop circuit for dividing a reference frequency to generate a second basic clock; In operation, the second basic clock is divided, while in the standby state, a phase error between the divided signal of the second basic clock and the corresponding division signal of the unit A is corrected to generate a second basic system clock. A phase control unit; A second system clock distribution unit for dispensing the second basic system clock to form a system clock; In the operating state, the second basic system clock is divided, while in the standby state, a position error between the division signal of the second basic system clock and the corresponding division signal of the unit A is corrected to generate a second basic synchronous clock. A second position controller; And a second synchronous clock distribution unit for dividing the basic synchronous clock to form a synchronous clock, wherein the first system clock distribution unit and the first synchronous clock distribution unit or the second system clock distribution unit and the second synchronous clock distribution unit. And the distribution unit is alternatively activated by enable control. 3. The circuit of claim 2, wherein the first feedback loop circuit comprises: a first divider for dividing the reference frequency; A first phase comparator comparing the output of the first divider with a feedback signal; A first loop filter for converting a phase error of the first phase comparator into an analog signal; A first oscillator which oscillates according to the output voltage of the first loop filter and outputs the first basic clock B_CLK1 when the phase is locked; And a second divider for dividing the oscillation signal and providing the oscillation signal to the first phase comparator. 4. The display device of claim 3, wherein the first phase control unit comprises: a first variable divider which divides the first basic clock B_CLK1 and outputs a first basic system clock BS1 when a phase error is removed; A phase detector for detecting a phase error between the output of the first variable period and the corresponding divided signal of the unit B; And a first division controller which adjusts the division value of the first variable division period according to the phase error. The apparatus of claim 4, wherein the first position controller comprises: a second variable divider which divides the first basic system clock BS1 to a predetermined value; A first position error detector for detecting a position error of the output of the second variable frequency divider and the corresponding divided signal of the unit B; And a second division controller which adjusts the division value of the second variable divider according to the position error. 3. The second feedback loop circuit of claim 2, further comprising: a third divider for dividing the reference frequency; A second phase comparator comparing the output of the third divider and the phase of the fed back signal; A second loop filter for converting a phase error of the second phase comparator into an analog signal; A second oscillator which oscillates according to the output voltage of the second loop filter and outputs a second basic clock B_CLK2 when the phase is locked; And a fourth divider for dividing the oscillation signal and providing the oscillation signal to the second phase comparator. The method of claim 6, wherein the second phase control unit comprises: a third variable frequency divider which divides the second basic clock B_CLK2 and outputs a second basic system clock BS2 when the phase error is removed; A phase detector for detecting a phase error between the output of the second variable frequency divider and the corresponding divided signal of the unit A; And a third division controller which adjusts the division value of the third variable division period according to the phase error. The apparatus of claim 7, wherein the second position controller comprises: a fourth variable divider which divides the second basic system clock BS2 to a predetermined value; A second position error detector for detecting a position error between an output signal of a fourth variable frequency divider and a corresponding division signal of the unit A; And a fourth frequency divider controller for adjusting the frequency division value of the fourth variable frequency divider according to the position error. 9. The system according to claim 5 or 8, wherein the position error detector is a counter that generates position error data when a count is started by an input signal of an operating unit and terminated by an input signal of a standby unit. Clock redundancy unit.