JP2000031819A - Clock synchronizing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock synchronizing circuit with which the quality of a synchronizing signal can be prevented from being degraded in the case of reference clock signal fluctuation or input interruption and stable operation is enabled. SOLUTION: A clock synchronizing circuit 100 is provided with a frequency divider 10, phase detector 20 and PLL circuit 30. The frequency divider 10 generates a frequency divided clock signal by dividing the frequency of a local clock signal. When the phase difference of a reference clock signal and the frequency divided clock signal is settled within a prescribed range, the phase detector 20 sets this frequency dividing ratio at a fixed value but in the other case, the frequency dividing ratio is variably controlled and the frequency divided clock signal is synchronized with the reference clock signal. Even when the reference clock signal contains jitter or the like, the frequency divided clock signal not to be affected by this jitter or the like is inputted to the PLL circuit 30. When the input of the reference clock signal is interrupted, the frequency divided clock signal outputted while being set to the prescribed frequency dividing ratio by the frequency divider 10 is inputted to the PLL circuit 30.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a clock synchronization circuit for generating a signal synchronized with a reference clock signal.

[0002]

2. Description of the Related Art Conventionally, there has been known a clock synchronization circuit which outputs a signal synchronized with a predetermined reference clock signal when the signal is input. FIG. 5 is a diagram showing a configuration of a conventional clock synchronization circuit, and is a widely used PL.
The L circuit is shown. The clock synchronizing circuit shown in FIG. 1 operates such that a signal obtained by dividing a signal output from a VCO (Voltage Controlled Oscillator) at a predetermined frequency division ratio and a reference clock signal input thereto have the same phase. Since the oscillation state is controlled, a signal synchronized with the reference clock signal is obtained from the VCO.

[0003]

The above-described conventional clock synchronization circuit can obtain a signal synchronized with a reference clock signal input from the outside. However, there is a problem that the edge position of the synchronization signal obtained in synchronization with the reference clock signal is not stable, and the quality of the output synchronization signal is deteriorated. Also, when the input of the reference clock signal is suddenly interrupted, the oscillation frequency may fluctuate greatly, for example, the value of the control voltage applied to the VCO becomes large (for example, the same value as the upper limit power supply voltage), There is a problem that operation becomes unstable.

In particular, when a reference clock signal is extracted from a signal received via a communication line, there are many jitters and wanders contained in the reference clock signal, and depending on the state of the line, there are also problems such as signal interruption. As a result, the input of the reference clock signal may be temporarily interrupted.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to prevent the quality of a synchronization signal from deteriorating due to a change in a reference clock signal and to interrupt the input of the reference clock signal. It is an object of the present invention to provide a clock synchronous circuit capable of stabilizing the operation even in the case where the clock synchronization circuit is used.

[0006]

In order to solve the above-mentioned problems, a clock synchronization circuit according to the present invention is configured to divide a frequency of an auxiliary clock signal input separately from a reference clock signal by a frequency divider, thereby dividing the frequency of the divided clock. A signal is generated, and when the phase difference between the reference clock signal and the frequency-divided clock signal is within a predetermined range, the frequency division ratio is controlled so that the frequency division ratio of the frequency divider becomes a predetermined fixed value. The setting operation by means is performed,
A phase locked loop circuit (PLL circuit) operates based on the frequency-divided clock signal output from the frequency divider. Therefore, even when the reference clock signal includes jitter or wander and the edge position fluctuates, if the fluctuation range is within a predetermined range, a divided clock signal that is not affected by these fluctuations is used. Since the PLL circuit operates using the same, the quality of the synchronization signal output from the PLL circuit does not deteriorate.

When the phase difference between the reference clock signal and the frequency-divided clock signal is not within the above-described predetermined range, the frequency division ratio control means may divide the phase difference until the phase difference falls within the predetermined range. It is preferable to set the frequency division ratio of the frequency divider variably. By performing such a setting operation, the phase of the frequency-divided clock signal is quickly changed to the phase of the reference clock signal even when synchronization is not established at the time of synchronization pull-in immediately after the input of the reference clock signal is started. Can be matched.

Preferably, the frequency division ratio control means sets the frequency division ratio of the frequency divider to a predetermined fixed value when the input of the reference clock signal is interrupted. As described above, since the divided clock signal is input to the PLL circuit even when the reference clock signal is not temporarily input, the operation of the PLL circuit, that is, the operation of the entire clock synchronization circuit can be stabilized.

It is preferable to use a signal extracted from a signal received via a communication line as the above-mentioned reference clock signal. In general, a signal received via a communication line contains a lot of jitter and wander, and a signal disconnection state is likely to occur depending on the state of the line. Therefore, the reference clock signal extracted from such a signal also contains a lot of jitter and wander and a signal disconnection state is likely to occur. However, according to the clock synchronization circuit of the present invention, such a reference clock signal is Even when it is used, it is possible to ensure stable operation with little deterioration of quality.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A clock synchronization circuit according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a configuration of the clock synchronization circuit of the present embodiment. As shown in FIG. 1, the clock synchronization circuit 100 according to the present embodiment includes a frequency divider 10, a phase detector 2
0, a PLL circuit 30 is included. The clock synchronization circuit 100 includes a reference clock signal extracted from a signal received via a communication line and a local oscillator 9.
A local clock signal as an auxiliary clock signal output from 0 is input, and a predetermined synchronous clock signal synchronized with the reference clock signal is output. In addition,
The “communication line” includes both a line using a wired transmission line and a wireless line.

The frequency divider 10 receives the local clock signal output from the local oscillator 90, and divides the local clock signal by a predetermined frequency division ratio (hereinafter, a signal output from the frequency divider 10). (Referred to as a "divided clock signal"). The frequency division ratio of the frequency divider 10 can be changed under the control of the phase detector 20, and the frequency-divided clock signal output from the frequency divider 10 is input to each of the phase detector 20 and the PLL circuit 30. You. The local oscillator 90 performs an oscillating operation with a small frequency fluctuation using a quartz oscillator, for example, and a local clock signal obtained as an oscillating output is input to the frequency divider 10.

Phase detector 20 as frequency division ratio control means
Has a reference clock signal input to one input terminal and a frequency-divided clock signal input to the other input terminal, and detects the relative phase state of these two types of clock signals. Specifically, the phase detector 20 determines (1) when the edge position of the frequency-divided clock signal falls within a predetermined range with reference to the edge position (for example, signal rising timing) of the input reference clock signal. (2) When the edge position of the divided clock signal is within the range of the phase delay,
(3) Three states are detected when the edge position of the divided clock signal is in the range of the phase advance. In addition, the phase detector 20 detects a state in which the reference clock signal is not input, apart from these three states. The phase detector 20 outputs a frequency division ratio control signal according to these detection results.
The frequency division ratio of the frequency divider 10 is variably controlled based on the frequency division ratio control signal.

The PLL circuit 30 includes a phase comparator 32, LP
It comprises an F (low-pass filter) 34, a VCO (voltage-controlled oscillator) 36, and a frequency divider 38. The phase comparator 32 receives a signal obtained by dividing the output signal of the VCO 36 by the frequency divider 38 and the frequency-divided clock signal output from the frequency divider described above, and calculates the phase difference between these two input signals. A pulse signal having a corresponding duty ratio is output, and a control voltage obtained by smoothing the pulse signal by the LPF 34 is applied to the VCO 36. When there is a phase difference between two signals input to the phase comparator 32, LP
The control voltage output from F34 changes in a direction to reduce the phase difference, and the VCO 36 outputs a synchronous clock signal synchronized with the frequency-divided clock signal input to the PLL circuit 30.

The clock synchronization signal according to the present embodiment has such a configuration, and its operation will be described below. First, when a reference clock signal is input,
The operation when the phase detector 20 performs a predetermined division ratio setting operation according to the phase difference between the reference clock signal and the divided clock signal will be described.

FIG. 2 is a diagram showing timings when the edge position of the divided clock signal is included in the predetermined range a with respect to the edge position of the reference clock signal. When the input of the reference clock signal to the clock synchronization circuit 100 of the present embodiment is started and the phases of the reference clock signal and the divided clock signal are almost coincident (detailed operation until coincidence will be described later), the reference clock signal The edge position of the frequency-divided clock signal is included in the predetermined range a with respect to the edge position. Actually, since the reference clock signal contains jitter and wander, the edge position of the reference clock signal always fluctuates from the ideal position. This is the case during normal operation because the frequency of the reference clock signal on the side is not different. The predetermined range a is set to, for example, a phase angle of 180 °.

In such a state, the PLL circuit 30
Operates using the frequency-divided clock signal output from the frequency divider 10 as a reference signal. Since the divided clock signal itself is a highly stable signal obtained by dividing the local clock signal output from the local oscillator 90 by a predetermined dividing ratio (1 / n), the PLL circuit 30 outputs the reference clock signal. , And can operate without being affected by jitter or wander included in the reference clock signal, and outputs a high-quality synchronous clock signal without phase fluctuation.

FIG. 3 is a diagram showing the timing when the edge position of the divided clock signal is within the range b of the phase delay. Even when a frequency-divided clock signal having the same frequency or an integral multiple of the frequency of the reference clock signal is generated, the relative phases of these two signals are significantly shifted during synchronization pull-in immediately after the input of the reference clock signal. May be. For example, when the edge position of the divided clock signal is included in the predetermined range b shown in FIG.
Sets i to a predetermined negative value at the frequency division ratio 1 / (n + i) of the frequency divider 10. Thus, 1 / (n + i)
Is set to be larger than the value of 1 / n, the period of the frequency-divided clock signal is shortened, and the edge position is gradually shifted in the advancing direction so as to be included in the predetermined range a. Thereafter, the phase detector 20 restores the value of i, and the frequency divider 10 outputs a frequency-divided clock signal synchronized with the reference clock signal.

FIG. 4 is a diagram showing the timing when the edge position of the divided clock signal is in the phase advance range c. When the edge position of the frequency-divided clock signal falls within the predetermined range c shown in FIG.
At a division ratio of 1 / (n + i), i is set to a predetermined positive value. Thus, the value of 1 / (n + i) is 1 / n
, The period of the frequency-divided clock signal becomes longer, and the edge position thereof gradually shifts in the delay direction so as to be included in the predetermined range a. Thereafter, the phase detector 20 restores the value of i, and the frequency divider 10 outputs a frequency-divided clock signal synchronized with the reference clock signal.

In the various operations of the phase detector 20, the frequency division ratio of the frequency divider 10 is controlled so as to synchronize with the input reference clock signal. The operation when interrupted is as follows. The phase detector 20 detects that there is no edge of the reference clock signal, that is, detects that there is no edge in the signal input to one input terminal, and uses the edge position of the reference clock signal as a reference. The frequency division ratio of the frequency divider 10 is simply set to a fixed value 1 / n without detecting the phase state of the frequency-divided clock signal. The PLL circuit 30 operates using the frequency-divided clock signal of the fixed frequency output from the frequency divider 10 as a reference signal, and outputs a predetermined synchronization signal.

As described above, the clock synchronization circuit according to the present embodiment divides a highly stable local clock signal to generate a divided clock signal, and synchronizes the divided clock signal with an input reference clock signal. Input to the PLL circuit 30. Therefore, the PLL circuit 30 can be synchronized with the reference clock signal, and a predetermined synchronized clock signal can be obtained. In particular, even if the reference clock signal contains jitter or wander, if the deviation of the edge position due to these is within a predetermined range, the PLL circuit 30 uses the frequency-divided clock signal unaffected by these.
Is performed, it is possible to prevent the quality of the synchronous clock signal from deteriorating.

Even if the input of the reference clock signal is interrupted, the output state of the divided clock signal is maintained, so that the operation of the PLL circuit 30 does not become unstable and The operation of generating the synchronous clock signal is maintained, so that the quality of the synchronous clock signal can be prevented from deteriorating.

The present invention is not limited to the above embodiment, and various modifications can be made within the scope of the present invention. For example, in the above-described embodiment, when the edge position of the divided clock signal is not included in a predetermined range with reference to the edge position of the reference clock signal (when the edge position is not included in the fixed range a shown in FIG. 2). , I of the frequency division ratio 1 / (n + i) of the frequency divider 10 is set to a negative value or a positive value. At this time, a plurality of types (for example, three types) of values are prepared and the reference clock is set. The magnitude of the frequency division ratio may be changed according to the phase difference between the signal and the frequency-divided clock signal.

In the above-described embodiment, the local oscillator 90 is connected outside the clock synchronization circuit 100. However, the local oscillator 90 may be included in the clock synchronization circuit 100.

[0025]

As described above, according to the present invention, the frequency of the auxiliary clock signal input separately from the reference clock signal is divided by the frequency divider to generate the frequency-divided clock signal.
When the phase difference between the reference clock signal and the frequency-divided clock signal is within a predetermined range, a setting operation is performed by the frequency division ratio control unit such that the frequency division ratio of the frequency divider becomes a predetermined fixed value, The phase locked loop circuit operates based on the frequency-divided clock signal output from the frequency divider. Therefore, even if the reference clock signal includes jitter or wander and the edge position fluctuates, if the fluctuation range is within a predetermined range, the phase synchronization is performed using a frequency-divided clock signal which is not affected by the fluctuation range. The loop circuit operates, and the quality of the synchronization signal is prevented from deteriorating.

When the input of the reference clock signal is interrupted, the frequency division ratio of the frequency divider is set to a predetermined fixed value by the frequency division ratio control means to maintain the operation of generating the frequency divided clock signal. This makes it possible to stabilize the operation of the phase locked loop circuit that operates using the divided clock signal, that is, the operation of the entire clock synchronous circuit.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a clock synchronization circuit according to an embodiment.

FIG. 2 is a diagram showing timing when an edge position of a divided clock signal is included in a predetermined range with respect to an edge position of a reference clock signal.

FIG. 3 is a diagram showing timing when an edge position of a divided clock signal is in a range of a phase delay;

FIG. 4 is a diagram illustrating timing when the edge position of the divided clock signal is in a range of phase advance.

FIG. 5 is a diagram showing a configuration of a conventional clock synchronization circuit.

[Explanation of symbols]

 10, 38 frequency divider 20 phase detector 30 PLL circuit 32 phase comparator 34 LPF (low-pass filter) 36 VCO (voltage controlled oscillator) 90 local oscillator

Claims (4)

[Claims] 1. An input auxiliary clock signal,
A frequency divider that performs a frequency division operation at a predetermined frequency division ratio that can be changed, a phase locked loop circuit that operates based on a frequency divided clock signal output from the frequency divider, and a predetermined reference clock signal are input. Division ratio control means for setting a division ratio of the frequency divider to a predetermined fixed value when a phase difference between the reference clock signal and the frequency-divided clock signal is within a predetermined range; A clock synchronization circuit, comprising: 2. The frequency division ratio control unit according to claim 1, wherein the phase difference is controlled to be within the predetermined range when a phase difference between the reference clock signal and the divided clock signal is not within the predetermined range. A clock synchronization circuit, wherein the frequency division ratio of the frequency divider is variably set until included in the clock synchronization circuit. 3. The frequency division ratio control unit according to claim 1, wherein the frequency division ratio control unit sets the frequency division ratio of the frequency divider to a predetermined fixed value when the input of the reference clock signal is interrupted. Characteristic clock synchronization circuit. 4. The clock synchronization circuit according to claim 1, wherein the reference clock signal is extracted from a signal received via a communication line.