JP2710969B2 - Phase locked loop device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop device used for a frequency synthesizer circuit or the like of a mobile radio device.

[Conventional technology]

FIG. 4 is a block diagram showing a conventional phase-locked loop device, in which 1 is a reference oscillator, 2 is a first divider, which divides the output frequency of the reference oscillator 1 and outputs an output signal. As a reference signal. 3 is a phase comparator,
The phase of the reference signal is compared with the phase of the comparison signal, and the voltage control signal is output. Reference numeral 4 denotes a loop filter which smoothes the voltage control signal and supplies the smoothed control voltage to the voltage controlled oscillator 5. Reference numeral 6 denotes a second frequency divider, which divides the output frequency of the voltage controlled oscillator 5 and outputs a comparison signal as an output signal. Reference numeral 7 denotes a control circuit which outputs reset signals 9, 10, 11 to the first and second frequency dividers 2, 6 and the phase comparator 3 based on the intermittent signal 8. Reference numeral 12 denotes a falling detection signal as the comparison signal. The control circuit 7 detects the falling of the comparison signal and controls the output timing of the reset signal 9.

 Next, the operation will be described.

When the intermittent signal 8 changes from on to off, the control circuit 7
First, the phase comparator 3 is reset. The output of the phase comparator 3 is opened, and the control voltage of the voltage controlled oscillator 5 is held. Next, the first and second frequency dividers 2 and 6 are reset, and the power of each circuit is turned off within a range that does not hinder the intermittent operation. FIG. 5 shows a reference signal S1 output from the first frequency divider 2.
5 shows the output waveform of the comparison signal S2 output from the second frequency divider 6. At the time of reset, the first and second frequency dividers 2 and 6 are low-level outputs “L”. Also, the phase comparator 3 used here is assumed to detect the phase difference between the falling edges of the two signals S1 and S2.

Next, when the intermittent signal 8 is turned on from off, the control circuit 7 turns on the power supply of each circuit again, releases the reset of the second frequency divider 6, and detects the falling of the comparison signal S2. Simultaneously with this detection, the reset of the first frequency divider 2 is released.
The delay time until the first frequency divider 2 starts frequency division of the output signal of the reference oscillator 1 becomes a phase error. Finally, the reset of the phase comparator 3 is released, and a loop is formed again. In FIG. 5, during the formation of the loop, that is, during the occurrence of the above-mentioned deviation, the falling signal input to the phase comparator 3 has the above-described phase error, so that the control voltage of the voltage controlled oscillator 5 Fluctuates, and the output frequency fluctuates.

[Problems to be solved by the invention]

Since the conventional phase locked loop device is configured as described above, when the loop is repeatedly opened and closed, the phase error at the time of loop formation is up to one cycle of the output signal of the reference oscillator 1. There are problems that the output frequency of the voltage-controlled oscillator 5 fluctuates greatly, and that it takes time until the phases are synchronized. As such a conventional phase-locked loop device, there is a description of a technique similar to IEICE CS85-21.

The present invention has been made in order to solve the above-described problems. The phase error at the time of loop formation is regulated within one cycle of the output signal of the voltage controlled oscillator 5, or the phase error is adjusted by adjusting the phase. It is an object of the present invention to obtain a phase locked loop device capable of suppressing frequency fluctuations of the above and obtaining high-speed synchronization characteristics.

[Means for solving the problem]

In the phase locked loop device according to the first aspect of the present invention, the control circuit detects the reference phase of the output signal of the first frequency divider, and the second frequency divider divides the output signal of the voltage controlled oscillator. A phase shifter that performs delay control in accordance with a delay time until the phase shift is performed.

According to a second aspect of the present invention, in the phase locked loop device, the second frequency divider performs voltage control after detecting the constant value and the delay time and the reference phase of the output signal of the first frequency divider by the control circuit. It is provided with setting means and a phase shifter for adjusting the delay time until the output signal of the oscillator is divided.

(Operation)

The phase locked loop device according to the first aspect of the present invention
The delay control by the phase shifter acts so that the phase error between the reference signal from the first frequency divider input to the phase comparator and the comparison signal from the second frequency divider is within one cycle. .

According to a second aspect of the present invention, there is provided a phase locked loop device comprising:
By adjusting the constant value and the delay time by the setting means and the phase shifter, the phases of the reference signal from the first frequency divider input to the phase comparator and the comparison signal from the second frequency divider are matched. Act on.

(Example of the invention)

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, reference numeral 6A denotes a second frequency divider which has a constant internal state at the time of reset. Reference numeral 14 denotes a phase shifter for shifting the phase of a reference signal S1, which is an output signal of the first frequency divider 2.
In addition, the same portions as those shown in FIG. 4 are denoted by the same reference numerals, and redundant description will be omitted.

Next, the operation will be described. Now, it is assumed that the phase shift comparator 3 detects the falling phase difference between the reference signal S1 and the comparison signal S2, and outputs a voltage control signal according to the phase difference, as in the related art. The operation of the intermittent signal 8 being turned off from on is also the same as the conventional operation.

First, the operation when the intermittent signal 8 changes from off to on will be described. When the intermittent signal 8 is turned on, the control circuit 7 turns on the power of each circuit again, and releases the reset of the first frequency divider 2. The first frequency divider 2 starts frequency division of the output frequency of the reference oscillator 1, and the control circuit 7 detects the falling of the reference signal S1 output from the first frequency divider 2. Simultaneously with this detection, the reset of the second frequency divider 6A is released. At this time, the second frequency divider 6A starts from the falling of the reference signal S1.
The delay time until the frequency division of the output signal is started becomes a phase error. Here, the second frequency divider 6A immediately after reset release,
Since the frequency dividing operation always starts from a constant value, this phase error includes an input signal to the second frequency divider 6A, that is, an error of one cycle of the output frequency of the voltage controlled oscillator 5, and is substantially constant. It is.

The phase shifter 14 outputs a reference signal S1 output from the first frequency divider 2.
Is delayed by a fixed amount corresponding to the phase error and input to the phase comparator 3.

Finally, the reset of the phase comparator 3 is released, and a loop is formed again.

In FIG. 2, when the loop is formed, the signals S1 and S2 of the first frequency divider 2 and the second frequency divider 6A have the above-mentioned phase error. Since the signal S1 compensates for the phase error by the phase shifter 14, the phase comparator 3
Can be suppressed within one cycle of the output frequency of the voltage-controlled oscillator 5.

For example, if the output frequency of the reference oscillator 1 is 10 MHz and the output frequency of the voltage controlled oscillator 5 is 1 GHz, the phase difference between the two signals S1 and S2 input to the phase comparator 3 when the loop is formed is
What was conventionally 100 nsec can be improved within 1 nsec.

In the above embodiment, the case where only the reference signal S1 is phase-shifted by the phase shifter is shown. However, as shown in FIG.
S2 may also be passed through the phase shifter 15. For example, when the polarity of the phase comparator 3 is reversed and the fall and rise of the reference signal S1 of the first frequency divider 2 are inverted using a logic circuit, the delay increases, and the phase of the reference signal S1 becomes large. This lags behind the phase of the comparison signal S2. In such a case, by providing the phase shifter 15 also on the side of the comparison signal S2, the phase difference can be compensated, and the same effect as in the above embodiment can be obtained.

〔The invention's effect〕

As described above, according to the first aspect of the invention, the control circuit detects the reference phase of the output signal of the first frequency divider, and then the second frequency divider divides the output signal of the voltage controlled oscillator. Since the phase shifter is provided with a phase shifter that performs delay control according to a delay time until the phase shift, the reference signal from the first frequency divider input to the phase comparator and the second phase shifter are controlled by the delay control by the phase shifter. The phase error with the comparison signal from the frequency divider 2 can be made substantially constant within one cycle, and the frequency fluctuation at the time of the intermittent operation can be reduced to achieve a high-speed synchronous lock.

According to the second aspect of the present invention, after the control circuit detects the reference phase of the output signal of the first frequency divider, the second frequency divider determines the constant value and the delay time. Since the apparatus is provided with setting means and a phase shifter for adjusting according to the delay time until the output signal is divided, the constant value and the delay time are adjusted by the setting means and the phase shifter, so that the input to the phase comparator is performed. The phase of the reference signal from the first frequency divider and the phase of the comparison signal from the second frequency divider can be matched, thereby reducing the frequency fluctuation during intermittent operation and achieving high-speed synchronous locking. The effect is obtained.

[Brief description of the drawings]

FIG. 1 is a block connection diagram showing a phase locked loop device according to an embodiment of the present invention, FIG. 2 is a signal waveform diagram in each section of the circuit of FIG. 1, and FIG. 3 is a phase locked loop device according to another embodiment. FIG. 4 is a block diagram showing a conventional phase-locked loop device, and FIG. 5 is a signal waveform diagram in each section of the circuit shown in FIG. 1 is a reference oscillator, 2 is a first frequency divider, 3 is a phase comparator,
5 is a voltage controlled oscillator, 6A is a second frequency divider, 7 is a control circuit, and 14, 15 are phase shifters. In the drawings, the same reference numerals indicate the same or corresponding parts.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Tsutomu Tsutoda 8-1-1, Tsukaguchi Honcho, Amagasaki-shi, Hyogo Mitsubishi Electric Corporation Communication Equipment Works (72) Inventor Hirokazu Ishida 8-chome, Tsukaguchi-Honcho, Amagasaki-shi, Hyogo No. 1-1, Mitsubishi Electric Corporation Communication Equipment Works (56) References JP-A-60-114030 (JP, A) JP-A-61-196619 (JP, A) JP-A-61-157028 (JP, A) JP-A-61-269421 (JP, A) JP-A-59-157028 (JP, A)

Claims (2)

(57) [Claims] A first frequency divider for dividing an output frequency of a reference oscillator; a phase shifter for delay controlling an output signal of the first frequency divider; and a loop together with the first frequency divider. And a voltage controlled oscillator for outputting a signal having a frequency higher than the output frequency of the reference oscillator, a second frequency divider for dividing the output signal of the voltage controlled oscillator, and a second frequency divider And a phase comparator that compares the phase of the output signal of the first frequency divider input through the phase shifter and outputs the phase error as a phase control signal to the voltage controlled oscillator; A control circuit for detecting a reference phase of an output signal of the first frequency divider and releasing a reset of the second frequency divider;
After detecting the reference phase of the output signal of the frequency divider of
A phase-locked loop device, which performs delay control in accordance with a delay time until the frequency divider of (1) divides the output signal of the voltage-controlled oscillator. 2. A first frequency divider for dividing an output frequency of a reference oscillator, a phase shifter for delay controlling an output signal of the first frequency divider, and a loop together with the first frequency divider. And a voltage controlled oscillator for outputting a signal having a frequency higher than the output frequency of the reference oscillator, a second frequency divider for dividing the output signal of the voltage controlled oscillator, and a second frequency divider And a phase comparator that compares the phase of the output signal of the first frequency divider input through the phase shifter and outputs the phase error as a phase control signal to the voltage controlled oscillator; A control circuit for detecting the reference phase of the output signal of the first frequency divider and releasing the reset of the second frequency divider; and dividing the frequency from a constant value after the second frequency divider releases the reset. Setting the constant value to its second divider to start operation Means for setting the constant value set by the setting means and the delay time for controlling the delay of the phase shifter, after the control circuit detects the reference phase of the output signal of the first frequency divider, 2. The phase locked loop device according to claim 1, wherein the second frequency divider is adjusted in accordance with a delay time until the output signal of the voltage controlled oscillator is divided.