JPH02153627A - Phase locked loop device - Google Patents

Abstract

PURPOSE:To reduce the fluctuation of a frequency at the time of an intermittent action and to attain a high speed synchronous lock by setting a reference signal from a first frequency divider as a trigger, releasing the reset of a second frequency divider in a voltage control oscillator and providing a phase shifter between the first and second frequency dividers and a phase comparator. CONSTITUTION:When an intermittent signal 8 is turned on, a control circuit 7 turns on the power of respective circuits again and releases the reset of the first frequency divider 2. The first frequency divider 2 starts frequency-dividing the output frequency of the reference oscillator 1, the control circuit 7 detects the fall of the reference signal S1 which the first frequency divider outputs and simultaneously removes the reset of the second frequency divider 6A. At that time, a delay time from the fall of the reference signal S1 to the time when the second frequency divider 6 starts frequency-dividing the output signal of the voltage control oscillator 5. Thus, the phase difference at the time of generating the loop can be regulated within one period of the output signal of the voltage control oscillator 5, and the fluctuation of the frequency at that time of the intermittent action can be controlled, whereby a high speed synchronous characteristic can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a phase-locked loop device used in a frequency synthesizer circuit of a mobile radio device or the like.

[Conventional technology]

FIG. 4 is a block connection diagram showing a conventional phase-locked loop device. In the figure, 1 is a reference oscillator, 2 is a first frequency divider, which divides the output frequency of the reference oscillator 1 to produce an output signal. Outputs the reference signal as A phase comparator 3 compares the phases of the reference signal and the comparison signal and outputs a voltage control signal. A loop filter 4 smoothes this voltage control signal and supplies the smoothed control voltage to the voltage controlled oscillator 5. A second frequency divider 6 divides the output frequency of the voltage controlled oscillator 5 and outputs a comparison signal as an output signal. 7 is a control circuit which controls the first . Second frequency divider 2.6 and phase comparator 3 heliset signal 9, 10.1
Outputs 1. Reference numeral 12 denotes a falling detection signal as the comparison signal, and the control circuit 7 detects the falling edge of the comparison signal and controls the output timing of the reset signal 9.

Next, the operation will be explained.

When the intermittent signal 8 turns from on to off, the control circuit 7 first resets the phase comparator 3. The output of the phase comparator 3 becomes open, and the control voltage of the voltage controlled oscillator 5 is held at 0. Then, 1st. The second frequency divider 2.6 is reset, and the power to each circuit is turned off within a range that does not interfere with intermittent operation. FIG. 5 shows the reference signal S output by the first frequency divider 2.
1 and the output waveform of the comparison signal S2 outputted by the second frequency divider 6. At the time of reset, the first. The second frequency divider 2.6 outputs a low level "L", and the phase comparator 3 used here outputs both signals S1. It is assumed that the phase difference of the falling edge of S2 is detected.

Next, when the intermittent signal 8 turns on from off, the control circuit 7
turns on the power of each circuit again, releases the reset of the second frequency divider 6, and detects the fall of the comparison signal S2. At the same time as this detection, the reset of the first frequency divider 2 is released, but due to the deviation during this time, that is, the fall of the comparison signal S2,
The delay time until the first frequency divider 2 starts dividing the output signal of the reference oscillator 1 becomes a phase error. Finally, the reset of the phase comparator 3 is released and a loop is formed again. In FIG. 5, when a loop is formed, that is, while the above-mentioned deviation is occurring, the falling signal input to the phase comparator 3 has the above-mentioned phase error, so the control voltage of the voltage-controlled oscillator 5 fluctuates, and the output frequency fluctuates.

[Invention tries to solve! 11! [3 Since the conventional phase-locked loop device is configured as described above, when the loop repeats opening and closing, the maximum phase error when forming the loop is equivalent to one period of the output signal of the reference oscillator l. For,
The output frequency of the voltage controlled oscillator 5 fluctuates greatly, and
There were problems such as the time it took for the phases to synchronize. As such a conventional phase-locked loop device, there is a description of a similar technique in IEICE technical report C385-21.

This invention was made to solve the above-mentioned problems, and by regulating the phase error during loop formation to within one cycle of the output signal of the voltage controlled oscillator 5, frequency fluctuations during intermittent periods are suppressed. An object of the present invention is to obtain a phase-locked loop device that can achieve high-speed synchronization characteristics.

[Means to solve the problem]

The phase-locked loop device according to the present invention is capable of using the reference signal from the first frequency divider as a trigger to release the reset of the second frequency divider that outputs the comparison signal by the voltage controlled oscillator, and A phase shifter is provided between the first frequency divider that outputs the reference signal or the 20th frequency divider and the phase comparator.

[For production]

The second frequency divider that outputs the comparison signal in this invention is
Immediately after the reset is released, the input signal is counted from a certain value and the comparison signal is output, so the output waveform of the comparison signal immediately after the reset is released is almost constant with an error within one cycle of the input signal, and the first If the phase difference with the reference signal obtained through the frequency divider is not negligible, the phase shifter shifts the phase of the reference signal by a certain amount and operates to match the phases of both signals input to the phase comparator.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 6A is a second frequency divider, which is a frequency divider whose internal state at the time of reset is a constant value.

A phase shifter 14 shifts the phase of the reference signal Sl, which is the output signal of the first frequency divider 2. Note that other parts that are the same as those shown in FIG. 4 are designated by the same reference numerals, and redundant explanation thereof will be omitted.

Next, the operation will be explained. Now, it is assumed that the phase comparator 3 detects a falling phase difference between the reference signal S1 and the comparison signal S2, and outputs a voltage control signal according to this phase difference, as in the conventional case. Further, the operation of turning the intermittent signal 8 from on to off is also the same as in the conventional case.

First, we will explain the operation when the intermittent signal 8 turns on from off. When the intermittent signal 8 turns on, the control circuit 7 turns on the power of each circuit again and releases the reset of the first frequency divider 2. do. The first frequency divider 2 starts dividing the output frequency of the reference oscillator 1, and the control circuit 7 detects the fall of the reference signal S1 output from the first frequency divider 2. Simultaneously with this detection, the reset of the second frequency divider 6A is released. At this time, the delay time from the fall of the reference signal S1 until the second frequency divider 6A starts dividing the output signal of the voltage controlled oscillator 5 becomes a phase error. Here, since the second frequency divider 6A always starts dividing from a constant value immediately after reset is released, this phase error is reflected in the input signal to the second frequency divider 6A, that is, the output of the voltage controlled oscillator 5. It is approximately a constant amount, including only one cycle of frequency error.

The phase shifter 14 receives the reference signal S output from the first frequency divider 2.
1 is input to the phase comparator 3 after being delayed by a certain amount corresponding to the phase error.

Finally, the reset of the phase comparator 3 is released and a loop is formed again.

In FIG. 2, when a loop is formed, the signals SL and S2 of the first frequency divider 2 and the second frequency divider 6A have the phase error, but the reference signal output from the first frequency divider 2 Signal Sl
Since the phase shifter 14 compensates for the phase error, the phases of both signals input to the phase comparator 3 can be suppressed to within one cycle of the output frequency of the voltage controlled oscillator 5.

For example, if the output frequency of the reference oscillator l is 10 MH2° and the output frequency of the voltage controlled oscillator 5 is I GHz, both signals Sl and S2 input to the phase comparator 3 when forming a loop are
The phase difference, which was conventionally 100 nsec, is
It can be improved within n5ec.

In the above embodiment, only the reference signal St is phase-shifted by the phase shifter, but as shown in FIG. 3, the comparison signal S2 may also be passed through the phase shifter 15. for example,
If the polarity of the phase comparator 3 is reversed and the rising and falling edges of the reference signal Sl of the first frequency divider 2 are inverted using a logic circuit, the delay will be large and the phase of the reference signal Sl will be different from that of the comparison signal. This will lag behind the phase of S2. In such a case, by providing the phase shifter 15 also on the comparison signal 32 side, the phase difference can be compensated for, producing the same effect as in the above embodiment.

〔Effect of the invention〕

As described above, according to the present invention, the voltage controlled oscillator can release the reset of the second frequency divider by using the reference signal from the first frequency divider as a trigger, and Since the phase shifter is provided between the frequency divider, the second frequency divider, and the phase comparator, the second frequency divider counts the input signal from a predetermined value and outputs the comparison signal immediately after the reset is released. When the output waveform can be made almost constant with an error within one cycle of the input signal, and the phase difference with the reference signal output from the first frequency divider cannot be ignored, the phase shifter It is possible to match the phases of both signals by shifting the phase of the reference signal, thereby reducing frequency fluctuations during intermittent operation and achieving high-speed synchronization locking.

[Brief explanation of the drawing]

FIG. 1 is a block connection diagram showing a phase-locked loop device according to an embodiment of the present invention, FIG. 2 is a signal waveform diagram in each part of the circuit shown in FIG. 1, and FIG. 3 is a diagram showing a phase-locked loop device according to another embodiment. FIG. 4 is a block connection diagram showing a conventional phase-locked loop device, and FIG. 5 is a signal waveform diagram at various parts of the circuit shown in FIG. 1 is a reference oscillator, 2 is a first frequency divider, 3 is a phase comparator,
5 is a voltage controlled oscillator, 6A is a second frequency divider, 7 is a control circuit, and 14.15 is a phase shifter. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] a first frequency divider that divides the output frequency of the reference oscillator; a second frequency divider that divides the output of the voltage controlled oscillator that forms a loop with the first frequency divider; a phase comparator that compares the phases of the output signals of the frequency divider and the first frequency divider and inputs the phase error to the voltage controlled oscillator; A control circuit that releases the reset of the second frequency divider, and a delay in the phase of the output signal of the first frequency divider or the second frequency divider from the input of these input signals until the start of frequency division. A phase-locked loop device comprising a phase shifter that is controlled according to time.