JPH01146426A - Pll circuit - Google Patents

Abstract

PURPOSE:To supply a stable clock even against a rapid fluctuation of a phase of an input signal by storing an input clock signal in a memory tentatively prior to the input to a phase comparator circuit and giving it to a synchronization detection circuit counter counting clocks according to an external reference signal clock signal so as to control the frequency-division ratio of a frequency- division counter. CONSTITUTION:The input clock signal 1b is given to a memory 5 prior to the input to a phase comparator circuit 2. Simultaneously, the same input clock signal 1b is given also to a frequency detection counter 7. If the period of the input clock signal is changed, the frequency detection counter gives a change to a frequency-division controller 8, from which a reset or a load signal is given to a frequency-division counter 1a. Then the frequency-division ratio of the frequency-division counter 1a is varied optionally in response to the deviation of the period of the input signal. On the other hand, the memory 5 retards the input signal by a processing delay time till the control of the frequency-division counter 1a so as to always make the phase between the signal give to the phase comparator 2 and the output signal of the frequency- division counter 1a constant.

Description

[Detailed description of the invention] [Industrial application field] This invention is based on p L L (Phase Locked
The present invention relates to a loop (Loop) circuit, and particularly to a control circuit that suppresses phase synchronization of an output clock signal due to fluctuations in an input clock signal.

[Conventional technology]

FIG. 7 is a block diagram showing the configuration of a conventional PLL circuit. In the figure, (1) is a recovered clock (2a) obtained by dividing the output clock (4a) by a factor of N (N is an integer of 1 or more). ), (2) is the input clock (lb)
and a phase comparator that detects the presence or absence of a phase difference between the reproduced clock (2a), (3) a low-pass filter that filters the phase comparison output having an AC component from the phase comparator (2) and extracts the DC component; 4) is a voltage controlled oscillator whose oscillation frequency can be finely adjusted according to the output of the low-pass filter (3).

Next, the operation will be explained. In the initial state, the voltage controlled oscillator (4) generates an output clock (4a) by oscillating at a frequency near the center frequency according to the output of the low-pass filter (3). This output clock (4a) is frequency-divided by 1/N by a frequency divider counter (1) and is applied as a recovered clock (2a) as one input of a phase comparator (2). At this time, the input clock (lb) is applied to the other input of the phase comparator (2). The phase comparator (2) compares the phases of the input clock (1b) and the reproduced clock (2a), and outputs an AC signal corresponding to the lead or lag.

Here, the phase of the input clock (lb) is the reproduced clock (
If it is ahead of the phase of phase comparator (2a), then phase comparator (2a)
) is passed through the low-pass filter (3), the oscillation frequency fine adjustment voltage output from the low-pass filter (3) changes in the direction of increasing the oscillation frequency of the voltage controlled oscillator (4). As a result, the phase difference between the input clock (tb) and the reproduced clock (2a) of the frequency divider counter (1) decreases, and the two approach the same frequency and phase. Even if the oscillation frequency is increased by such an operation, if the phase of the input clock (lb) is still ahead,
By repeating these operations, the input clock (tb
) and the reproduced clock (2a) are corrected so that they have the same frequency and the same phase.

On the other hand, the phase of the input clock (1b) is
If it lags behind the phase of a), the phase comparator (2)
By passing the signal through the low-pass filter (3), the oscillation frequency fine adjustment voltage output from the low-pass filter (3) changes in the direction of lowering the oscillation frequency of the voltage controlled oscillator (4). Then, the phase difference between the input clock (1b) and the reproduced clock (2a) obtained by frequency division by the frequency division counter (1) decreases, and the phase of the input clock (lb) leads the reproduced clock (2a). As in the case where the two are connected, the two are brought close together so that they have the same frequency and the same phase. As a result of this operation, if the phase of the input clock (lb) is still delayed even if the frequency is lowered, the oscillation frequency is corrected by repeating the same operation.

As described above, the oscillation frequency is sequentially increased and decreased, and an output clock (4a) having the same frequency and phase as the input clock (1b) is obtained.

In this case, the oscillation frequency of the input for adjusting the oscillation frequency of the voltage controlled oscillator (4) is controlled in the vicinity of the center frequency so that the jitter component of the output clock (4a) does not increase.

Furthermore, when the input clock (1b) and the regenerated clock (4a) are in a synchronized state, the oscillation frequency fine adjustment voltage input to the voltage controlled oscillator (4) increases or decreases slightly in the vicinity of a predetermined DC voltage level. The phase is corrected in real time by repeating the steps.

[Problem that the invention seeks to solve]

Conventional PLL circuits lose phase lock when the phase of the input signal partially fluctuates and exceeds the output frequency fluctuation range of the voltage controlled oscillator. There were problems such as interference with signal processing. As an example, as shown in FIG. 3, if we take the case where an image synchronization signal is input, input signal 1 and input signal 2 are synchronized but out of phase, and these two input signals If the input signal is switched at the position of the arrow, the input signal becomes 3, and the phase changes partially, which eventually interferes with the output clock signal.

This invention was made to solve the above-mentioned problems, and its purpose is to provide a PLL circuit that can supply a stable clock without losing lock even in the face of rapid fluctuations in the input signal phase. do.

[Means for solving problems]

The PLL circuit according to the present invention temporarily stores the input clock signal in the memory before inputting it to the phase comparison circuit, and
The above input clock signal is input to the synchronization detection counter, where it is counted according to the external reference clock signal, and when a phase shift is detected, the frequency division controller sets the frequency division ratio of the frequency division counter that outputs the comparison clock signal to the phase comparison circuit. control,
After the control is completed, the input clock signal is input from the memory to the phase comparator circuit.

[Effect]

The synchronization detection kakunta according to the present invention detects the period deviation of the input clock signal by counting the period of the input clock signal in clock units, and when detecting the period deviation, gives the amount of change to the frequency division controller, and uses this amount of change to detect the period deviation of the input clock signal. The frequency division ratio of a frequency division counter is arbitrarily changed according to the period shift of an input clock signal. On the other hand, the memory delays the output of the input clock signal until the control of the frequency division counter is completed, and keeps the clock signal input to the phase comparator constant in phase with the output clock signal of the frequency division counter.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. In the figure, the same reference numerals as in FIG. 2 indicate the same or corresponding parts, and detailed explanation thereof will be omitted.

In the figure, (la) is the frequency division counter in this embodiment, (5) is the memory for delay time adjustment, (6) is the delay controller that controls the delay time, and (7) is the input clock signal (
1b) is a period detection counter that detects partial phase and period fluctuations, and (8) is a frequency division controller that controls the frequency division ratio of the frequency division counter (1a).

Next, the operation of this embodiment will be explained based on the above configuration. - As an example, a case will be described in which an image synchronization signal is input. Referring to the timing chart in Figure 3,
It is assumed that there are two systems of signals, input signal 1 and input signal 2, and input signal 1 and input signal 2 are synchronized but out of phase.

If the PLL is locked with gold input signal 1 and the input is instantaneously switched to input signal 2 at the point indicated by the arrow, the signal will become input signal 3 and the cycle will change. If this period shift exceeds the frequency variation range of the voltage controlled oscillator (4) shown in FIG. 1, the PLL will lose its lock. Therefore, the input clock signal (1b) is input to the memory (5) before being input to the phase comparator (2). At the same time, period detection counter (7)
Also input the doujin cuff lock signal (1b). The period detection counter (7) counts the period of the input clock signal (1b) in clock units, and when the period of the input clock signal changes, it gives the amount of change to the frequency division controller (8) and calculates the period from there. A reset or load signal is applied to the frequency division counter (la) to arbitrarily change the frequency division ratio of the frequency division counter (la) according to the period shift of the input signal (see FIG. 3). On the other hand, the memory (5) uses the frequency dividing counter (1
The input signal is delayed by the processing delay time until controlling a), and serves to keep the phase of the signal input to the phase comparator (2) constant with respect to the output signal of the frequency division counter (la). A delay controller (6) controls the amount of delay in this memory (5).

In the above embodiment, when an image synchronization signal is input,
Although we have explained the case where input signal 1 is switched to input signal 2 as shown in Fig. 3, not only is there a period shift when switching the input signal, but also the jitter of the input signal is large.
A similar effect can be obtained even in cases where the control range of the conventional PLL is exceeded. Further, the input signal can have any frequency as long as it is the frequency output from the voltage controlled oscillator (4), and the duty ratio does not matter.

〔Effect of the invention〕

As described above, according to the present invention, the frequency and phase of the input to the phase comparator can always be made to match by changing the clock division ratio to compensate for partial phase changes in the input signal, so phase synchronization is achieved. There is no deviation, and a stable clock can always be supplied.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a PLL circuit according to an embodiment of the present invention. FIG. 2 is a block diagram showing a conventional PLL circuit, and FIG. 3 is a timing chart according to an embodiment of the present invention. In the figure, (1a) is a frequency division counter, (2) is a phase comparator, (3) is a low-pass filter, (4) is a voltage controlled oscillator, (5) is a memory, (6) is a delay controller, ( 7) is a period detection counter, and (8) is a frequency division controller. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Agent Masuo Oiwa

Claims (1)

[Claims] The phase of the recovered clock obtained by dividing the output clock of the voltage controlled oscillator whose frequency changes in response to the DC voltage signal using a frequency division counter, and the phase of the reference clock obtained by dividing the external input lock. Compare with using a phase comparator,
The PLL circuit smoothes the output signal of this phase comparator and applies it to the voltage controlled oscillator, which includes a memory that stores the input clock for a certain period of time before inputting it to the phase comparator, and a memory that inputs the input clock and receives an external reference clock. a period detection counter that detects a period deviation of the input clock in comparison with the period of the input clock;
The present invention is characterized by comprising a frequency division controller that controls the frequency division ratio of the frequency division counter according to the amount of period variation, and a delay controller that delays reading out the input clock from the memory until the frequency division ratio control is completed. PLL circuit.