JPH0435416A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To permit a reference signal to reach synchronization in a short time when the reference signal which once stops is restored by providing a circuit detecting the stop of the reference signal and a control circuit stopping input for a frequency divider based on the output of the detection circuit. CONSTITUTION:The circuit 5 detecting the stop of the reference signal and the control circuit 6 stopping input for the frequency divider 2 based on the output of the detection circuit 5 are given. When the reference signal fi stops, the detection circuit 5 detects it, and the control circuit 6 stops input for the frequency divider 2. Consequently, the output of the frequency divider 2 becomes zero and the operation of phase comparison is interrupted. When the reference signal fi restores, the detection circuit 5 releases the stop operation by the control circuit 6 and a phase locked loop circuit resumes the synchronization operation from the state of interrupted time. Thus, time required for the reference signal which once stops reaches a synchronous state after it is restored can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a phase synchronization circuit for obtaining an output signal of an oscillation frequency synchronized with an input reference signal.

[Conventional technology]

FIG. 3 is a block diagram showing this kind of conventional phase synchronization circuit. In the figure, (1) is a phase comparator, which calculates the difference in the rising timing of the reference signal f, which is the original signal, and the signal ftb, which is a comparison signal from the frequency divider (2), which will be described later, as a phase difference. The signal f corresponding to the phase difference is recognized.
Outputs 8. (3) is a low-pass filter that smoothes the signal f and converts it into a DC voltage value vCO; (A) is a voltage-controlled oscillator that generates a pulse train f0 with a frequency proportional to the DC voltage value vCO; and a frequency divider (2). is the pulse train f. is frequency-divided and output as signal ftb.

Next, the operation will be explained with reference to the time chart shown in FIG. Now, as shown in period (a) in FIG.
The output signal fi of 1) becomes larger during the phase shift period, and the output vCO of the low-pass filter B) also increases accordingly. As a result, the frequency of the pulse train f0 also increases, and the frequency divider port operates to advance the phase of its output signal ftb.

As a result of this phase advancing operation, as shown in period (b), when the output phase of the frequency divider ■ advances (or the frequency becomes higher) than the reference signal f+, the output signal of the phase comparator (1) f1 becomes smaller during the out-of-phase period, and the output vCO of the low-pass filter (3) also decreases accordingly. As a result, the frequency of the pulse train f0 becomes lower and the frequency divider port operates to delay the phase of its output signal fsb.

As described above, the output signal ffb of the frequency divider (2) performs a negative feedback control operation in which it becomes a feedback signal for the reference signal f, and the synchronization state of both signals is maintained while repeating a slight phase lead and a phase delay. That's what you get.

[Problem to be solved by the invention]

Next, the operation when the reference signal f1 stops for some reason during the above control operation will be described. now,
Assuming that the reference signal f stops at time (A) shown in FIG. The phase synchronized circuit operates to delay its output phase. However, the reference signal f
Since I remains stopped, the phase is further delayed, and eventually the output voltage vCO of the low-pass filter (3) reaches the lowest level. As a result, the voltage controlled oscillator (a) outputs the pulse train f0 of the lowest level frequency.

In such an uncontrolled state, for example, if the reference signal f is restored at the time indicated by time CB> in FIG.
The phase comparator (1) determines that the output signal ffb of the frequency divider (2) leads the reference signal f1 in phase.

Therefore, the low-pass filter (3) still outputs a command to delay the phase even though the output voltage vCO is saturated at the lowest level. Then, it is determined that the output signal ffb lags behind the reference signal f1 for the first time at the time of the next phase comparison, and an operation to advance the phase (or increase the frequency) is started.

In general, the low-pass filter (3) is composed of a large integral element (capacitor), and the output voltage VCO of the low-pass filter (3), once saturated, rises slowly, and the phase comparator (1) The phase synchronization level is finally reached after phase comparison is performed several times and the phase advance command is repeated.

As described above, in the conventional phase synchronization circuit, there is a problem that when the reference signal f stops once and then returns, resynchronization after the return takes a long time depending on the timing of the return.

The second invention was made to solve the above-mentioned problems, and aims to provide a phase-locked circuit that can reach synchronization in a short time when the reference signal that has been stopped is restored. .

[Means to solve the problem]

The phase synchronized circuit according to the present invention includes a circuit for detecting stoppage of a reference signal and a control circuit for stopping input to a frequency divider based on the output of this detection circuit.

[For production]

When the reference signal stops, the detection circuit detects this, and in response to this, the control circuit stops the input to the frequency divider. Accordingly, the output of the frequency divider becomes zero and the phase comparison operation is also interrupted.

When the reference signal returns, the detection circuit releases the above-mentioned stop operation by the control circuit, and the phase synchronization circuit resumes the synchronization operation from the state at the time of the above-mentioned interruption.

(Embodiment) Fig. 1 is a block diagram showing a phase synchronization circuit according to an embodiment of the present invention.In the figure, (1) to 4)
are the same as or equivalent to the conventional ones with the same symbols, but among these, the frequency divider ■ is the conventional signal fib
In addition to this, a signal f fb+ which rises at a timing slightly earlier than this signal f fb is output.

(5) is a detection circuit that detects the stoppage of the reference signal; (6) is a control circuit that controls the input clock of the frequency divider (2);
It consists of an AND gate (9) and an inverter (10).

Next, the operation will be explained. However, when the reference signal f+ is present, the clock stop signal STP is at L level as described later, and the AND gate (9) directly converts the R pulse train f0 from the voltage controlled oscillator (4) into a frequency divider. Since the operation of the phase locked circuit is the same as that of the conventional circuit, the explanation thereof will be omitted since it will be redundant.

Therefore, the operation assuming the case where the reference signal t1M- is stopped and then restored after a predetermined period of time will be described in detail with reference to the flowchart of FIG.

Now, suppose that the reference signal f+ stops at time (A) shown in FIG.
I) and outputs a stop signal LOS. In response to this signal, the flip-flop block 1 (7) outputs a clock stop signal STP at the rising timing (A2) of the signal fab+ from the frequency divider (2). As a result, the AND condition of the AND gate (9) is not satisfied, the input to the frequency divider (2) is stopped, and the operation of the frequency divider port is suspended.

The clock stop signal STP is simultaneously passed through a low-pass filter (3
) is discharged.

Assuming that the reference signal f1, which has been temporarily stopped as described above, returns at time (B) shown in FIG. 2, the detection circuit (
The stop signal LO3 of the inverter (to
10) and the rising edge of the reference signal f+, the flip-flop 28 operates and sends a reset signal to the flip-flop 1 (7). As a result, the clock stop signal STP is reset and becomes L level, the AND condition of the AND gate (9) is satisfied, the pulse train f0 is input, and the frequency divider (2) resumes its operation.
Since the frequency divider port was in an interrupted state at the rising edge of the signal flk+ (A2), by restarting the operation,
When a preset difference in rise time between the signals fib+ and fob has elapsed, the signal ftb is caused to rise (time (old) in FIG. 2). At the same time as the clock stop signal STP is lost, the integral element of the low-pass filter (3) resets.
The output vCO rises instantaneously and is further increased by the signal f1 from the phase comparator (1). From then on, the original synchronization operation continues.

As described above, in this embodiment, when the reference signal f0 is restored, the phase comparison operation is started from a state where the reference signal f+ and the signal flb, which is the comparison signal, have a preset extremely small phase difference. The time required to reach a synchronized state after recovery will be significantly reduced.

Note that in the above embodiment, the new signal f from the frequency divider (2)
This signal fxb outputs tb+ and interrupts the frequency divider (2).
I made it to be performed at the timing of the rise of +, but
The detection circuit (9) may be interrupted at the timing of the rise of the stop signal LOS from 9. In this case,
The conventional problem of the operating level of the voltage controlled oscillator (a) reaching its saturation range while the reference signal f+ is stopped is resolved, so the time it takes to achieve synchronization after the signal returns is shorter than before. is shortened.

Furthermore, the operation of the integral element of the low-pass filter B) based on the clock stop signal STP is not necessarily necessary for the configuration of the present invention, and may be omitted to simplify refinement.

〔Effect of the invention〕

As described above, in the present invention, since the predetermined detection circuit and control circuit are added, the time required to reach the synchronized state after the reference signal which has been temporarily stopped is restored is shortened.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a phase locked circuit according to an embodiment of the present invention, FIG. 2 is a time chart for explaining its operation, and FIGS. 3 and 4 are block diagrams showing conventional ones. and a time chart. In the figure, (1) is a phase comparator, (2) is a frequency divider, (
3) is a low-pass filter, (2) is a voltage controlled oscillator, +
51 is a detection circuit, (6) is a control circuit, f is a reference signal,
ftb is a comparison signal. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent: Masuo Oiwa, Patent Attorney

Claims (1)

[Claims] A phase comparator that detects the phase difference between the reference signal and the comparison signal and outputs a signal according to this phase difference, a low-pass filter that smoothes the signal output from this phase comparator, and a low-pass filter that smooths the signal output from this low-pass filter. a voltage-controlled oscillator that outputs a signal with a frequency proportional to the signal output from the voltage-controlled oscillator, and a frequency divider that divides the frequency of the signal output from the voltage-controlled oscillator and outputs the frequency-divided signal to the phase comparator as the comparison signal, A phase-locked circuit comprising: a circuit for detecting stoppage of the reference signal; and a control circuit for stopping input to the frequency divider based on the output of the detection circuit.