JPS6037664B2 - Out-of-sync detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an out-of-synchronization detection circuit in a phase control system.

This phase control system is constructed using the generally well-known PLL (P
This will be explained below using the (haseLockedLoop) circuit as an example.

Figure 3 shows a block of the PLL circuit, where 1 is a voltage controlled oscillator (Volta oscillator).
tor (hereinafter referred to as VCO).

The output signal of this VCOI and the reference signal from the reference signal oscillator 4 are phase-compared by a phase comparator (PSD) 3, and the output of the phase comparator 3 is applied to the VCOI to perform phase synchronization. . Note that in the figure, 13 is an output terminal of the VCOI. The VCOI is an oscillator whose oscillation frequency is determined by the output control signal voltage of the phase comparator 3, and its output is applied to the phase comparator 3 to form a feedback system of the PLL.

FIG. 4 shows the frequency tracking characteristic of the PLL when the output error voltage of the phase comparator 3 is Ve.

In the configuration shown in Fig. 3, when the VCOI is currently oscillating at the center frequency, an input signal with a frequency f is applied to the input signal, and the input signal frequency f is gradually increased from the lower frequency to the higher frequency. Then, at f/fl, the PLL is pulled in by the input signal, and the VCOI oscillates synchronously at the same frequency as the input signal until f reaches f2.

When synchronization is lost at f=f2, the oscillation frequency f of the VCOI goes back up a notch. Next, when the input signal frequency f is gradually lowered from the higher frequency side to the lower frequency side, at f=f3, the PLL is drawn into the input signal, and the above VCO oscillates synchronously. When synchronization is lost at f=f4, the VCO
The oscillation frequency f of I is pushed back. above fl>f>f3
The range 2△℃ is the frequency pull-in range (Pull-in range; P
ullinrange), and the range 2△ mountain of f2>f>f4 is locked range (mountain ckran connection), and furthermore, f6
The range 2△yama 1 inch of >f>f5 is called the phase entrainment range (lock-in range; mountain ck-jnran trout).

Until a signal is applied to the PLL, there is no output voltage from the phase comparator 3 and the phase control system is in an open state. Generally, the frequency and phase of the input signal are determined by the frequency and phase of the VCOI in a successful oscillation state. They do not match because they are not in a synchronous relationship.

Therefore, it can be considered that synchronization occurs in a two-step range, in which the frequencies first become close in the frequency pull-in range, and then synchronization occurs in the phase pull-in range. That is, when input signals with different frequencies are applied to the phase comparator 3, the phase comparator 3 operates as a mixer because it has non-linear operating characteristics, and uses the output signal of the VCOI as a local oscillation signal to mix both signals. Generates a beat signal output corresponding to the frequency difference.

If this beat frequency is below a certain value determined by the characteristics of the grandchild, the VCOI will gradually shorten the frequency difference and synchronize, but outside of that range, the frequencies will only repeat approaching and departing, and the average There is no frequency reduction and cannot be synchronized.

However, if the PLL can respond to the beat frequency, it will act to bring the oscillation frequency of the VCOI closer to the input frequency during the positive half cycle of the beat signal waveform, and move it away from it during the negative half cycle.

This causes a change in the beat waveform, which changes slowly in the positive half cycle and quickly in the negative half cycle.As a result, the average DC level shifts toward the positive side in one cycle of the beat waveform, and this DC The closer the frequency of the VCOI to the input signal in minutes, the shorter the frequency difference. Then, an even larger DC component is generated, and the frequency gradually follows the frequency at an accelerated pace due to the positive feedback effect. This range is the pull-in or frequency pull-in process. Next, when the frequency difference is below a certain level,
The response of the PLL can completely follow the beat waveform, and synchronization is established.

This process is lock-in or phase entrainment. The time required for the PLL to synchronize with the input signal frequency is represented by the sum of the pull-in frequency pull-in time and the lock-in phase pull-in time.

There are various types of circuits that detect out-of-synchronization in the above-mentioned phase control system, but in these circuits, the detection time of out-of-synchronization or the resolution of out-of-synchronization detection (how much out of synchronization is considered as out-of-synchronization) ), and it was not possible to satisfy both of them at the same time. SUMMARY OF THE INVENTION An object of the present invention is to provide an out-of-synchronization detection circuit that can detect out-of-synchronization in a short time and is easy to dismantle, while eliminating the above-mentioned conventional drawbacks.

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, 1 is a voltage controlled oscillator, 2 is a variable frequency divider for dividing the output of the VCOI, and 3 is a reference signal oscillator 4.
The output of the phase comparator 3 is applied to the VCOI, thereby controlling the oscillation frequency of the VCOI. 5 is a frequency divider that divides the reference signal into 1/8, and 6 and 7 are both 1/2 frequency dividers, which constitute a counter 10 and divide the output of the VCOI.

8 is a gate circuit that oscillates the outputs of frequency dividers 6 and 7; 9
is a storage circuit that stores the output of the gate circuit 8.

Further, the output of the frequency divider 5 is given to the frequency dividers 6 and 7 to set or reset them, and also to set or reset the frequency dividers 6 and 7.
is given to trigger it and cause it to change its memory state.
Next, we will discuss the operation.

The output of the VCOI is frequency-divided by a variable frequency divider 2, converted into a signal having a frequency approximately equal to the frequency of the reference signal, and then provided to a phase comparator 3. The phase comparator 3 compares the phase difference between the two signals and provides an output corresponding to the phase difference to the VCOI. This controls the oscillation frequency of the VCOI,
In the end, the oscillation frequency fo of the VCOI is equal to n×fr. Here, n: division ratio of the variable frequency divider 2, h: frequency of the reference signal. Therefore, in the synchronous state, the second
As shown in the figure, there are n VCs in one pulse section of the reference signal.
Since the O output pulse is occurring, there are 4n VCO output pulses in the half section of the output of the duplexer 5, for example, the section B.

This means that even if the frequency division ratio n of the variable seat divider 2 is changed,
This means that the number of pulses entering the section B is always an integral multiple of 4. Therefore, A of the output of frequency divider 5
In the interval, the frequency dividers 6 and 7 are reset to the state (in this state, it is assumed that the frequency dividers 6 and 7 are both "0", and this is set as the output state of the counter 0 ( 0,
0)), and if only the section B is set and operated, the output state of the cursor 10 at the end of the section B will be (1, 0) regardless of the value of n. 1
).

However, counter 0 changes every pulse from (0, 0) to
(0,1)→(1,0)→(1,1)→(0,0)→・
Assume that the output state changes as follows. Therefore, if the frequency deviates by, for example, two pulses, the output state of the counter 10 will be (0) at the end of section B.
,1).

Here, if the gate circuit 8 is designed to determine only the state (0, 1) as out-of-synchronization, the deviation of the two pulses can be determined as out-of-synchronization. On the other hand, (1,1), (0,0), and (1,0) are determined to be in a normal state. These determination results are stored in the storage circuit 9 at the end of section B. In addition, in the above case, in addition to the original normal state (1, 1), the states on both sides of it (0, 0) and (1, 0) are also determined to be normal states. This is to ensure that even if a circuit element (such as an IC) malfunctions if the time point at which the output of counter 0 changes and the time point at which the output of frequency divider 5 changes are almost equal, it will still remain within the normal range. be.

As is clear from the above explanation, as for the decomposition of the times in Figure 1, if the frequency/number of pulses deviates by two or more out of 4n pulses, it is possible to determine out of synchronization, but in general, n is a variable frequency divider. 2, the resolution is much higher than the normal resolution.

Further, the detection time is 8 clocks of the reference signal when there is a two-pulse shift, and it can be seen that this is also a very short time. Furthermore, the circuit can be easily constructed by using about 2 to 3 ordinary ICs. In the circuit shown in FIG. 1, pulses are only sporadically generated as the out-of-synchronization detection output, but in order to extend these pulses, a pulse extension circuit may be added.

Further, in the above embodiment, the frequency division ratios of the counter 10 and the frequency divider 5 are set to 1'4 and 1/8, respectively, but it is of course possible to change these as appropriate, and to adjust the detection time and resolution appropriately. It is possible to design to obtain the following characteristics. As described above, according to the present invention, an out-of-sync detection circuit with short detection time and high resolution can be easily obtained.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the out-of-sync circuit of the present invention, Fig. 2 is a chart for explaining the operation of the circuit shown in Fig. 1, and Fig. 3 is an example of a PLL using a conventional VCO. Figure 4 is a block circuit diagram showing the VC shown in Figure 3.
FIG. 1... Voltage controlled oscillator, 2... Variable frequency divider, 3...
・Phase comparator, 4...Reference signal oscillator, 5, 6, 7・
... Frequency divider, 8... Gate circuit, 9... Memory circuit. Figure 2 Figure 1 Figure 3 Figure 4

Claims (1)

[Claims] 1. A reference signal oscillator that generates a reference signal, a phase comparator that receives the reference signal from this reference signal oscillator as one input, and a voltage-controlled oscillator whose oscillation frequency is controlled by the output control signal from this phase comparator. In the out-of-sync detection circuit in the phase control system, the output signal of the voltage controlled oscillator is inputted to the other input of the phase comparator, the output signal of the voltage controlled oscillator is variably divided and the output signal of the voltage controlled oscillator is inputted to the other input of the phase comparator. a first frequency divider that divides the frequency of the reference signal; a second frequency divider that divides the output signal of the voltage controlled oscillator; A gate circuit for determining out-of-synchronization based on the output state of the frequency divider, and a storage circuit for storing the output of the gate circuit, 1. An out-of-synchronization detection circuit, characterized in that it sets or resets a device and changes the storage state of a storage circuit.