JPS60247330A - Unlock detecting circuit - Google Patents

Abstract

PURPOSE:To deliver an unlock signal at a fixed level for a period during which a PLL is locked completely from an unlock state without receiving the effects due to the variance of the power voltage and the temperature, by using a counter which produces a phase difference discriminating signal with an output signal of a phase comparator defined as an input and delivers an unlock signal for a prescribed period with an AND between said discriminating signal and a pulse of a fixed time width synchronous with a reference signal defined as a reset signal. CONSTITUTION:A PLL is unlocked and the pulse width of a phase difference discriminating signal (c) delivered from a phase difference discriminating circuit 4 exceeds the pulse width of an output signal (d) of a pulse width generating circuit 16. Under such conditions, an output signal (e) of an H level is obtained and supplied to a reset terminal R of a counter circuit 22. Thus the circuit 22 starts counting reference signals fref. When the PLL is completely locked, the circuit 22 counts the signals fref since the signal (e) of an AND circuit 21 is always kept at L. Then the gate of an AND gate 23 is closed when the count value of the circuit 22 reaches the prescribed level.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a PLL that sets the oscillation frequency of a voltage controlled oscillator by varying the division ratio of a programmable divider.
(Phase Lock Loop)
The present invention relates to an unlock detection circuit that detects lock and unlock states and generates signals in a frequency p7 synthesizer.

[Prior art]

An example of a conventional unlock detection circuit is shown in FIG. 3 is an input terminal to which an output signal fl/s frequency-divided by a programmable divider (not shown) is applied; A phase comparator 4 detects a phase difference, and 4 is a phase difference discrimination circuit which receives the output of the phase comparator 3 as an input.
is constituted by an inverter 5 which receives one output of the inverter 5 as an input, and a Nant gate 6 which receives the output of the inverter 5 and the other output of the phase comparator 3 as inputs. I is a charge pump connected to the output side of this phase difference discrimination circuit 4, and 8 is an output terminal from which an output signal PD of this charge pump 1 is obtained. 9 is a pulse width detection circuit which receives the branch output of the phase difference discrimination circuit 4 as an input, and a resistor 10 which receives the output of the Nandt gate 6 of the phase difference discrimination circuit 4;
A capacitor 11 connected in series with the capacitor 11. The inverter 12 includes an integrator circuit and an inverter 12 which receives the output of this integrator circuit. Further, 13 indicates a phase difference discrimination signal obtained by the phase difference discrimination circuit 4, and 14 indicates an unlock signal obtained by the pulse width detection circuit 9.

Figure 2 is an operation explanatory diagram showing the signal waveforms of each part used in the operation of Figure 1. (a) shows the waveform of the reference signal f ref, and (b) shows the waveform of the reference signal f ref divided by the programmable divider. The output signal f1/N1 (C) is the charge pump 7
The output signal P D , (d) is the phase difference discrimination signal 13, (
e) is the output signal of the integrating circuit, (f) is the unlock signal 1
4 shows each waveform. And vT indicates the threshold voltage of the inverter 12.

Next, the operation of the unlock detection circuit shown in FIG. 1 will be explained with reference to FIG. 2.

First, the reference signal fref shown in FIG. 2 (a3) and the output signal h/
The phases are compared in the 1iFi phase comparator 3, and the phase difference discrimination signal enters the charge pump T via the phase difference discrimination circuit 4, and its output is a charge pump with a waveform as shown in FIG. 2(e). An output signal I'D is obtained. Next, FIG. 2(d) K discriminated by the phase difference discrimination circuit 4
A phase difference discrimination signal 13 having a waveform as shown in FIG.
By inputting the integrated waveform (see FIG. 2(e)) to the inverter 12, the signal Fi shown in FIG. 2(f) is input to the output terminal 14.
An unlock signal with a waveform as shown in is obtained.

However, in such an unlock detection circuit, accurate pulse width detection is difficult because the threshold voltage Vrn of the inverter 12 of the pulse width detection circuit 9 changes due to fluctuations in the power supply voltage or changes in temperature. There was a drawback. Furthermore, when the unlock signal is a muting signal, there is a drawback that a pulsed signal causes interruptions in the sound.

[Summary of the invention]

In view of the above points, the present invention has been made to solve such problems and eliminate such drawbacks.The purpose of the present invention is to have a simple circuit configuration that is not affected by fluctuations in power supply voltage or temperature. An object of the present invention is to provide an unlock detection circuit capable of outputting an unlock signal as a constant level signal until a PLL is completely locked from an unlocked state.

In order to achieve such an object, the present invention provides a phase difference discrimination circuit that receives the output signal of a phase comparator as input and generates a phase difference discrimination signal, and a pulse width discrimination circuit that generates a pulse with a constant time width synchronized with a reference signal. The pulse width generating circuit includes a generating circuit, and a counter that outputs an unlock signal for a predetermined period using the logic of the output of the phase difference discrimination circuit and the output of the pulse width generating circuit as a reset signal.

[Embodiments of the invention]

Embodiments of the present invention will be described in detail below based on the drawings.

FIG. 3 is a circuit diagram showing an embodiment of the unlock detection circuit according to the present invention, and only the parts necessary for explanation are shown.

In FIG. 3, the same reference numerals as in FIG. 1 indicate corresponding parts, and 15 is an input terminal to which a clock signal fck, which is usually generated by dividing a highly stable frequency oscillated by a crystal oscillator, is applied; 16 is the reference signal fr from input terminal 1
This is a pulse width generation circuit that generates a pulse for a certain period of time in synchronization with ef', and the reference signal fre from input terminal 1 is connected to the D terminal.
D type flip-flop 1B inputs the output from the Q terminal of this flip-flop 17 to the D terminal, and D inputs the Uj force from the Q terminal of this flip-flop 1B to the D terminal. It consists of a type flip-flop 19 and a Nant gate 20 whose inputs are the output from the Q terminal of this flip-flop 1B and the output from the silk terminal of the 7-type flip-flop 17. Then, the clock signal fc from the input terminal 15
k is configured to be supplied to each T terminal of each of these flip-flops 17 to 19, respectively. Also,
The output from the Q terminal of the D-type flip-flop 1B is configured to be supplied to the phase comparator 3 as a reference signal fref.

21 is an AND circuit which receives the output of the Nant's gate 20 of this pulse width generating circuit 16 and the output of the Nand's gate 6 of the phase difference discrimination circuit 4, and calculates the AND of the inner inputs; 22, the output of the phase difference discrimination circuit 4 and the pulse; This is a counter circuit that uses the AND output of the output of the width generation circuit 16 as a reset signal and outputs an unlock signal for a predetermined period.The output from the Q terminal of the D-type flip-flop 18 of the pulse width generation circuit 16 and the T-type clip-flop described later are used as counter circuits. An AND gate 23 which takes the output from the glue terminal 26 as an input and performs the logical product of the inner inputs, and a T-type flip-flop 2 which inputs the output of this AND gate 23 to the T terminal.
4, a T-type flip-flop 25 that inputs the output from the Q terminal of this flip-flop 24 to the T terminal, and a T-type flip-flop 26 that inputs the output from the Q terminal of this flip-flop 25 to the T terminal. . The output from the i terminal of this T-type clip-flop 26 is output to the output terminal 27 as an unlock output signal.
and the AND gate 21
The output is configured to supply a reset signal to each reset terminal R of each of these T-type flip-flops 24-26.

FIG. 4 is an operation explanatory diagram showing signal waveforms of each part to explain the operation of FIG. 3, and (a) shows the waveform of the reference signal fref input to the phase comparator 3.

(b) is the output signal f1. which is frequency-divided by the programmable divider and input to the phase comparator 3. /N, (c) is the phase difference discrimination signal that is the output of the phase difference discrimination circuit 4, 0) is the output signal of the pulse width generation circuit 16, (e) is the AND circuit 21
(f) shows each waveform of the unlock signal which is the output signal of the counter circuit 22 obtained at the output terminal 2T.

Next, the operation of the embodiment shown in FIG. 3 will be explained with reference to FIG. 4.

First, the reference signal f r ef' applied to input terminal 1
Three stages of D-type flip-flops 17 to 1 are connected in cascade.
9, the signal is delayed one clock at a time by the clock signal fck applied to the input terminal 15, and the Q output of the first stage D-type flip-flop 1f and the Q output of the third stage D-type flip-flop 19 are By inputting it to the gate 20, the output signal from the Q terminal of the second-stage D-type flip-flop 18, that is, one clock before and after the falling edge of the reference signal fref shown in FIG. The pulse waveform d(
0)) is obtained. Here, as mentioned above, the frequency of the clock signal fck applied to the input terminal 15 is usually created by dividing a highly stable frequency such as a crystal oscillator, so As for d, a signal with an accurate pulse waveform can be obtained.

Next, the PLL becomes unlocked, and the phase difference discrimination signal C (see FIG. 4(C)) is output from the phase difference discrimination circuit 4.
) is the output signal d of the pulse width generation circuit 16.
(See FIG. 4(d)), the AND circuit 21 outputs a 1H'' level output signal e with a waveform as shown in FIG. 4(e). By inputting the output signal e of this AND circuit 21 to the reset terminal R of the counter circuit 22, the counter circuit 22
The output signal f (see FIG. 4(a)) goes to H'' level and opens the gate of the AND gate 23, so that the reference signal fref (see FIG. 4(a)) goes to the counter circuit
The count begins. While counting this reference signal f ref, when a 1H'' level signal e is input from the AND circuit 21 to the reset terminal R, the counter value is reset each time. The unlock signal f (see FIG. 4(f)), which is the output from the four terminals of the T-type flip-flop 26 in the third stage, is %Hl/
It remains at the level.

Next, when the PLL is completely locked, the output signal e of the AND circuit 21 is always at the %L/level, so the counter circuit 22 counts the reference signal fref, and when it reaches a predetermined value, the counter circuit 22 counts the reference signal fref. The output from the cascade-connected third-stage T-type flip-flop 260ζ terminal of the counter circuit 22 becomes 1L'' level, and the gate of the AND gate 23 is closed, so that counting is no longer performed and the output becomes 1L'' level.

In this way, as an unlock signal, a 1H'' level signal is obtained when the PLL is in the unlocked state, and a 1L'' level signal is obtained when the PLL is in the locked state. These signals are not affected by fluctuations in power supply voltage or temperature.

Although the present invention has been described above using as an example a case where a counter circuit using three stages of T-type flip-flops is provided, the present invention is not limited to this, and unlocking can be achieved by changing the number of stages of the counter circuit. The time of the signal can be varied.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, a simple configuration including a phase difference discrimination circuit, a pulse width generation circuit, and a counter circuit can be used to compensate for fluctuations in power supply voltage and temperature without using complicated means. It will not be affected (,P
Since the unlock signal can be output as a constant level signal until the LL is completely locked from the unlocked state, the practical effect is extremely good.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of a conventional unlock detection circuit, FIG. 2 is an explanatory diagram of the operation of FIG. FIG. 4 is an explanatory diagram of the operation of FIG. 3 of Zusha. 3... Phase comparator, 4... Phase difference discrimination circuit, 1
6 fists...Pulse width generation circuit, 21...-AND circuit, 22* 11 @ e counter circuit. Agent Masu Oiwa ・Male Figure 1 λ, >ocf, 1+-Q-Q-,,.

Claims (1)

[Claims] It includes a phase comparator that detects the phase difference between the output signal obtained by dividing the oscillation output of the voltage controlled oscillator by a programmable divider and a reference signal, and when the division ratio of the programmable divider is varied, the oscillation frequency of the voltage controlled oscillator is increased by K. A PLL frequency synthesizer that sets a phase difference discrimination circuit that receives the output signal of the phase comparator as an input and generates a phase difference discrimination signal, and a pulse width generation circuit that generates a pulse with a constant time width synchronized with the reference signal. An unlock detection circuit comprising: a counter that uses the AND of the output of the phase difference discrimination circuit and the output of the pulse width generation circuit as a reset signal and outputs an unlock signal for a predetermined period of time.