JPH07297712A - Phase locked loop synthesizer - Google Patents

Abstract

PURPOSE:To switch the frequency of the PLL frequency synthesizer at high speed with small current consumption. CONSTITUTION:In the PLL frequency synthesizer having a variable oscillator circuit 1, a phase comparator 2, a low pass filter circuit 3 and a voltage controlled oscillator 4, an output of the variable oscillator circuit 1 being a reference frequency of the loop and a divided frequency from the variable frequency divider 7 being a divided frequency of the loop are switched simultaneously at the switching of the loop frequency. The frequency division ratio is increased at the frequency setting and decreased after lapse of prescribed time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop synthesizer, and more particularly to a high speed and low power consumption PLL (phase locked loop) frequency synthesizer.

[0002]

2. Description of the Related Art FIG. 7 shows a block diagram of a conventional PLL frequency synthesizer for changing a reference frequency. In the figure, 1 is a variable oscillator circuit, 2 is a phase comparator that compares the phases of two input frequencies, and outputs a signal corresponding to the phase difference, for example, a signal having a pulse width corresponding to the phase difference, 3 Is a low-pass filter circuit, 4 is a voltage controlled oscillator (VC) that outputs a frequency corresponding to the input voltage.
O), 5 is a fixed frequency divider, and 6 is a data setting circuit for outputting data to the variable oscillation circuit 1.

Next, the operation will be described. The variable oscillation circuit 1 changes the output frequency according to the data from the data setting circuit 6, and inputs it to the phase comparator 2 as the reference frequency. The voltage controlled oscillator 4 outputs a frequency corresponding to the control voltage. One of the two divided outputs is output to the output side and the other is output to the fixed frequency divider 5 as the feedback side.
The fixed frequency divider 5 frequency-divides the input frequency and outputs the frequency-divided signal to the phase comparator 2.

At this time, the output of the voltage controlled oscillator 4 is changed to f0
, Where fp is the output from the fixed frequency divider 5 and N is the frequency division number of the fixed frequency divider 5, then fp = f0 / N. If the output of the variable oscillator circuit 1 is fr,
The phase comparator 2 compares the phases of fr and fp and outputs a voltage corresponding to the phase difference to the low pass filter circuit 3. The low-pass filter circuit 3 outputs the output voltage of the phase comparator 2 from which the ripple has been removed to the voltage controlled oscillator 4 as a control voltage. In this way, the phase comparator 2, the low-pass filter circuit 3, the voltage-controlled oscillator 4, and the fixed frequency divider 5 constitute a loop of the PLL frequency synthesizer, and the phase comparator 2 always maintains fr and fp.
The phase difference is detected, the voltage-controlled oscillator 4 passes through the low-pass filter circuit 3, the output frequency is changed by the phase difference, and this is fed back again to operate so that fr = fp. Therefore, the output frequency of this PLL frequency synthesizer is kept at f0 = fr.N.

Here, the loop natural frequency ωn of the transfer function of the loop of the PLL frequency synthesizer is ωn = (KφKv / NT) ^1/2 Kφ: gain of the phase comparator Kv: gain of the voltage controlled oscillator T: low-pass filter It becomes the constant of the wave circuit, and the relationship between ωn and the frequency switching time t is ωn · t = x. Note that x is determined by the damping factor of the loop. From this, it is understood that when the frequency division frequency N of the loop is large, the frequency switching time t becomes long, and when N is small, t becomes small.

The device used for the phase comparator is C
In the case of a -MOS, this frequency characteristic makes the comparison frequency proportional to the current consumption, and the higher the comparison frequency, the more the current consumption increases.

[0007]

Since the conventional PLL frequency synthesizer with a variable reference signal is constructed as described above, if the output fr of the direct digital synthesizer is made larger than fr = fv = f0 / N, the loop is generated. N, which is the frequency division number of, becomes smaller. In the PLL frequency synthesizer, since the frequency switching time of the loop depends on the frequency division number as described above, the switching time becomes faster if fr is increased. However, at a high frequency, the phase comparator 2
There is a problem that the current consumption increases when the is operated.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a PLL frequency synthesizer that can switch frequencies at high speed and consumes less current.

[0009]

In order to achieve the above object, a PLL frequency synthesizer (phase locked loop synthesizer) according to claim 1 comprises variable oscillating means for generating a reference signal whose frequency is variable according to input data, A voltage controlled oscillator for outputting a frequency corresponding to an input voltage, a variable frequency divider for dividing the output from the voltage controlled oscillator, a reference signal from the variable oscillator, and a signal from the variable frequency divider. , A low-pass filtering means for outputting a signal from the phase comparing means to the voltage controlled oscillating means, a frequency in the variable oscillating means, and a frequency dividing ratio in the variable frequency dividing means. And switching means for simultaneously switching at a predetermined timing.

In order to achieve the above object, the PLL frequency synthesizer according to claim 2 is the phase locked loop synthesizer according to claim 1, wherein the variable oscillation means includes a reference oscillator and a direct digital synthesizer. It is characterized by being done.

In order to achieve the above object, the PLL frequency synthesizer according to claim 3 is the phase locked loop synthesizer according to claim 1, wherein the variable oscillating means includes a reference oscillator and a variable frequency divider. It is characterized by being configured.

In order to achieve the above object, the PLL frequency synthesizer according to claim 4 is the phase locked loop synthesizer according to claim 1, wherein the variable oscillating means is a reference oscillator, a direct digital synthesizer,
And a variable frequency divider.

Further, in order to achieve the above object, the PLL frequency synthesizer according to claim 5 is the phase locked loop synthesizer according to claim 1 or claim 2 or claim 3 or claim 4, Is
It is characterized in that it is configured to include a phase synchronization circuit and a phase comparator.

[0014]

In the PLL frequency synthesizer according to the first to fifth aspects, switching is performed by changing the fixed frequency divider in the loop to a variable frequency divider. The output frequency fr of the variable oscillating means is increased at the initial stage of frequency setting, and the frequency division number N
Set smaller. The time for the output frequency of the loop to reach the predetermined range of the frequency to be converged is set in advance, and when the time elapses after the frequency is set, fr is decreased and N is increased simultaneously.

At the initial stage of frequency setting, the frequency dividing number N is small, so that the switching time is short and the current consumption is large. However, after a certain time elapses, the switching time is slow but the current consumption is reduced because N is increased. The loop converges, and it can be operated with a small current consumption when using the frequency. Therefore, as a total,
The frequency switching time is shortened and the current consumption is also reduced.

In the PLL frequency synthesizer according to the fifth aspect, since the phase comparison means includes the phase synchronizing circuit, it is possible to prevent the phase shift when switching fr and the frequency division number N.

[0017]

Embodiments of the present invention will be described below with reference to the drawings.

Embodiment 1 FIG. 1 shows a reference frequency variable P in this embodiment.
A structural block diagram of an LL frequency synthesizer is shown. In the figure, 1 is a variable oscillating circuit, 2 is a phase comparator (phase comparing means) for detecting a phase difference between two frequencies, 3 is a low-pass filtering circuit, and 4 is voltage control for outputting a frequency corresponding to an input voltage. An oscillator (VCO), 7 is a variable frequency divider, and 8 is a data setting circuit (switching means) for setting frequency data of the variable oscillation circuit 1 and frequency division number data to the variable frequency divider 7.
The difference from the conventional PLL frequency synthesizer shown in FIG. 7 is that a variable frequency divider is provided instead of the fixed frequency divider, and data is set in both the variable oscillator circuit 1 and the variable frequency divider 7. A circuit (switching means) is connected to output data.

The configuration of this embodiment is as described above, and its operation will be described below. A series of operations is almost the same as the above-mentioned conventional PLL frequency synthesizer with variable reference frequency, but the frequency division number of the loop is variable. The phase comparison between the output fr of the variable oscillation circuit 1 and the output fp of the variable frequency divider 7 is performed by the phase comparator 2, and a voltage corresponding to the phase difference is output. This is output to the control voltage oscillator 4 through the low pass filter circuit 3, and the frequency corresponding to the control voltage is distributed to the output side and the feedback side. On the feedback side, the frequency is divided by the variable frequency divider 7 and output to the phase comparator 2 as fp.

Here, the data setting circuit (switching means) 8 which is a feature of this embodiment is the data for causing the variable oscillation circuit 1 to output afr, and the variable frequency divider 7 has N / F.
Data for frequency division by a is set and output. At this time, if the output frequency of the loop is f01, then f01 = afrN / a = frN Since the frequency division number is set to N / a smaller than N, it converges to a desired frequency at high speed. After that, when the time when the output frequency approaches a certain fixed range with respect to the desired frequency, for example, the time when it reaches the desired frequency ± 1 kHz, the data setting circuit 8 causes the variable oscillating circuit 1 to f.
The data for outputting r and the data for dividing by N in the variable frequency divider 7 are set, and these data are simultaneously output to the variable oscillator circuit 1 and the variable frequency divider 7. At this time,
If the frequency on the output side of the loop is f02, then f02 = fr.multidot.N (= f01).

As described above, the frequency switching time is shortened by switching at a high speed by dividing the frequency by N / a at the time of frequency switching, switching to the frequency dividing by N after a lapse of a certain time, and operating at the frequency dividing by N until the next frequency switching. The consumption current is large only while the current consumption is converged, and thereafter, the consumption current can be reduced to operate.

Embodiment 2 In Embodiment 1 described above, the phase comparator is used as the phase comparison means, but the phase comparison means may be composed of the phase synchronization circuit 9 and the phase comparator 2 as shown in FIG. FIG. 3 shows a block diagram of the configuration of the PLL frequency synthesizer in the case where the phase comparison means is thus constituted by the phase synchronization circuit 9 and the phase comparator 2. The reference frequency from the variable oscillator circuit 1 and the frequency-divided signal from the variable frequency divider 7 are both output to the phase synchronization circuit 9. In the first embodiment described above, there is a possibility that the phases of fr and fp may be out of phase when data is switched by the data setting circuit 8, and it takes some time to correct the deviation, but in the present embodiment, the phase synchronization circuit 9 is used. It is provided to prevent out of phase.

By thus preventing the phase shift when switching the reference frequency and the frequency division number, the frequency switching operation can be performed at a higher speed than in the case of the first embodiment.

Third Embodiment Further, in the above-described first or second embodiment, the variable oscillating means can be constituted by the reference oscillator 10 and the direct digital synthesizer 11 driven by it, as shown in FIG. In this case, the data from the data setting circuit 8 is the direct digital synthesizer 1
1 and changes the output frequency. Also in this embodiment, it is possible to increase the speed and reduce the current consumption.

Fourth Embodiment Further, in the above-described first or second embodiment, the variable oscillating means may be composed of the reference oscillator 10 and the variable frequency divider 12, as shown in FIG. In this case, the data from the data setting circuit 8 is output to the variable frequency divider 12, and the output frequency is changed by switching the frequency division number. Also in this embodiment, it is possible to increase the speed and reduce the current consumption.

Fifth Embodiment Further, in the first or second embodiment described above, as shown in FIG. 6, the variable oscillating means can be constituted by a reference oscillator 10, a direct digital synthesizer 11, and a variable frequency divider 12. . In this case, channel switching is performed by switching the output of the direct digital synthesizer 11, and the variable frequency divider 12 is used when switching the frequency division number of the loop.
The output frequency from the variable frequency divider 12 is changed by switching the frequency division number. Also in this embodiment, it is possible to increase the speed and reduce the current consumption.

[0027]

As described above, according to the PLL frequency synthesizer of claims 1 to 5, the PLL
By switching the reference frequency and the frequency division number of the loop when switching the frequency of the frequency synthesizer, there is an effect that the frequency can be switched at high speed with low current consumption.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of a PLL frequency synthesizer with a variable reference frequency according to a first embodiment of the present invention.

FIG. 2 is a configuration block diagram of a phase comparison unit according to a second embodiment of the present invention.

FIG. 3 is a configuration block diagram of a PLL frequency synthesizer with a variable reference frequency according to a second embodiment of the present invention.

FIG. 4 is a structural block diagram of a variable oscillator according to a third embodiment of the present invention.

FIG. 5 is a configuration block diagram of a variable oscillator according to a fourth embodiment of the present invention.

FIG. 6 is a configuration block diagram of a variable oscillator according to a fifth embodiment of the present invention.

FIG. 7 is a configuration block diagram of a conventional PLL frequency synthesizer with a variable reference frequency.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 variable oscillation circuit, 2 phase comparator, 3 low-pass filtering circuit, 4 voltage controlled oscillator, 5 fixed frequency divider, 6 data setting circuit, 7 variable frequency divider, 8 data setting circuit (switching means), 9 Phase lock circuit, 10 Reference oscillator, 11
Direct digital synthesizer, 12 variable frequency divider.

Claims (5)

[Claims] 1. A variable oscillating means for generating a reference signal having a variable frequency according to input data, a voltage controlled oscillating means for outputting a frequency corresponding to an input voltage, and a variable frequency dividing means for dividing an output from the voltage controlled oscillating means. Frequency dividing means, phase comparing means for phase comparing the reference signal from the variable oscillating means and the signal from the variable dividing means, and a low-pass filter for outputting the signal from the phase comparing means to the voltage controlled oscillating means. A phase locked loop synthesizer, comprising: wave means; and switching means for simultaneously switching the frequency of the variable oscillating means and the frequency division ratio of the variable frequency dividing means at a predetermined timing. 2. The phase-locked loop synthesizer according to claim 1, wherein the variable oscillation means includes a reference oscillator and a direct digital synthesizer. 3. The phase-locked loop synthesizer according to claim 1, wherein the variable oscillation means includes a reference oscillator and a variable frequency divider. 4. The phase-locked loop synthesizer according to claim 1, wherein the variable oscillation means includes a reference oscillator, a direct digital synthesizer, and a variable frequency divider. 5. Claim 1 or claim 2 or claim 3.
The phase-locked loop synthesizer according to claim 4, wherein the phase comparison means includes a phase-locked circuit and a phase comparator.