CN100353673C - Lock phare cycle frequency synthesizer - Google Patents
Lock phare cycle frequency synthesizer Download PDFInfo
- Publication number
- CN100353673C CN100353673C CNB021305315A CN02130531A CN100353673C CN 100353673 C CN100353673 C CN 100353673C CN B021305315 A CNB021305315 A CN B021305315A CN 02130531 A CN02130531 A CN 02130531A CN 100353673 C CN100353673 C CN 100353673C
- Authority
- CN
- China
- Prior art keywords
- frequency
- signal
- phase
- frequency divider
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The present invention relates to a frequency synthesizer of a phase-locking loop, which comprises a reference signal generator, a voltage-control oscillator, a first and a second frequency dividers with variable divisors, a first and a second controllable synchronous frequency dividers, a phase frequency comparator, a loop filter, a phase locking detector and a switching control logical circuit, wherein the reference signal generator is used for generating a signal of reference frequency; the voltage-control oscillator generates oscillating frequency according to control voltage. The first frequency divider with variable divisors is used for carrying out frequency dividing to the signal of the reference frequency and for the output of the signal of the reference frequency, and the second frequency divider with variable divisors divides the oscillation frequency; the output of the first frequency divider with the variable divisors is divided synchronously by the first controllable synchronous frequency divider, and the output of the second frequency divider with the variable divisors is divided synchronously by the second controllable synchronous frequency divider; the phase difference between output pulses from the first controllable synchronous frequency divider and the second controllable synchronous frequency divider is detected by the phase frequency comparator, and the phase frequency comparator exports an output regulation signal which is received by a charge pumping circuit. Control voltage is exported by the loop filter which acts synchronously with the charge pumping circuit, the phase locking detector which is connected with the phase frequency comparator exports phase locking signals, and the switching control logical circuit exports a signal for regulating the charge pumping circuit and the loop filter.
Description
Technical field
The present invention relates to phase-locked loop frequency synthesizer, particularly the phase-locked loop frequency synthesizer of quick frequency locking.
Background technology
" can change the phase-locked loop frequency synthesizer (PLL Frequency Synthesizer Capable of Changing an Output Frequency at aHigh Speed) of the output frequency fast " patent that Figure 1 shows that the U.S. the 5th, 173, No. 665.As shown in the drawing, this phase-locked loop frequency synthesizer has that reference signal generator 121, first pulse remove circuit 131, second pulse removes circuit 132, phase frequency comparator 124, charge pump circuit 125, loop filter 126, voltage controlled oscillator 122 and variable divisor number frequency divider 123.This phase-locked loop frequency synthesizer reaches the quick frequency locking purpose that changes output frequency in the mode of higher-frequency, and after frequency locking, utilize two pulses remove circuit 131,132 respectively with pulse reference clock with output clock pulse partial pulse remove, to meet output frequency.
Fig. 2 shows that the pulse of the 5th, 173, No. 665 patents of the above-mentioned U.S. removes the structure of circuit 131,132.This pulse removes circuit and comprises an inverter 311, a frequency-dividing counter 312 and one and door (ANDGATE) 313.As shown in Figure 2, whether this pulse removes circuit 131,132 and utilizes the mode of switching divisor A1 (A2) to come control impuls to remove, and the umber of pulse that removes.But as Fig. 1 and shown in Figure 2, first pulse removes circuit 31 and second pulse and removes and do not use same control signal control between the circuit 32, therefore can't make two pulses remove circuit and reach synchronous; Simultaneously, when changing divisor, and can't obtain best change opportunity, therefore have the discontinuous problem of phase signal.
Summary of the invention
Because the problems referred to above, the objective of the invention is to propose a kind of phase-locked loop (Phase-Locked-Loop, PLL) frequency synthesizer, and the synchronization frequency division control signal of utilizing switch control logic to export is controlled the action of controlled synchronous frequency divider of quick frequency locking.
For reaching above-mentioned purpose, phase-locked loop frequency synthesizer of the present invention comprises a reference signal generator, produces the signal of reference frequency; One voltage-controlled oscillator produces the output frequency of oscillation according to a control voltage; One first variable divisor number frequency divider according to an input variable divisor number value, carries out frequency division and exports the signal of gained the signal of reference frequency; One second variable divisor number frequency divider according to an input variable divisor number value, carries out frequency division and exports the signal of gained frequency of oscillation; One first controlled synchronous frequency divider according to input variable divisor number value and a synchronous division control signal, carries out synchronization frequency division or frequency division and export the signal of gained not to the output of first variable frequency divider; One second controlled synchronous frequency divider according to input variable divisor number value and a synchronous division control signal, carries out synchronization frequency division or frequency division and export the signal of gained not to the output of the second variable divisor number device; One phase frequency comparator receives the output pulse of the first controlled synchronous frequency divider and the second controlled synchronous frequency divider, detects the phase difference between them and exports an adjustment signal; One charge pump circuit receives from the adjustment signal of described phase frequency comparator output; One loop filter with the charge pump circuit synchronization action, and is exported described control voltage; One lock detector is connected in phase frequency comparator, and the output lockin signal; And one switch control logic, receives the output frequency of the first variable divisor number frequency divider and the lockin signal of lock detector, and producing the synchronization frequency division control signal, and exportable signal is with adjustment charge pump circuit and loop filter.
Above-mentioned phase-locked loop frequency synthesizer of the present invention, wherein controlled synchronous frequency divider comprises: one first inverter, the clock pulse of reception incoming frequency; One first d type flip flop triggers clock pulse signal with the output of first inverter as positive edge, and with the synchronization frequency division control signal as this d type flip flop input end signal; One controllable frequency divider is put signal with the Q output signal of first d type flip flop as heavy duty, and the output signal of first inverter is exported after divided by M; One NAND gate receives the Q output signal and the synchronization frequency division control signal of first d type flip flop; One second inverter, the output signal of reception controllable frequency divider; One second d type flip flop, with the output of second inverter as triggering clock pulse signal, and with the output signal of NAND gate as this d type flip flop input end signal; One or door, receive the output signal of controllable frequency divider and the Q output signal of second d type flip flop; And one and door, receiving or the output signal and the clock pulse of incoming frequency of door, this output signal with door be the output signal of this controlled synchronous frequency divider.
According to phase-locked loop frequency synthesizer of the present invention, because controlled synchronous frequency divider is subjected to the Synchronization Control of synchronization frequency division control signal, so when carrying out the mode switch of frequency division and frequency division not, can not influence the signal of frequency locking.
Description of drawings
Fig. 1 is the calcspar of the phase-locked loop frequency synthesizer of prior art.
Fig. 2 removes the circuit diagram of circuit for the pulse of Fig. 1.
Fig. 3 is the calcspar of phase-locked loop frequency synthesizer of the present invention.
Fig. 4 is the circuit diagram of the controlled synchronous frequency divider of Fig. 3.
Fig. 5 is the sequential chart of the controlled synchronous frequency divider of Fig. 4.
Each description of reference numerals in the accompanying drawing is as follows:
10 phase-locked loop frequency synthesizers, 12 reference signal generators
14 phase frequency comparator, 16 charge pump circuits
18 loop filters, 20 voltage-controlled oscillators
22,24 variable divisor number frequency dividers, 26,28 controlled synchronous frequency dividers
30 lock detectors, 32 switch control logics
Embodiment
Below with reference to description of drawings phase-locked loop frequency synthesizer of the present invention.Because phase frequency comparator is very fast for the reaction of high-frequency signal, therefore can faster reach the purpose of frequency locking, but but be easy to generate labile state, cause the phase noise of frequency locking signal of voltage-controlled oscillator relatively poor.Comparatively speaking, phase frequency comparator is slower for the reaction of low frequency signal, but more stable, can make the phase noise of frequency locking signal of voltage-controlled oscillator better.Therefore, utilize this characteristic, phase-locked loop frequency synthesizer of the present invention utilized for two stages controlled to carry out frequency locking control.That is, can be when not reaching phase locked state, the output high-frequency signal is to phase frequency comparator.And when phase-locked loop frequency synthesizer during near phase locked state, then the output low frequency signal is to phase frequency comparator, promptly utilizes the frequency divider of second stage to carry out the action of synchronization frequency division, obtains the result of best frequency locking.Also can when phase locked state, switch controlled synchronous frequency divider arbitrarily, carry out frequency division and frequency division not, and still keep the continuous characteristic of phase place.
Figure 3 shows that the control calcspar of phase-locked loop frequency synthesizer of the present invention.As shown in the drawing, the basic structure of phase-locked loop frequency synthesizer 10 of the present invention is identical with the phase-locked loop of prior art, all comprises reference signal generator 12, phase frequency comparator 14, charge pump circuit 16, loop filter 18, voltage-controlled oscillator 20, the first variable divisor number frequency divider 22 and the second variable divisor number frequency divider 24.In addition, the present invention also comprises controlled synchronous frequency divider 26 and 28 and the lock detector 30 and switch control logic 32 of controlling the action moment of this frequency divider 26 and 28.The also exportable signal of this switch control logic 32 is to adjust the action of charge pump circuit 16 and loop filter 18.
Reference signal generator 12 produces the signal of the reference frequency of a standard.The signal of this reference frequency via the first variable divisor number frequency divider 22 divided by after the R, the controlled synchronous frequency divider 26 of the signal to the first of output low frequency reference frequency.In addition, the output frequency that voltage-controlled oscillator 20 is produced via the second variable divisor number frequency divider 24 divided by after the N, the controlled synchronous frequency divider 28 of output low frequency output frequency to the second.Phase frequency comparator 14 more controlled synchronous frequency dividers 26 and 28 output frequency, and produce and adjust signal.Charge pump circuit 16 promptly produces the frequency of oscillation that control voltage is controlled voltage-controlled oscillator 20 according to adjusting signal with loop filter 18.Therefore, voltage-controlled oscillator 20 is the clock pulse signal of exportable required frequency.
Figure 4 shows that the controlled synchronous frequency divider 26 of Fig. 3 and 28 calcspar, and Figure 5 shows that the sequential chart of this controlled synchronous frequency divider.So-called controlled synchronous frequency divider is through acknowledge(ment) signal control, and switches on the frequency division and the pattern of frequency division not synchronously.Because controlled synchronous frequency divider 26 is identical with 28 function and structure, so the structure of controlled synchronous frequency divider 26 is only described.As shown in Figure 4, controlled synchronous frequency divider 26 comprises two inverters 261 and 262, one controllable frequency divider 263, two d type flip flops 264 and 265, a NAND gate 266, one or door 267 and one and 268.
Controlled synchronous frequency divider 26 and 28 controllable frequency divider 263 do not need to remove the transformation of variables action, are M and keep divisor always.Controlled synchronous frequency divider 26 and 28 mainly is to put action with the heavy duty that first d type flip flop 264 is controlled controllable frequency divider 263, that is after the output of synchronization frequency division control signal, with respect to the clock pulse of the output frequency of variable divisor number frequency divider 22 and 24, when the negative edge input signal of the next one, controllable frequency divider 263 is carried out heavy duty and put.Simultaneously, controlled synchronous frequency divider 26 and 28 is controlled the time that synchronization frequency division finishes with second d type flip flop 265, that is after the synchronization frequency division control signal finishes to export, and switches to not division function at the negative edge signal of next controllable frequency divider 263.
Then, action sequence with reference to the controlled synchronous frequency divider of figure 5 explanations, wherein (a) is that the clock pulse, (b) of incoming frequency is the synchronization frequency division control signal, the Q output signal, (e) that with reference to the output frequency of the first variable divisor number frequency divider 22, output signal, (d) that (c) is first inverter 261 is first d type flip flop 264 for the output signal of controllable frequency divider 263, (f) be second d type flip flop 265 Q output signal, (g) for or 267 output signal and (h) be the clock pulse of the output frequency of the first controlled synchronous frequency divider 26.At first, suppose that controllable frequency divider 263 is to remove 3 frequency divider, that is M is 3.In the digital circuitry, represent low voltage signal and represent high voltage signal with H with L.
When the synchronization frequency division control signal was exported, when promptly becoming H by L, the Q output signal of first d type flip flop 264 became H in the t1 time by L.At this moment, controllable frequency divider 263 be subjected to first d type flip flop 264 the Q output signal triggering and become H.Then, in the t2 time, the output of controllable frequency divider 263 becomes L, and simultaneously, the Q output of second d type flip flop 265 also becomes L by H.At this moment, the first controlled synchronous frequency divider 26 promptly enters the frequency division pattern.And when synchronization frequency division control signal end of output, when promptly becoming L by H, the Q output signal of first d type flip flop 264 becomes L in the t3 time by H.In this case, second d type flip flop 265 is by the time during t4, that is the output signal of controllable frequency divider 263 just can become H by L with output when becoming L by H.At this moment, the first controlled synchronous frequency divider 26 promptly enters not frequency division pattern.Therefore, as shown in Figure 5, the time of t2-t4 is the frequency division pattern, and the output frequency of the first controlled synchronous frequency divider 26 between at this moment can be reduced to 1/3rd (M=3) of incoming frequency.
Because controlled synchronous frequency divider 26 and 28 can be subjected to the control of synchronization frequency division control signal and switch to the frequency division pattern simultaneously, and can when becoming L by H, the output signal of controllable frequency divider 263 just can switch not frequency division pattern simultaneously, therefore the state of frequency locking can not be affected because of switch mode, and the phase signal that can be maintained is continuous effect synchronously.
Then, the divisor N value of the second variable divisor number frequency divider 24 of the present invention can be integer, also can be mark, i.e. fractional divider.When the N value is mark (NI+NF/F; NI is an integer part; NF is a molecule; F is a denominator) time, the inverse of the denominator F value of this fractional divider must be an integer with the product (M/F) of the M value of controlled synchronous frequency divider, so, the fractional divider that this N value is a mark is when controlled synchronous frequency divider 26 and 28 synchronization frequency divisions, do not need offset current, because according to the principle of fractional divider, in the cycle, not exporting the comparison phase signal because of synchronization frequency division does not need offset current at fraction division multiple (M/F).So, when locked phase place,, still can keep identical pinning phase place through all after dates of fraction division multiple (M/F).
Though more than with embodiment the present invention has been described, therefore do not limit scope of the present invention, only otherwise break away from main idea of the present invention, those skilled in the art can carry out various distortion or change.
Claims (9)
1. phase-locked loop frequency synthesizer comprises:
One reference signal generator produces the signal of a reference frequency;
One voltage-controlled oscillator produces an output frequency of oscillation according to a control voltage;
One first controlled synchronous frequency divider according to a synchronous division control signal, carries out synchronization frequency division or frequency division and export the signal of gained not to the signal of described reference frequency;
One second controlled synchronous frequency divider according to described synchronization frequency division control signal, carries out synchronization frequency division or frequency division and export the signal of gained not to described frequency of oscillation;
One phase frequency comparator receives the output signal of the described first controlled synchronous frequency divider and the second controlled synchronous frequency divider, detects the phase difference between them and exports one and adjust signal;
One charge pump circuit receives from the described adjustment signal of described phase frequency comparator output;
One loop filter, with described charge pump circuit synchronization action, and the described control voltage of the described voltage-controlled oscillator of output control;
One lock detector is connected in described phase frequency comparator, and the output lockin signal; And
One switches control logic, and according to the signal of described reference frequency and the described lockin signal of described lock detector, producing described synchronization frequency division control signal, and output signal is adjusted described charge pump circuit and described loop filter.
2. phase-locked loop frequency synthesizer according to claim 1 also comprises the first variable divisor number frequency divider, according to the first variable divisor number value of an input, described reference frequency is carried out exporting the described first controlled synchronous frequency divider to behind the frequency division.
3. phase-locked loop frequency synthesizer according to claim 2 also comprises the second variable divisor number frequency divider, according to the second variable divisor number value of an input, described frequency of oscillation is carried out exporting the described second controlled synchronous frequency divider to behind the frequency division.
4. phase-locked loop frequency synthesizer according to claim 3, wherein, described controlled synchronous frequency divider comprises:
One first inverter, the clock pulse of reception incoming frequency;
One first d type flip flop triggers clock pulse signal with the output of described first inverter as positive edge, and with described synchronization frequency division control signal as this d type flip flop input end signal;
One controllable frequency divider is put signal with the Q output signal of described first d type flip flop as heavy duty, and the output signal of described first inverter is exported after divided by M;
One NAND gate receives the Q output signal and the described synchronization frequency division control signal of described first d type flip flop;
One second inverter receives the output signal of described controllable frequency divider;
One second d type flip flop, with the output of described second inverter as triggering clock pulse signal, and with the output signal of described NAND gate as this d type flip flop input end signal;
One or the door, receive the output signal of described controllable frequency divider and the Q output signal of described second d type flip flop; And
One with door, receives described or the output signal of door and the clock pulse of described incoming frequency, this be the output signal of described controlled synchronous frequency divider with output signal of door.
5. phase-locked loop frequency synthesizer according to claim 4, wherein, the divisor R of the described first variable divisor number frequency divider is an integer.
6. phase-locked loop frequency synthesizer according to claim 4, wherein, the divisor N of the described second variable divisor number frequency divider is an integer.
7. phase-locked loop frequency synthesizer according to claim 4, wherein, the divisor M of described controlled synchronous frequency divider is an integer.
8. phase-locked loop frequency synthesizer according to claim 7, wherein, the described second variable divisor number frequency divider is a fractional divider, that is divisor N is mark, and the product (M/F) of the M value of the inverse of the denominator F value of this mark and described controlled synchronous frequency divider is an integer.
9. phase-locked loop frequency synthesizer according to claim 8, wherein, described frequency synthesizer does not need offset current when described controlled synchronous frequency divider synchronization frequency division.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021305315A CN100353673C (en) | 2002-08-14 | 2002-08-14 | Lock phare cycle frequency synthesizer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021305315A CN100353673C (en) | 2002-08-14 | 2002-08-14 | Lock phare cycle frequency synthesizer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1476171A CN1476171A (en) | 2004-02-18 |
| CN100353673C true CN100353673C (en) | 2007-12-05 |
Family
ID=34144504
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021305315A Expired - Fee Related CN100353673C (en) | 2002-08-14 | 2002-08-14 | Lock phare cycle frequency synthesizer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100353673C (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100444641C (en) * | 2005-11-11 | 2008-12-17 | 北京中星微电子有限公司 | System for clock recovery of multi media system |
| CN101098141B (en) * | 2006-06-29 | 2012-05-30 | 日本电波工业株式会社 | Frequency synthesizer |
| JP6439915B2 (en) * | 2014-09-12 | 2018-12-19 | セイコーエプソン株式会社 | Fractional N-PLL circuit, oscillator, electronic device, and moving object |
| US11088697B2 (en) * | 2017-07-04 | 2021-08-10 | Mitsubishi Electric Corporation | PLL circuit |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5173665A (en) * | 1990-10-22 | 1992-12-22 | Nec Corporation | Pll frequency synthesizer capable of changing an output frequency at a high speed |
| CN1291376A (en) * | 1998-10-22 | 2001-04-11 | 皇家菲利浦电子有限公司 | Frequency synthesizer |
| JP2001127630A (en) * | 1999-10-26 | 2001-05-11 | Sharp Corp | Pll frequency synthesizer circuit |
| US6359950B2 (en) * | 1998-09-03 | 2002-03-19 | Infineon Technologies. | Digital PLL (phase-locked loop) frequency synthesizer |
-
2002
- 2002-08-14 CN CNB021305315A patent/CN100353673C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5173665A (en) * | 1990-10-22 | 1992-12-22 | Nec Corporation | Pll frequency synthesizer capable of changing an output frequency at a high speed |
| US6359950B2 (en) * | 1998-09-03 | 2002-03-19 | Infineon Technologies. | Digital PLL (phase-locked loop) frequency synthesizer |
| CN1291376A (en) * | 1998-10-22 | 2001-04-11 | 皇家菲利浦电子有限公司 | Frequency synthesizer |
| JP2001127630A (en) * | 1999-10-26 | 2001-05-11 | Sharp Corp | Pll frequency synthesizer circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1476171A (en) | 2004-02-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6147561A (en) | Phase/frequency detector with time-delayed inputs in a charge pump based phase locked loop and a method for enhancing the phase locked loop gain | |
| US20100214031A1 (en) | Spectrum spread clock generation device | |
| US7323942B2 (en) | Dual loop PLL, and multiplication clock generator using dual loop PLL | |
| US20060145772A1 (en) | Precision frequency and phase synthesis with fewer voltage-controlled oscillator stages | |
| EP1246369B1 (en) | Mode switching method for PLL circuit and mode control circuit for PLL circuit | |
| WO2007080918A1 (en) | Phase comparison circuit and pll synthesizer using the same | |
| JP2817676B2 (en) | PLL frequency synthesizer | |
| CN209627350U (en) | Electronic circuit | |
| JPH09321617A (en) | Pll frequency synthesizer | |
| CN111294043B (en) | System for automatically recovering external clock based on PLL | |
| CN100353673C (en) | Lock phare cycle frequency synthesizer | |
| JP2007142791A (en) | Frequency synthesizer | |
| KR100256838B1 (en) | Pll circuit and noise reduction method for pll circuit | |
| US6359948B1 (en) | Phase-locked loop circuit with reduced jitter | |
| US6285260B1 (en) | Phase-locked loop having circuit for synchronizing starting points of two counters | |
| US20030042948A1 (en) | PLL circuit | |
| US11923860B2 (en) | PLL circuit | |
| JP3883812B2 (en) | PLL circuit | |
| JPH10126263A (en) | Frequency synthesizer | |
| JP2018113501A (en) | Voltage control oscillation circuit and control method of the same | |
| US7609117B2 (en) | Phase-locked loop circuit with current-pulse injection for improving linearity | |
| JP3798253B2 (en) | Phase synchronization circuit | |
| JPH11163722A (en) | Pll frequency synthesizer | |
| JP3869661B2 (en) | PLL circuit | |
| JP3596172B2 (en) | PLL frequency synthesizer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20071205 Termination date: 20190814 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |