JP2018113501A - Voltage control oscillation circuit and control method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a voltage control oscillation circuit with small phase noise.SOLUTION: A voltage control oscillation circuit includes: a voltage control generator (110) that outputs a clock signal of a frequency controlled by a control voltage; a frequency divider (120) that outputs a frequency-divided signal by frequency-dividing the clock signal; a first delay unit (125) that synchronizes with the clock signal, and outputs a first delay clock signal in which the frequency-divided signal is delayed; a variable delay unit (130) that outputs a second delay clock signal in which the frequency-divided signal is delayed by a delay amount in accordance with a frequency control signal; a phase comparator (140) that compares a phase of a first delay clock signal and a second delay clock signal; a charge pump (150) that flows a current to a first node or extracts the current from the first node in accordance with a comparison result of the phase comparator; and a low-pass filter (160) that smooths a voltage of the first node, and feed-backs a control voltage to a voltage control generator.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a voltage controlled oscillation circuit and a method for controlling the voltage controlled oscillation circuit.

  In high-speed serial communication technology, a high-quality clock signal with low phase noise is required. In order to generate a high-quality clock signal, means for suppressing noise of a voltage controlled oscillator (VCO) using a phase locked loop circuit is known. The suppression of the VCO noise depends on the loop band of the phase-locked loop, and the noise of the higher frequency VCO can be suppressed by widening the loop band. In general, the frequency of the reference clock signal input to the phase locked loop circuit is the sampling frequency of the phase lock loop (PLL) circuit. Therefore, in order to widen the loop band, it is desirable to increase the frequency of the reference clock signal, but it is difficult to realize it with an inexpensive crystal oscillator.

  As described above, since there is a limit to suppressing the VCO noise by the phase synchronization circuit, means for reducing the VCO noise itself is taken in order to generate a clock signal with a small phase noise. Although the means for reducing the noise generated by the elements in the VCO by flowing more current through the VCO and reducing the noise of the VCO is effective, there is a problem that the power consumption increases. On the other hand, means for reducing the VCO noise by devising the circuit architecture is effective. For example, in the voltage controlled oscillation circuit described in Patent Document 1, phase noise can be reduced by a feedback loop using a delay device.

JP-A-8-195676

  However, the voltage controlled oscillation circuit described in Patent Document 1 has a problem that phase noise caused by delay noise is not suppressed.

  An object of the present invention is to provide a voltage-controlled oscillation circuit with low phase noise and a method for controlling the voltage-controlled oscillation circuit.

  The voltage controlled oscillation circuit of the present invention includes a voltage controlled oscillator that outputs a clock signal having a frequency controlled by a control voltage, a frequency divider that outputs a divided clock signal obtained by dividing the clock signal, Synchronously, a first delay unit that outputs a first delayed clock signal obtained by delaying the divided clock signal, and a second delay unit that delays the divided clock signal by a delay amount corresponding to a frequency control signal. A variable delay device that outputs a delayed clock signal, a phase comparator that compares the phases of the first delayed clock signal and the second delayed clock signal, and a first comparator according to a comparison result of the phase comparator. A charge pump that draws current into or pulls out current from the first node, and smoothes the voltage at the first node, and uses the smoothed voltage as the control voltage to control the voltage. And a low-pass filter for feedback to the oscillator.

  According to the present invention, it is possible to provide a voltage controlled oscillation circuit with small phase noise.

It is a figure which shows the structural example of the voltage controlled oscillation circuit by 1st Embodiment. It is a figure which shows the structural example of VCO by 1st Embodiment. It is a figure which shows the structural example of the variable delay device by 1st Embodiment. It is a figure which shows the structural example of a charge pump and a low-pass filter. 3 is a timing chart of the voltage controlled oscillation circuit according to the first embodiment.

  FIG. 1 is a diagram illustrating a configuration example of a voltage controlled oscillation circuit 100 according to an embodiment of the present invention. The voltage controlled oscillator circuit 100 includes a voltage controlled oscillator (VCO) 110, a frequency divider 120, a variable delay device 130, a first delay device 125, a phase comparator 140, a charge pump 150, and a low pass filter 160. And have. The VCO 110 is a part of the control loop of the voltage controlled oscillation circuit 100. The delay amount of the variable delay device 130 is controlled by a frequency control signal input to the frequency control signal input terminal 102. By controlling the frequency control signal input to the frequency control signal input terminal 102, the oscillation frequency of the VCO 110 can be controlled. The clock signal output terminal 101 outputs the clock signal 111 output from the VCO 110 to the outside. The frequency control signal input terminal 102 inputs a frequency control signal from the outside. The VCO 110 outputs a clock signal 111 having a frequency controlled by the control voltage 161 output from the low-pass filter 160. The clock signal 111 is output from the clock signal output terminal 101 as an output of the voltage controlled oscillation circuit 100.

  FIG. 2 is a circuit diagram showing a configuration example of the VCO 110 of FIG. The VCO 110 includes inverters 201 to 203 and a variable current source 204. The inverters 201, 202, and 203 are ring oscillators connected in a ring shape, and output a clock signal 111. The variable current source 204 is connected between the power supply voltage node and the power supply terminals of the inverters 201 to 203, and changes the current supplied to the inverters 201 to 203 in accordance with the output voltage 161 of the low pass filter 160. That is, the variable current source 204 adjusts the delay time per stage of the inverters 201 to 203 by changing the driving capability of the inverters 201 to 203, and changes the oscillation frequency of the clock signal 111. The configuration of the VCO 110 is not limited to that shown in the figure, and may be a ring oscillator that performs delay control by changing the load of the inverters 201 to 203, a ring oscillator having a differential configuration, an LC tank system, or other configurations.

  In FIG. 1, a frequency divider 120 receives a clock signal 111 and outputs a divided clock signal 121 obtained by dividing the clock signal 111 by four. The frequency dividing ratio of the frequency divider 120 is 4. When the frequency dividing ratio of the frequency divider 120 is larger, the design of the variable delay device 130 is facilitated from the viewpoint of avoiding the loss of a clock signal described later. However, if the frequency division ratio of the frequency divider 120 is too large, the band of phase noise that can be suppressed by the control loop of the voltage controlled oscillation circuit 100 is narrowed. It is desirable.

  The first delay unit 125 receives the divided clock signal 121 and outputs a first delayed clock signal 126 obtained by delaying the divided clock signal 121 by one cycle of the clock signal 111. Note that the number of cycles delayed by the first delay unit 125 is not limited to 1, but considering the avoidance of a clock signal loss described later, a smaller one is desirable in design. The first delay unit 125 may output a first clock signal 126 obtained by delaying the divided clock signal 121 by one cycle or a plurality of cycles of the clock signal 111 in synchronization with the clock signal 111. The number of cycles of the clock signal 111 delayed by the first delay unit 125 is less than the frequency division ratio (for example, 4) of the frequency divider 120. The variable delay device 130 outputs a second delayed clock signal 131 obtained by delaying the divided clock signal 121 by a delay amount corresponding to the frequency control signal from the frequency control signal input terminal 102.

  FIG. 3 is a circuit diagram showing a configuration example of the variable delay device 130 of FIG. The variable delay device 130 includes resistors 301 and 302, MOS varactors 303 and 304, and buffers 305, 306, and 307. The MOS varactors 303 and 304 are capacitors. The resistor 301 and the MOS varactor 303 constitute an RC delay unit of the first stage RC filter. The resistor 302 and the MOS varactor 304 constitute an RC delay device of the second stage RC filter. In the variable delay device 130, resistors 301 and 302 and RC delay devices of MOS varactors 303 and 304 are connected in a plurality of stages. In general, the resistors 301 and 302 which are passive elements do not have 1 / f noise as compared with the active elements, and therefore the noise is small. The buffer 305 is provided before the RC delay device of the resistor 301 and the MOS varactor 303. The buffer 306 is provided after the RC delay unit of the resistor 301 and the MOS varactor 303. The buffer 307 is provided after the RC delay device of the resistor 302 and the MOS varactor 304. The number of buffers 305 to 307 is not limited to three. The variable delay device 130 includes buffers 305 to 307 provided either before or after the RC delay device or both before and after the RC delay device. The buffer 305 receives the divided clock signal 121 and the buffer 307 outputs the second delayed clock signal 131. The buffers 305 to 307 perform waveform shaping on the clock signal. The frequency control voltage signal from the frequency control signal input terminal 102 controls the delay amount of the variable delay device 130 by changing the capacitance values of the MOS varactors 303 and 304. The variable delay device 130 delays the divided clock signal 121 by charging and discharging the RC filters of the resistors 301 and 302 and the MOS varactors 303 and 304. Therefore, the pulse width of the frequency-divided clock signal 121 input to the variable delay device 130 needs to ensure a sufficient time for charging / discharging to be sufficiently completed. When the pulse width of the divided clock signal 121 is short, a sufficient pulse amplitude cannot be secured due to the low pass filter (LPF) effect by the RC filter, and the delayed clock signal waveform cannot drive the buffers 306 and 307. . As a result, the clock signal waveform disappears.

  In the present embodiment, the variable delay device 130 receives the waveform of the divided clock signal 121 divided by four by the frequency divider 120 in order to ensure a sufficient charge / discharge time. Note that the loss of the clock signal waveform can be avoided by connecting the delay devices with short delay times in multiple stages without using the frequency divider 120, but the noise generated by the buffer itself is increased by increasing the number of buffer stages. Is added. As a result, the phase noise of the variable delay device 130 becomes large, so it is preferable to use the frequency divider 120.

  In addition, although the structure which changes the capacitance value of MOS varactor 303,304 was shown as a means to change the delay amount of the variable delay device 130, the structure which changes the resistance value of resistance 301,302 may be used, and they were combined. It may be configured. One or both of the resistance values of the RC delay resistors 301 and 302 and the capacitance values of the MOS varactors 303 and 304 are controlled by the frequency control signal at the frequency control signal input terminal 102.

  Although all of the above-described multiple stages of RC delay devices have been described in the case where the delay amount is controlled by the frequency control signal of the frequency control signal input terminal 102, the present invention is not limited to this. The delay amount of some of the RC delay units of the plurality of stages is shorter than the period of the clock signal 111, and the delay amount of the remaining RC delay units of the plurality of stages of RC delay units is the frequency control signal. It may be controlled by a frequency control signal at the input terminal 102.

  In FIG. 1, a phase comparator 140 receives a first delayed clock signal 126 and a second delayed clock signal 131, compares the phases of the first delayed clock signal 126 and the second delayed clock signal 131, and As a result of the comparison, an up signal UP or a down signal DN is output. As shown in FIG. 5A, the phase comparator 140, when the phase of the second delayed clock signal 131 is ahead of the phase of the first delayed clock signal 126, is a high-level pulse up signal UP. Is output to the charge pump 150. Further, as shown in FIG. 5B, the phase comparator 140 reduces the high-level pulse when the phase of the second delayed clock signal 131 is delayed from the phase of the first delayed clock signal 126. The signal DN is output to the charge pump 150.

  FIG. 4 is a circuit diagram showing a configuration example of the charge pump 150 and the low-pass filter 160 of FIG. The charge pump 150 includes current sources 401 and 404 and switches 402 and 403. The current source 401 and the switch 402 are connected in series between the power supply voltage node and the second node 408. The switch 403 and the current source 404 are connected in series between the second node 408 and the ground potential node. When the up signal UP of the phase comparator 140 is at a high level, the switch 402 is turned on, and the current source 401 feeds the source current to the first node 407 of the low-pass filter 160. Further, when the down signal DN of the phase comparator 140 is at a high level, the switch 403 is turned on, and the current source 404 extracts the sink current from the first node 407 of the low-pass filter 160.

  The low-pass filter 160 includes an RC filter having a resistor 405 and a capacitor 406, smoothes the voltage of the first node 407, and feeds back the smoothed voltage to the VCO 110 as a control voltage 161. The resistor 405 is connected between the first node 407 and the second node 408. The capacitor 406 is connected between the first node 407 and the ground potential node. The low-pass filter 160 integrates the source current and sink current of the charge pump 150 and converts them into a voltage value, and outputs the voltage 161 at the first node 407 to the VCO 110. The configuration of the low pass filter 160 is not limited to the configuration of FIG.

  5A and 5B are timing charts showing a control method of the voltage controlled oscillation circuit 100 of FIG. FIG. 5A shows the operation when the delay amount of the variable delay device 130 is smaller than one cycle of the clock signal 111, and FIG. 5B shows the operation when the delay amount of the variable delay device 130 is one cycle of the clock signal 111. Shows the operation when. The delay amount of the variable delay device 130 is controlled by a frequency control signal from the frequency control signal input terminal 102.

  First, an operation when the delay amount of the variable delay device 130 is smaller than one cycle of the clock signal 111 will be described with reference to FIG. The variable delay device 130 receives the divided clock signal 121 and outputs a second delayed clock signal 131. The delay amount of the second delayed clock signal 131 with respect to the divided clock signal 121 is smaller than one cycle of the clock signal 111. On the other hand, the first delay unit 125 outputs a first delayed clock signal 126 obtained by delaying the divided clock signal 121 by one cycle of the clock signal 111. When the delay amount of the variable delay device 130 is smaller than one cycle of the clock signal 111, the second delayed clock signal 131 has a waveform whose phase is advanced with respect to the first delayed clock signal 126. At this time, the phase comparator 140 outputs a high-level up signal UP by the advance phase of the second delayed clock signal 131. While the up signal UP is at a high level, the switch 402 is turned on, the source current of the charge pump 150 flows, and the output voltage 161 of the low-pass filter 160 rises. At this time, the VCO 110 increases the frequency of the clock signal 111. As described above, when the phase of the second delayed clock signal 131 is ahead of the phase of the first delayed clock signal 126, the phase comparator 140 outputs the high level up signal UP, and the VCO 110 The frequency of the clock signal 11 to be output increases. That is, when the delay amount of the variable delay device 130 is reduced by the frequency control signal from the frequency control signal input terminal 102, the frequency of the clock signal 111 output from the VCO 110 is increased.

  Next, an operation when the delay amount of the variable delay device 130 is larger than one cycle of the clock signal 111 will be described with reference to FIG. The variable delay device 130 receives the divided clock signal 121 and outputs a second delayed clock signal 131. The delay amount of the second delayed clock signal 131 with respect to the divided clock signal 121 is larger than one cycle of the clock signal 111. On the other hand, the first delay unit 125 outputs a first delayed clock signal 126 obtained by delaying the divided clock signal 121 by one cycle of the clock signal 111. When the delay amount of the variable delay device 130 is larger than one cycle of the clock signal 111, the second delayed clock signal 131 has a waveform delayed from the first delayed clock signal 126. At this time, the phase comparator 140 outputs a high level down signal DN by the amount corresponding to the delayed phase of the second delayed clock signal 131. While the down signal DN is at a high level, the switch 403 is turned on, the sink current of the charge pump 150 flows, and the output voltage 161 of the low-pass filter 160 decreases. At this time, the VCO 110 decreases the frequency of the clock signal 111. As described above, when the phase of the second delayed clock signal 131 is delayed from the phase of the first delayed clock signal 126, the phase comparator 140 outputs the high level down signal DN, and the VCO 110 The frequency of the clock signal 111 to be output decreases. That is, when the delay amount of the variable delay device 130 is increased by the frequency control signal from the frequency control signal input terminal 102, the frequency of the clock signal 111 output from the VCO 110 is decreased.

  As described above, the voltage controlled oscillation circuit 100 forms a feedback loop for the VCO 110 and acts as a voltage controlled oscillation circuit as a whole. In this voltage controlled oscillation circuit 100, noise is suppressed compared to the VCO 110. Therefore, the use of the voltage controlled oscillation circuit 100 can contribute to the reduction of the phase noise of the output clock signal of the phase synchronization circuit.

  According to the present embodiment, the frequency of the clock signal 111 output from the clock signal output terminal 101 can be controlled by the frequency control voltage signal from the frequency control signal input terminal 102 of the voltage controlled oscillation circuit 100. By configuring the variable delay device 130 constituting the voltage controlled oscillation circuit 100 as a passive element, the voltage controlled oscillation circuit 100 can reduce phase noise. The present embodiment can provide the voltage controlled oscillation circuit 100 with small phase noise by reducing the noise of the variable delay device 130.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

DESCRIPTION OF SYMBOLS 100 Voltage control oscillation circuit, 101 Clock signal output terminal, 102 Frequency control signal input terminal, 110 VCO, 111 clock signal, 120 frequency divider, 121 frequency dividing clock signal, 125 1st delay device, 126 1st delay clock Signal, 130 variable delay, 131 second delayed clock signal, 140 phase comparator, 150 charge pump, 160 low pass filter

Claims (13)

A voltage controlled oscillator that outputs a clock signal having a frequency controlled by a control voltage; and
A frequency divider that outputs a divided clock signal obtained by dividing the clock signal;
A first delay unit that outputs a first delayed clock signal obtained by delaying the divided clock signal in synchronization with the clock signal;
A variable delay device that outputs a second delayed clock signal obtained by delaying the divided clock signal by a delay amount according to a frequency control signal;
A phase comparator that compares phases of the first delayed clock signal and the second delayed clock signal;
A charge pump for flowing a current to the first node or drawing a current from the first node according to a comparison result of the phase comparator;
A voltage-controlled oscillation circuit comprising: a low-pass filter that smoothes the voltage of the first node and feeds back the smoothed voltage as the control voltage to the voltage-controlled oscillator.   The voltage controlled oscillation circuit according to claim 1, wherein the variable delay device includes an RC delay device having a resistance and a capacitance.   The voltage controlled oscillation circuit according to claim 1, wherein the variable delay device includes a plurality of stages of RC delay devices each having a resistor and a capacitor.   4. The voltage controlled oscillation circuit according to claim 2, wherein the variable delay device includes a buffer provided before or after the RC delay device or both before and after the RC delay device. 5.   4. The voltage controlled oscillation circuit according to claim 3, wherein delay amounts of all of the plurality of stages of RC delay devices are controlled by the frequency control signal. 5. The delay amount of a part of the RC delay units of the plurality of stages is shorter than the period of the clock signal,
4. The voltage controlled oscillation circuit according to claim 3, wherein the delay amount of the remaining RC delay units of the plurality of stages of RC delay units is controlled by the frequency control signal.   7. The voltage controlled oscillation circuit according to claim 2, wherein one or both of a resistance value of the resistor and a capacitance value of the capacitor of the RC delay device is controlled by the frequency control signal. 8.   The voltage controlled oscillation circuit according to claim 1, wherein the first delay device delays the divided clock signal by one cycle or a plurality of cycles of the clock signal.   The voltage controlled oscillation circuit according to claim 8, wherein the number of cycles of the clock signal delayed by the first delay unit is smaller than a frequency division ratio of the frequency divider. When the phase of the second delayed clock signal is ahead of the phase of the first delayed clock signal, the frequency of the clock signal output by the voltage controlled oscillator increases,
The frequency of the clock signal output from the voltage-controlled oscillator decreases when the phase of the second delayed clock signal is delayed from the phase of the first delayed clock signal. 2. The voltage controlled oscillation circuit according to item 1. The low-pass filter has a capacitance connected to the first node;
When the phase of the second delayed clock signal is ahead of the phase of the first delayed clock signal, the charge pump flows a current into the first node, and 11. The voltage controlled oscillation circuit according to claim 1, wherein when a phase is delayed from a phase of the first delayed clock signal, a current is drawn from the first node. Furthermore, a clock signal output terminal for outputting the clock signal output from the voltage controlled oscillator to the outside,
The voltage controlled oscillation circuit according to claim 1, further comprising a frequency control signal input terminal for inputting the frequency control signal from outside. Outputting a clock signal having a frequency controlled by a control voltage by a voltage controlled oscillator;
Outputting a divided clock signal obtained by dividing the clock signal by a divider;
Outputting a first delayed clock signal obtained by delaying the divided clock signal in synchronization with the clock signal by a first delay device;
Outputting a second delayed clock signal obtained by delaying the divided clock signal by a delay amount according to a frequency control signal by a variable delay device;
Comparing the phase of the first delayed clock signal and the second delayed clock signal by a phase comparator;
Flowing a current to the first node or drawing a current from the first node according to the result of the comparison by a charge pump; and
A method of controlling a voltage controlled oscillation circuit, comprising: smoothing a voltage of the first node by a low pass filter and feeding back the smoothed voltage as the control voltage to the voltage controlled oscillator.

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