RU2530248C1 - Pulse frequency-phase detector - Google Patents

Abstract

FIELD: radio engineering, communication.

SUBSTANCE: when a detector is being changed over from a relay mode of frequency control to a storage state of a linear mode of phase control, periods of signals of compared frequencies have zero initial phase difference.

EFFECT: reducing the tine for transient processes in a circuit of phase automatic frequency control due to optimisation of a shaping algorithm of output control signals of a pulse frequency-phase detector.

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Description

The invention relates to electronics, and in particular to a pulse frequency-phase detector, intended for use as part of high-speed synthesizers of the frequency network (SSC) based on the pulse phase locked loop (PLL).

High-speed frequency response systems based on the PLL loop are important elements of such applications as communication systems with a jumping frequency, radio monitoring complexes, high-performance microprocessors with support for dynamic scaling of the supply voltage and frequency, and high-speed digital interfaces. The requirement to improve the characteristics of these systems determines an increase in the requirements for quality indicators of the PLL frequency response and, first of all, to increase the speed of transient processes (PP) of automatic tuning when switching frequencies. One of the ways to improve the PLL loop performance is to optimize the algorithm for generating the output control signals of the pulse frequency-phase detector during the PCB.

Figure 1 presents a typical structural diagram of a high-speed MSS based on the pulse PLL with an analog filter in the control circuit.

The composition of the NSS includes the following blocks:

1 - pulse frequency-phase detector (ICHFD);

2 - block controlled sources of charge pump current (ITNZ);

3 - analog filter of the control loop (PKU), consisting of capacitor C1, isodromic link R2, C2, low-pass filter (LPF) R3, C3 and switching element Sw;

4 - voltage controlled oscillator (VCO);

5 - frequency divider (DF) with the division factors N, Nup and Ndn, set by the control device;

6 - synchronization unit frequency divider (MFD).

The ICPD unit, comparing the phases of the signals of the reference frequency Fref and the feedback frequency Fcnt, generates signals Up and Dn, the installation of which is determined by the sign, and the duration - by the magnitude of the detected difference. In accordance with the signals Up and Dn, the ITNZ unit generates current pulses I _{0 of the} required polarity. Under the influence of current pulses, the voltage Vvco is formed on the PKU elements. In accordance with the voltage Vvco, an output frequency signal Fvco is generated at the output of the VCO, which is fed to the PM circuit to generate the Fcnt signal. The voltage Vvco is changed in such a way as to eliminate the phase error between the compared signals Fref and Fcnt and thereby introduce the PLL in synchronism. In the steady state, the duration of the pulses of the output signals of the ICHFD, and hence the pulses of the output current of the ITNZ, is practically approaching zero. In this case, the capacitors of the PKU operate as memory elements, while maintaining the voltage Vvco. The PLL loop multiplies the input reference frequency Fref to the output frequency Fvco by dividing the frequency Fvco by an appropriate factor. The amplitude of the output current of the ITNZ and the characteristics of the PKU determine the passband of the PLL.

To increase the speed of the PLL in transient mode while maintaining the specified filtering properties in the steady state, separate control modes are used depending on the magnitude of the phase mismatch of the signals of the compared frequencies Fref and Fcnt. When the phase difference of the compared signals Fref and Fcnt is less than ± 2π radians, a control is linearly dependent on the magnitude of the phase difference. If the phase difference between the Fref and Fcnt signals is more than ± 2π radians (and also after switching to a new synthesized frequency), the circuit is switched to relay control mode with frequency control, bandwidth expansion of the circuit and the use of favorable phase relations due to RF synchronization by pulses of the reference frequency signal. In the relay mode of frequency regulation, the control action is continuously generated, and its value does not depend on the magnitude of the phase difference, which eliminates the beating in the control (slip cycles) and accelerates the development of a large phase difference circuit.

Considering that the presence of an RF in the feedback circuit introduces additional inertia into the circuit, in order to prevent significant overshoot, the moment of withdrawal of the circuit from the relay control of the frequency control is shifted in the direction of advance. To this end, the output frequency of the VCO is divided by a value different from that required in the steady state, but providing the necessary lead. The selection of the appropriate division coefficient Nup or Ndn is carried out according to the state of the signals Relay, Up and Dn.

In the relay frequency control mode, the synchronization (reset to the initial state) of the PM is carried out according to the pulses of the signal of the reference frequency Fref. Corresponding pulses of the Sync signal are generated by the SDC block, a typical block diagram of which is shown in FIG. The pulse width of the Sync signal is determined by the switching delays of the inverters L61 and L62.

Due to the synchronization of the PM, the loop returns to the linear phase control mode as soon as the lead frequency is reached (a condition is to change the sign of the difference in the periods of the compared frequencies). Thus, preconditions are created in the circuit for setting the phase relations favorable from the point of view of the fast termination of PP.

The bandwidth of the circuit is expanded by increasing the current amplitude of the ITNZ with simultaneous corresponding shunting of the resistance of the resistor R2 of the isodromic link by a switching element Sw with a small residual resistance. After the loop returns to linear phase control, the bandwidth is restored to its original value.

The transition to the relay mode of frequency control can also be carried out within the interval of the phase difference of ± 2π radians.

A decisive influence on the dynamics of the PLL circuit of the PLL is provided by the algorithm for generating the output control signals of the ICPD, the choice of the moment the circuit is removed from the relay mode of the frequency control and, especially, the initial conditions when the ICPD returns to the linear phase control mode.

The closest technical solution to the claimed invention is the ICPD scheme described in the patent of the Russian Federation No. 2483434 (C1) "Pulse Frequency Phase Detector", IPC H03D 13/00 [1]. This scheme is selected as a prototype of the claimed invention and is shown in figure 3.

The first common feature with the claimed invention is that when the phase difference of the input signals of the compared frequencies is exceeded, the values are ± 2π radians, the circuit of the invention [1] generates control signals that transfer the PLL from the linear phase control mode to the relay frequency control mode. The second common feature with the claimed invention is that when the frequency control is in the relay mode in case of a change in the sign of the difference of the compared frequencies, the circuit of the invention [1] generates control signals that translate the PLL directly into the initial state of charge storage in the PKU, i.e. . bypassing the intermediate states of the linear phase control mode.

The ICHPD scheme of the invention [1] has: first (Fref) and second (Fcnt) inputs; the first (Up1), second (Dn1), third (Up2) and fourth (Dn2) outputs; first (D1), second (D2), third (D3), fourth (D4), fifth (D5) and sixth (D6) memory elements; the first (L1) and second (L2) logic elements. The storage elements have inputs and outputs, designated as: information input - “D”, information output - “Q”, inverted information output - “NQ”, clock input - “C”, installation input - “R”.

The clock inputs of the elements D1, D3, D5 and D6 are interconnected and connected to the input Fref of the device. The clock inputs of the elements D2 and D4 are interconnected and connected to the input Fcnt of the device. The information output of the element D1, the information input of the element D3 and the first input of the element L1 are interconnected and connected to the output Up1 of the device. The information output of the element D2, the information input of the element D4 and the second input of the element L1 are interconnected and connected to the output Dn1 of the device. The information output of the element D3 is connected to the output Up2 of the device. The output of the element L2 is connected to the output Dn2 of the device. The information input of the element D1, the inverted information output of the element D4 and the installation input of the element D5 are interconnected. The installation inputs of the elements D1, D2, D3 and D6 and the output of the element L1 are interconnected. The installation input of the element D4 and the information output of the element D5 are interconnected. The first input of the element L2, the information output of the element D4 and the information input of the element D6 are interconnected. The second input of the element L2 and the information output of the element D6 are interconnected. The information inputs of elements D2 and D5 are connected to the level “log.1”.

Figure 4 in the form of a directed graph presents an algorithm of state transitions and the formation of the output control signals of the ICHPD scheme of the invention [1]. The group of states corresponding to the charge storage mode in the PKU is designated as “Keep”. The capacitors are recharged in PKU in the corresponding states, designated as “Up” and “Dn”, and the accelerated recharge by the increased current value of the ITNS is carried out in the states of the frequency control relay mode, indicated as “Relay”.

Figure 5 presents the state table of the ICHPD scheme of the invention [1] for the corresponding states of the transition graph of figure 4. In states 2 and 4, the relay mode of frequency control is carried out. To generate the Relay signal, the output signals of the ICHPD circuit Up2 and Dn2 are combined by the function “log. OR".

The ICPD scheme of the invention [1] has the following disadvantage. After the ICHPD returns from state 2 of the relay control mode to the initial state of storage of the linear phase control mode, the phase of the reference signal Fref and the start of counting in the frequency converter are not synchronized, which increases the initial phase difference in the first clock cycle of the linear mode comparison and, accordingly, increases the PCB duration, necessary to work out this difference.

The technical result of the claimed invention is to minimize the duration of the PCB of the pulse PLL due to the fact that when the ICHP from the relay frequency control mode to the storage state of the linear phase control mode, the signal periods of the compared frequencies Fref and Fcnt have a zero initial phase difference.

The specified technical result is achieved by the fact that before returning to the initial state of storage of the linear phase control mode, the ICHP scheme of the claimed invention has an additional storage state in which the beginning of periods of the compared frequencies Fref and Fcnt are synchronized while blocking the generation of output control signals Up and Dn.

To ensure this functionality, the ICHPD scheme of the claimed invention, to the ICHPD scheme of the invention [1], having first and second inputs; first, second and third exits; first, second, third, fourth, fifth and sixth storage elements; first and second logical elements; the clock inputs of the first, third and sixth storage elements are interconnected and connected to the first input of the device; the clock inputs of the second and fourth storage elements are interconnected and connected to the second input of the device; the information output of the first and the information input of the third storage elements and the first input of the first logical element are interconnected and connected to the first output of the device; installation inputs of the first and third storage elements are interconnected; the information input of the second storage element is connected to the level of the logical unit; the information output of the second storage element and the second input of the first logical element are interconnected; the installation input of the second storage element and the output of the first logical element are interconnected; the information input of the sixth storage element and the first input of the second logic element are interconnected; the information output of the sixth storage element and the second input of the second logic element are interconnected, it is proposed to introduce the third, fourth, fifth, sixth and seventh logic elements; the output of the third logical element is connected to the second output of the device; the output of the fourth logical element is connected to the third output of the device; connect the information input of the first storage element to the level of the logical unit; to connect the inverted information output of the first storage element and the first input of the fifth logic element; to connect the installation input of the first storage element and the output of the sixth logic element; connect the first inputs of the third and seventh logical elements to each other and connect to the information output of the second storage element; to connect the information output of the third and the information input of the fifth storage elements and the first input of the fourth logical element; to connect the information input of the fourth storage element and the output of the seventh logic element; to connect the information output of the fourth storage element and the second inputs of the third, fourth and seventh logic elements to each other; to connect the inverted information output of the fourth storage element and the second input of the fifth logic element; to connect the installation input of the fourth storage element, the output of the fifth and the first input of the sixth logic elements; connect the third input of the fifth and second input of the sixth logic elements to each other and connect to the output of the first logical element; to connect the information output of the fifth storage element, the first input of the second and third inputs of the fourth and sixth logic elements; set the inputs of the fifth and sixth storage elements and the output of the second logic element to interconnect; connect the clock input of the fifth storage element to the second input of the device.

As a result, the claimed ICPD scheme upon exiting the frequency control relay mode, before returning to the initial storage state of the linear phase control mode, has an additional storage state in which the beginning of the periods of the signals of the compared frequencies Fref and Font is synchronized while blocking the generation of the output control signals Up and Dn that provides a zero initial phase difference of the periods of the compared frequencies Fref and Fcnt and, accordingly, contributes to the fast termination of the PP.

The invention is illustrated by the following graphic materials.

Figure 1. A typical block diagram of a high-speed MSS based on a pulse PLL with an analog filter in the control loop.

Figure 2. Typical block diagram of the SDM.

Figure 3. The ICHPD scheme presented in the invention [1] and selected as an analogue of the prototype of the claimed invention.

Figure 4. The algorithm of the ICHFD scheme of the invention [1] in the form of a directed graph.

Figure 5. The state table of the ICPD scheme of the invention [1] for the corresponding states of the transition graph of FIG.

6. Scheme ICPD claimed in this invention.

7. The algorithm of the ICHFD scheme claimed in this invention, in the form of a directed graph.

Fig. 8. The state table of the ICPD scheme claimed in this invention for the corresponding states of the transition graph of Fig. 7.

Fig.9. State diagrams and the formation of the output control signals of the ICHFD circuit during the Fvco frequency auto-tuning software during frequency tuning up.

Figure 10. State diagrams and the formation of the output control signals of the ICHFD circuit during the Fvco frequency auto-tuning software during downward tuning.

The inventive circuit ICHFD is presented in Fig.6.

The ICHFD circuit has: first (Fief) and second (Fcnt) inputs; first (Up), second (Dn) and third (Relay) outputs; first (D1), second (D2), third (D3), fourth (D4), fifth (D5) and sixth (D6) memory elements; the first (L1), second (L2), third (L3), fourth (L4), fifth (L5), sixth (L6) and seventh (L7) logic elements. The storage elements have inputs and outputs, designated as: information input - “D”, information output - “Q”, inverted information output - “NQ”, clock input - “C”, installation input - “R”.

The clock inputs of the elements D1, D3 and D6 are interconnected and connected to the input Fref of the device. The clock inputs of the elements D2, D4 and D5 are interconnected and connected to the Fcnt input of the device. Information inputs of elements D1 and D2 are connected to the level “log.1”. The information output of the element D1, the information input of the element D3 and the first input of the element L1 are interconnected and connected to the output Up of the device. The inverted information output of the element D1 and the first input of the element L5 are interconnected. The information output of the element D2, the second input of the element L1, the first inputs of the elements L3 and L7 are interconnected. The installation inputs of the elements D1 and D3 and the output of the element L6 are interconnected. The information output of the element D3, the information input of the element D5 and the first input of the element L4 are interconnected. The information input of the element D4 and the output of the element L7 are interconnected. The information output of the element D4 and the second inputs of the elements L3, L4 and L7 are interconnected. The inverted information output of the element D4 and the second input of the element L5 are interconnected. The installation input of the element D4, the output of the element L5 and the first input of the element L6 are interconnected. The installation input of the element D2, the output of the element L1, the third input of the element L5 and the second input of the element L6 are interconnected. The information output of the element D5, the information input of the element D6, the first input of the element L2, the third inputs of the elements L4 and L6 are interconnected. The installation inputs of the elements D5 and D6 and the output of the element L2 are interconnected. The information output of the element D6 and the second input of the element L2 are interconnected. The output of element L3 is connected to the output Dn of the device. The output of the L4 element is connected to the relay output of the device.

Figure 7 presents the algorithm of the ICHFD circuit claimed in this invention in the form of a directed graph.

On Fig presents a state table of the scheme ICPD claimed in this invention, for the corresponding states of the transition graph of Fig.7. States 0 to 4 of the table of FIG. 8 coincide with the corresponding states of the table of FIG. 5 for the invention [1].

With an increase in the phase difference during PP over -2π radians, the ICPD scheme goes into state 4 of the algorithm. According to the signal Fref, the ICHPD circuit enters state 5 of the algorithm. States 4 and 5 of the algorithm are relay control states in which the FM synchronization is performed by the Fref signal. Next, the ICPD scheme is switched between states 4 and 5 of the algorithm until the difference sign of the compared frequencies changes, which transfers the ICPD to the initial state 0 of the algorithm. Moreover, at the moment the ICPD enters the initial state 0 of the algorithm, the beginning of the frequency periods of the compared signals Fref and Fcnt will be synchronized, as in the invention [1].

The state transition algorithm of the ICPD scheme of the claimed invention, as a result of which, before returning the ICPD from the relay frequency control mode to the initial state of storage of the linear phase control mode, the beginning of the periods of the compared frequencies is synchronized with the simultaneous blocking of the output of the output control signals, as follows.

When the phase difference of the signals of the compared frequencies increases during PP, it exceeds + 2π radians, the ICHP circuit goes into state 2 of the algorithm, in which the elements D1 and D3 are in the “log.1” state. When a Fref signal arrives, this state is maintained and the PM is synchronized. Due to the synchronization of the PM, the generation of the Fcnt signal (and the subsequent transition to state 6 of the algorithm) will occur only when the sign of the difference in the phased periods of the compared frequencies is changed, i.e. after reaching the desired lead time.

When the Fcnt signal arrives, the elements D2 and D5 are set to the state “log.1”, which through the elements L1 and L7 will asynchronously reset the elements D1, D2 and D3 to the state “log.0”. In contrast to the invention [1], the ICPD scheme of the claimed invention will go into state 6 of the algorithm, which is an additional state of charge storage in the FC, in which the output signal Relay maintains the state of “log.1”, which is necessary for the SDC circuit to generate a Sync signal for synchronizing the PM at the signal of Fref. In this case, the state "log.1" of the element D5 asynchronously holds the state "log.0" element D1.

By the signal Fref, the element D6 is set to the state “log.1”, which through the element L2 will asynchronously reset the elements D5 and D6 to the state “log.0”. As a result, the Fref signal is locked for one clock cycle to set the D1 element (and, accordingly, the output signal Up) to the “log.1” state, the ICHP circuit will go to the initial state 0 of the algorithm. The next incoming pulses of the Fref and Fcnt signals will give the difference of the two phased compared periods for the initial state 0 of the algorithm, which reduces the initial phase difference in the first comparison cycle in the linear phase control mode.

If in the state 6 of the algorithm an Fcnt signal arrives, then the element D2 will be set to the state “log.1”, and the element D5 will be set to the state “log.0” and the ICPD circuit will go to state 3 of the algorithm.

Thus, the transition of the ICPD scheme from the relay mode of frequency control (state 2 of the algorithm) to the additional state of charge storage in the PCF (state 6 of the algorithm), when the transition from which to the initial state 0 of the algorithm, the PM is synchronized by the reference frequency signal Fref, is necessary and sufficient condition for synchronizing the periods of the signals of the compared frequencies when the ICHPD circuit returns to the linear phase control mode.

As an example, Fig.9 and Fig.10 presents a diagram of the results of the simulation of PP in the FSS circuit of the pulse PLL using the ICHP scheme of the claimed invention. According to the diagrams, one can see state transitions and the formation of the output control signals of the ICHFD, draw conclusions about the quality of control, evaluate the values of overshoot and the duration of the PCB. The value of the output synthesized frequency Fvco is presented in normalized form.

Figure 9 presents the state diagrams and the formation of the output control signals of the ICHFD circuit during the Fvco frequency auto-tuning software when tuning in frequency upwards, and in Figure 10 when tuning in frequency downward.

As follows from the presented diagrams, the development of the residual phase difference after the ICPD scheme returns to the linear phase control mode begins with the most favorable, from the point of view of the fast termination of PC, trajectories of the phase space, which confirms the possibility of obtaining high speed in the MSS based on the pulse PLL using the claimed scheme ICHFD.

In the initial stage of the PCB, the PLL circuit behaves as a speed-optimal relay system, closed in frequency, using pre-emption and quick setting of voltage on the PKU capacitors.

Continuous monitoring in the relay mode of the frequency difference Fref and Fcnt (using the synchronization of the PM) provides a transition to the linear phase control region as soon as the VCO crosses the lead frequency limit.

Moreover, the synchronization of the periods of the compared frequencies before returning to the initial state of the linear phase control mode provides a zero initial phase difference, which contributes to the rapid completion of the SP.

The described ICHPD scheme can have various alternative options for its implementation, depending on the used circuitry basis of the storage and logical elements while maintaining the specified functionality and the algorithm for generating the output control signals.

Claims (1)

Frequency-phase detector having first and second inputs; first, second and third exits; first, second, third, fourth, fifth and sixth storage elements; first and second logical elements; the clock inputs of the first, third and sixth storage elements are interconnected and connected to the first input of the device; the clock inputs of the second and fourth storage elements are interconnected and connected to the second input of the device; the information output of the first and the information input of the third storage elements and the first input of the first logical element are interconnected and connected to the first output of the device; installation inputs of the first and third storage elements are interconnected; the information input of the second storage element is connected to the level of the logical unit; the information output of the second storage element and the second input of the first logical element are interconnected; the installation input of the second storage element and the output of the first logical element are interconnected; the information input of the sixth storage element and the first input of the second logic element are interconnected; the information output of the sixth storage element and the second input of the second logic element are interconnected, characterized in that the third, fourth, fifth, sixth and seventh logic elements are introduced; the output of the third logic element is connected to the second output of the device; the output of the fourth logic element is connected to the third output of the device; the information input of the first storage element is connected to the level of a logical unit; the inverted information output of the first storage element and the first input of the fifth logic element are interconnected; the installation input of the first storage element and the output of the sixth logic element are interconnected; the first inputs of the third and seventh logical elements are interconnected and connected to the information output of the second storage element; the information output of the third and the information input of the fifth storage elements and the first input of the fourth logical element are interconnected; the information input of the fourth storage element and the output of the seventh logical element are interconnected; the second inputs of the third, fourth and seventh logic elements and the information output of the fourth storage element are interconnected; the inverted information output of the fourth storage element and the second input of the fifth logic element are interconnected; the installation input of the fourth storage element, the output of the fifth and the first input of the sixth logic elements are interconnected; the third input of the fifth and second input of the sixth logic elements are interconnected and connected to the output of the first logical element; the information output of the fifth storage element, the first input of the second, third inputs of the fourth and sixth logic elements are interconnected; the installation inputs of the fifth and sixth memory elements and the output of the second logic element are interconnected; the clock input of the fifth storage element is connected to the second input of the device.

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