TWI411236B - Phase locked loop circuits - Google Patents

Abstract

A phase locked loop circuit is provided. The PLL circuit receives an input clock signal and generates an output clock signal according to internal clock signals with phase shifting which are generated according to the input clock signal. The PLL circuit includes a selector, a dividing unit, a converter, a low pass filer (LPF), and a modulator. The selector selects one of the internal clock signals to serve as a selection clock signal according to an enable signal. The first dividing unit performs dividing operations to the selection clock signal to generate the output clock signal and a feedback clock signal. The converter detects phase difference between the feedback clock signal and a reference clock signal to generate a detection signal. The LPF performs a filtering operation to the detection signal to generate a filtering signal. The modulator modulates the filtering signal to generate the enable signal.

Description

Phase locked loop circuit

The present invention relates to a phase locked loop (PLL), and more particularly to a dual loop PLL circuit for locking low frequency signals.

In a conventional two-loop phase locked loop (PLL) circuit, if an input clock signal having a low frequency (for example, 15K-100KHz applied to a video application) is input to a dual-loop PLL circuit as a reference When a low-frequency (eg, 10M-300MHz) output clock signal is generated by the main PLL loop of the dual-loop PLL circuit, the low-pass filter in the main PLL loop must have a larger capacitor to reduce the output jitter. However, the low pass filter having a larger capacitor in the main PLL loop occupies a larger area, so that the overall area of the dual loop PLL circuit is thus increased.

Accordingly, it is desirable to provide a dual loop PLL circuit with a smaller low pass filter to lock low frequencies.

The present invention provides a phase locked loop (PLL) circuit for receiving an input clock signal and generating an output clock signal based on a plurality of internal clock signals having a phase offset. The internal clock signals are generated based on the input clock signal. The PLL circuit includes a selector, a first frequency dividing unit, a converter, a first low pass filter, and a modulator. The selector receives the internal clock signals and outputs a selected clock signal. The selector selects one of the internal clock signals as a selection clock signal based on the coincidence signal. The first frequency dividing unit receives the selected clock signal, and performs a complex frequency dividing operation on the selected clock signal to generate an output clock signal and a first feedback clock signal. The converter receives the first feedback clock signal and a reference clock signal, and detects a phase difference between the first feedback clock signal and the reference clock signal to generate a detection signal. The first low pass filter receives the detection signal and performs a filtering operation on the detection signal to generate a filtered signal. The modulator receives and modulates the filtered signal to produce an enable signal.

The above described objects, features and advantages of the present invention will become more apparent from the description of the appended claims.

Figure 1 is a diagram showing a dual loop phase locked loop (PLL) circuit in accordance with an embodiment of the present invention. Referring to FIG. 1, the dual loop PLL circuit 1 includes two PLL loops 10 and 11. The dual-loop PLL circuit 1 receives an input clock signal XTAL and a reference clock CKref, and generates an output clock signal PLLCK according to the input clock signal XTAL and the reference clock CKref. As shown in FIG. 1, the PLL loop 10 receives the input clock signal XTAL and generates a plurality of internal clock signals according to the input clock signal XTAL, wherein the internal clock signals have a phase offset from each other. The frequency of the input clock signal XTAL is fixed and generated by an oscillator such as a quartz oscillator. In this embodiment, for example, the frequency of the input clock signal XTAL is set to 24.57 MHz, and the frequencies F of the internal clock signals are identical to each other and set to 1.57 GHz. In this embodiment, eight internal clock signals CKin0-CKin7 are illustrated as an example. The phases of the internal clock signals CKin0-CKin7 are sequentially shifted by a fixed period. For example, referring to FIG. 2, the phase of the internal clock signal CKin4 is shifted backward with respect to the clock of the previous internal clock signal CKin3 by the period DT (8/F=1/(0.125*F)), and the latter internal The phase of the clock signal CKin5 is shifted backward by the period DT with respect to the clock of the internal clock signal CKin4. In other words, the phase of the internal clock signal CKin4 is shifted backward by the frequency difference of 0.125*F for the clock of the previous internal clock signal CKin3, and the phase of the latter internal clock signal CKin5 is relative to the internal clock signal. The clock of CKin4 is shifted backward by a frequency difference of 0.125*F.

The PLL loop 11 receives the internal clock signals CKin0-CKin7 and the reference clock CKref, and generates an output clock signal PLLCK. In this embodiment, for example, the frequency of the reference clock CKref is set to 10 kHz. Referring to FIG. 1, the PLL loop 11 includes a selector 110, a frequency dividing unit 111, a converter 112, a low pass filter 113, and a modulator 114. The selector 110 receives the internal clock signals CKin0-CKin7 and outputs a selection clock signal Ssel according to the coincidence signal Sen. The selector 110 is enabled by the enable signal Sen to select one of the internal clock signals CKin0-CKin7 as the selection clock signal Ssel. The selector 110 also receives a decision signal Sdec. This decision signal Sdec is used to control the selection direction of the selector 110. In other words, the selector 110 determines, based on the decision signal Sdec, that it is about to switch from the selected internal clock signal to select the previous or next internal signal. It is assumed that the selector 110 currently selects the internal clock signal CKin4 and it decides to switch to the selection of a forward direction according to the decision signal Sdec. When the enable signal Sen is triggered to enable the selector 110, the selector 110 switches from selecting the internal clock signal CKin4 to selecting the previous internal clock signal CKin3. Referring to FIGS. 2 and 3, before time point T31, selector 110 selects internal clock signal CKin4, and the phase of the selected clock signal Ssel is the same as the phase of internal clock signal CKin4. When the enable signal Sen is triggered between the time points T31 and T32 to enable the selector 110, the selector 110 switches from the selected internal clock signal CKin4 to select the previous internal clock signal CKin3 in the forward direction. Therefore, after the time point T32, the phase of the selected clock signal Ssel is the same as the phase of the internal clock signal CKin3. As shown in Fig. 3, between the time points T30 and T32, the frequency of the signal Ssel at the time of selection becomes equal to F*1.125. After the time point T32, the frequency of the selection signal Ssel is equal to F.

It is assumed that the selector 110 currently selects the internal clock signal CKin4 and it decides to switch to the selection of a backward direction according to the decision signal Sdec. When the enable signal Sen is triggered to enable the selector 110, the selector 110 switches from selecting the internal clock signal CKin4 to selecting the latter internal clock signal CKin5. Referring to FIGS. 2 and 4, before time point T41, selector 110 selects internal clock signal CKin4, and the phase of the selected clock signal Ssel is the same as the phase of internal clock signal CKin4. When the enable signal Sen is triggered between the time points T41 and T42 to enable the selector 110, the selector 110 switches from the selected internal clock signal CKin4 to select the latter internal clock signal CKin5 in the backward direction. Therefore, after the time point T42, the phase of the selected clock signal Ssel is the same as the phase of the internal clock signal CKin5. As shown in Fig. 4, between the time points T40 and T42, the frequency of the signal Ssel at the time of selection becomes equal to F*0.875. After the time point T42, the frequency of the selection signal Ssel is equal to F.

Since the selector 110 can switch to select one of the internal clock signals CKin0-CKin7 according to the enable signal Sen, the average frequency of the selected clock signal Ssel can be adjusted to a desired value. In this embodiment, the average frequency of the adjusted clock signal Ssel is, for example, 1.6 GHz. The clock signal Ssel is then selected by the frequency dividing unit 111 to perform frequency division to generate an output clock signal PLLCK. As described above, the output clock signal PLLCK having the desired frequency can be generated by adjusting the average frequency of the selected clock signal Ssel by the selector 100 and by performing the frequency division operation on the selected clock signal Ssel by the frequency dividing unit 111. In this embodiment, for example, the frequency of the output clock signal PLLCK is 200 MHz.

As shown in Fig. 1, the frequency dividing unit 111 includes two frequency dividers 111A and 111B. The frequency divider 111A receives the selected clock signal Ssel and divides the selected clock signal Ssel by an integer INTA to generate an output clock signal PLLCK. The frequency divider 111B receives the output clock signal PLLCK and divides the output clock signal PLLCK by an integer INTB to generate a feedback clock signal CKfb11.

The converter 112 receives the feedback clock signal CKfb11 from the divider 111B and the reference clock signal CKref. Converter 112 also receives internal clock signals CKin0-CKin7 from PLL loop 10 as the operating clock for converter 112. The converter 112 detects the phase difference between the feedback clock signal CKfb11 and the reference clock CKref according to its working clock to generate the detection signal Sdet. In this embodiment, the detection signal Sdet is a digital signal. The converter 112 can be implemented by a time-to-digital converter (T2D converter).

In this embodiment, the low pass filter 113 is a digital low pass filter (DLPF). The DLPF 113 receives the digital detection signal Sdet from the T2D converter 112. The DPLF 113 performs a filtering operation on the digital detection signal Sdet to filter the high frequency noise from the digital detection signal Sdet to generate a filtered signal Sf. The modulator 114 receives the filtered signal Sf and modulates the filtered signal Sf to generate the enable signal Sen to control the selector 110. For example, when the enable signal Sen is triggered to enable the selector 110 of one of the internal clock signals CKin0-CKin7 to be selected, the selector 110 switches to select one/next before the selected internal clock signal is selected. The internal clock signal is used as the selection clock signal Ssel. When the enable signal Sen is reverse enabled, the selector 110 continues to output the selected internal clock signal as the selection output signal Ssel. In other words, the selector 110 does not switch to selecting one of the other internal clock signals as the selection clock signal Ssel. In this embodiment, the modulator 114 operates at a high frequency operating clock and can function as a sigma-delta modulator (SDM).

Through the feedback loop from the frequency division unit 111 through the T2D converter 112 and the DLPF 113 to the modulator 114, the selector 110 continuously adjusts the selected clock signal Ssel according to the enable signal Sen derived from the output clock signal PLLCK. The average frequency until the average frequency of the selected clock signal Ssel reaches the desired value.

In the embodiment of FIG. 1, the PLL loop 10 receives the input clock signal XTAL and generates a complex internal clock signal CKin0-CKin7 having a phase offset based on the input clock signal XTAL. A PLL loop capable of generating a complex internal clock signal having a phase offset based on one of the fixed frequency input clock signals can be used to implement the PLL loop 10 of the present embodiment.

Fig. 5 is a view showing an embodiment of the PLL circuit 10 in the dual-loop PLL circuit 1 of Fig. 1. As shown in FIG. 5, the P loop 10 includes a phase frequency detector (PFD) 101, a charge pump (CP) 102, a low pass filter (LPF) 103, and a voltage controlled oscillator (voltage). a -controlled oscillator (VCO) 104, and a frequency dividing unit 105. The PFD 101 receives the input clock signal XTAL and a feedback clock signal CKfb10, and generates a control signal Spfd according to the phase difference between the input clock signal XTAL and the feedback clock signal CKfb10. The CP 102 receives the control signal Spfd from the PFD 101 and charges the control voltage Vcol at the output of the CP 102 in accordance with the control signal Spfd. Next, the LPF 103 receives the control voltage Vcol and performs a filtering operation on the control voltage Vcol. The VCO 104 receives the filtered control voltage Vcol, and generates an oscillation clock signal CKosc and the complex internal clock signals CKin0-CKin7 according to the filtered control voltage Vcol. Next, the frequency dividing unit 105 receives the oscillation clock signal CKosc, and performs a frequency dividing operation on the oscillation clock signal CKosc to generate the feedback clock signal CKfb10.

According to the above, the PLL circuit 10 generates and locks the internal clock signals CKin0 to CKin7 and the oscillation clock signal CKosc based on the internal clock signal XTAL and the feedback clock signal CKfb10 through the feedback loop via the frequency dividing unit 105. In the two-loop PLL circuit 1, it is not necessary to set the frequency of the input clock signal XTAL to a small value. As previously mentioned, the frequency of the input clock signal XTAL can be set to 24.57 MHz, which is much higher than the range of the conventional dual loop PLL circuit of 15K-100 KHz. In addition, the frequency F of the internal clock signal is equal to a higher value of 1.57 GHz. Therefore, the LPF 103 does not require a large capacitance to reduce the output jitter, so that the area of the PLL loop 10 can be reduced. Then, the PLL loop 11 generates an output clock signal PLLCK having a desired frequency of 200 MHz based on the internal clock signals CKin0-CKin7 from the PLL loop 10 and locked. Since the modulation 114 operates at high frequency operating pulses, the effect of output jitter can also be reduced.

The present invention has been disclosed in the above preferred embodiments, and is not intended to limit the scope of the present invention. Any one of ordinary skill in the art can make a few changes without departing from the spirit and scope of the invention. The scope of protection of the present invention is therefore defined by the scope of the appended claims.

Figure 1:

1. . . Dual loop PLL circuit

10, 11. . . PLL loop

110. . . Selector

111. . . Frequency division unit

111A, 111B. . . Frequency divider

112. . . converter

113. . . Low pass filter (LPF)

114. . . Modulator

CKin0-CKin7. . . Internal clock signal

CKfb11. . . Feedback clock signal

CKref. . . Reference clock

INTA, INTB. . . Integer

PLLCK. . . Output clock signal

Sdec. . . Decision signal

Sdet. . . Detection signal

Sen. . . Enable signal

Sf. . . Filtered signal

Ssel. . . Select clock signal

XTAL. . . Input clock signal

Figure 2:

CKin0-CKin7. . . Internal clock signal

Figure 3:

CKin3, CKin4. . . Internal clock signal

F. . . Internal clock signal frequency F

Ssel. . . Select the clock signal;

T30, T31, T32. . . Time point

Figure 4:

CKin4, CKin5. . . Internal clock signal

F. . . Internal clock signal frequency F

Ssel. . . Select clock signal

T40, T41, T42. . . Time point

Figure 5:

101. . . Phase frequency detector (PFD)

102. . . Charge pump (CP)

103. . . Low pass filter (LPF)

104. . . Voltage controlled oscillator (VCO)

105. . . Frequency division unit

CKfb10. . . Feedback clock signal

CKosc. . . Oscillating clock signal

Spfd. . . control signal

Vcol. . . Control voltage

Figure 1 shows a dual loop PLL circuit in accordance with an embodiment of the present invention;

Figure 2 is a diagram showing the internal clock signal in the dual-loop PLL circuit of Figure 1;

Figure 3 is a diagram showing the phase change of a selected clock signal generated in accordance with a selective operation embodiment of the internal clock signal in Figure 2 in the dual-loop PLL circuit of Figure 1;

Figure 4 is a diagram showing the phase change of a selected clock signal generated in accordance with another alternative operation embodiment of the internal clock signal in Figure 2 in the dual-loop PLL circuit of Figure 1;

Figure 5 shows a dual loop PLL circuit in accordance with another embodiment of the present invention.

1. . . Dual loop PLL circuit

10, 11. . . PLL loop

110. . . Selector

111. . . Frequency division unit

111A, 111B. . . Frequency divider

112. . . converter

113. . . Low pass filter (LPF)

114. . . Modulator

CKin0-CKin7. . . Internal clock signal

CKfb11. . . Feedback clock signal

CKref. . . Reference clock

INTA, INTB. . . Integer

PLLCK. . . Output clock signal

Sdec. . . Decision signal

Sdet. . . Detection signal

Sen. . . Enable signal

Sf. . . Filtered signal

Ssel. . . Select clock signal

XTAL. . . Input clock signal

Claims (9)

A phase locked loop (PLL) circuit for receiving an input clock signal and generating an output clock signal according to a plurality of internal clock signals having a phase offset, wherein the internal clock signals are according to the Inputting a clock signal, and the PLL circuit includes: a selector for receiving the internal clock signals, and outputting a selected clock signal, wherein the selector selects the internal time according to the uniform energy signal One of the pulse signals is used as the selected clock signal; a first frequency dividing unit is configured to receive the selected clock signal, and perform a complex frequency dividing operation on the selected clock signal to generate the output clock signal and a first feedback clock signal; a converter for receiving the first feedback clock signal and a reference clock signal, and detecting a phase difference between the first feedback clock signal and the reference clock signal Generating a detection signal, and the converter is implemented by a time-to-digital converter (T2D converter); a first low-pass filter for receiving the detection signal, and Performing a filtering operation detection signal to generate a filtered signal; and a modulator for receiving and modulating the filtered signal to generate the enable signal. The PLL circuit of claim 1, wherein the phase of the selected internal clock signal is shifted backward relative to the phase of the previous internal clock signal of the selected internal clock signal, And the phase of the latter internal clock signal of the selected internal clock signal is shifted backward relative to the phase of the selected internal clock signal. The PLL circuit according to claim 2, wherein the The selector switches the selected internal clock signal to select the previous internal clock signal based on the enable signal. The PLL circuit of claim 2, wherein the selector switches the selected internal clock signal to select the latter internal clock signal according to the enable signal. The PLL circuit of claim 2, wherein the selector determines, according to a decision signal, that the selected internal clock signal is switched to select the previous or subsequent internal clock signal. The PLL circuit of claim 1, wherein the first frequency dividing unit comprises: a first frequency divider for receiving the selected clock signal, and selecting the clock with a first integer The pulse signal is divided to generate the output clock signal; and a second frequency divider is configured to receive the output clock signal, and divide the output clock signal by a second integer to generate the first A feedback clock signal. The PLL circuit of claim 1, further comprising a PLL loop for receiving the input clock signal and generating the internal clock signals. The PLL circuit of claim 1, wherein the converter receives the internal clock signals as a working clock of the converter. The PLL circuit of claim 1, wherein the modulator is implemented by a sigma-delta modulator (SDM).