CN101098141B

CN101098141B - Frequency synthesizer

Info

Publication number: CN101098141B
Application number: CN2007101122805A
Authority: CN
Inventors: 古幡司
Original assignee: Nihon Dempa Kogyo Co Ltd
Current assignee: Nihon Dempa Kogyo Co Ltd
Priority date: 2006-06-29
Filing date: 2007-06-29
Publication date: 2012-05-30
Anticipated expiration: 2027-06-29
Also published as: JP2010166605A; CN101098141A; JP4484940B2; JP4644302B2; JP2009077432A

Abstract

Disclosed is a frequency synthesizer capable of preventing occurrence of a frequency shift upon occurrence of a change in the level of an input to an A/D converter by preventing PLL control from being properly operated. The frequency synthesizer includes a carrier remove (16), an inverse rotational vector multiplier (17), a phase time difference detector (18), an adder (19), a phase difference accumulator (20), a loop filter (21), a parameter output part (25), an amplitude information detector (26), a filter (27), and a multiplier (28) configured by an FPGA. Unlock detection means monitors the value of amplitude information detected by the amplitude information detector (26). When the value lies within a proper range, a lock (synchronization) process is performed under PLL control, whereas when the value is off the proper range, an unlock state in PLL control is detected.

Description

Frequency synthesizer

Technical field

The present invention relates to obtain the frequency synthesizer (synthesizer) of the vibration output of desirable frequency; Be particularly related to when the incoming level to AD (analog digital) converter changes; Can prevent PLL (Phase Locked Loop; Phase-locked loop) controls the situation of moving undesiredly, can prevent to produce the frequency synthesizer of frequency shift (FS).

Background technology

With reference to Fig. 2 existing frequency synthesizer is described.Fig. 2 is the formation block diagram of existing frequency synthesizer.

Existing frequency synthesizer is as shown in Figure 2, possesses VCO (Voltage ControlledOscillator: voltage controlled oscillator) 1; Frequency divider 2; Reference oscillation circuit 3; A/D (Analogue/Digital, analog/digital) converter 4; Phase comparator 5; Digital filter 6; D/A (Digital/Analogue, digital-to-analog) converter 7; Analog filter 8.

VCO1 be from the input of analog filter 8 as control voltage, make the voltage controlled oscillator of desirable frequency Fout vibration.

Frequency divider 2 carries out 1/N ground frequency division to the frequency of oscillation Fout that in VCO1, generates, and outputs to A/D converter 3.

Reference oscillation circuit 3 makes reference signal (reference clock) Fref vibration.

A/D converter 4 is transformed to digital signal to the analog signal from frequency divider 2 according to the reference clock that provides from reference oscillation circuit 3.

5 pairs of phase comparators have carried out the frequency of digital conversion and have compared the output phase difference signal from the phase place of the reference signal of reference oscillation circuit 3 in A/D converter 4.

6 pairs of phase signals from phase comparator 5 of digital filter carry out filtering.

D/A converter 7 is the digital signal conversion from digital filter 6 analog signal according to the reference clock that provides from reference oscillation circuit 3.

Analog filter 8 is that the analog signal from D/A converter 7 is carried out smoothing, removes noise component(s), outputs to the loop filter (Loop Filter) of VCO1 as control voltage.

And, open in the flat 5-22131 communique (patent documentation 1) the spy and disclose, in the PLL frequency synthesizer, keep watch on the 1st value and the 2nd value of PLL, detection locks the lock detecting circuit (with reference to patent documentation 1) of the PLL circuit of (Lock) state.

And; Open in the flat 7-201137 communique (patent documentation 2) the spy and to disclose; In PLL Phase synchronization loop, the lock detecting method and the lock detection device (with reference to patent documentation 2) of the Phase synchronization loop of the counting of the AD value of supervision VCO, detection lock-out state or unlock state.

[patent documentation 1] spy opens the 5-22131 communique

[patent documentation 1] spy opens flat 7-201137 communique

But in above-mentioned existing frequency synthesizer, when the level of input A/D converter changed significantly, the PLL control in phase comparator was moved sometimes undesiredly, consequently, had the such problem of frequency shift (FS) that produces.

Specifically, as shown in Figure 3, at handle the amplitude of the incoming level signal of ADC (A/D converter) is arranged to from 0 to P (Peak; Peak value); When being arranged to for 4134 steps (step) by benchmark, frequency error is 0Hz, and incoming level is negative the increase at 90%, 80% o'clock frequency error; In addition, incoming level at 110%, 120% o'clock frequency error for just increasing.

Like this, if the incoming level relative datum value of ADC is changed greatly, then produce the problem that frequency error increases.

In addition, in above-mentioned patent documentation 1, the PLL circuit has been actually before the latch-release output latch-release circuit of such information, but in digital phase comparator for variation to the incoming level of A/D converter, do not prevent to produce frequency shift (FS).

In addition; In above-mentioned patent documentation 2; With the sampling clock that is based on the clock of regenerating in the Phase synchronization loop synchronously, be transformed to digital signal to regenerated signal, to the corresponding sampled value of clock module (clock pattern) in the edge of clock module near at least 2 sampled values compare, count the number of times of identical comparative result; Detect lock-out state during more than or equal to predetermined threshold value at number of times; After comparative result under lock-out state counter-rotating,, detect and be unlock state when the number of times of identical comparative result during more than or equal to predetermined threshold value; But this is the input signal that comparison other is postponed, and this look-ahead technique does not prevent to import relatively the frequency shift (FS) that the level of A/D converter changes yet.

Summary of the invention

The present invention proposes in view of above-mentioned actual conditions, and its purpose is to provide a kind of frequency synthesizer, when the incoming level to the A/D converter changes, can prevent the situation that PLL control is moved undesiredly and prevent to produce frequency shift (FS).

Be used for solving the invention is characterized in of problem of above-mentioned existing example: be equipped with at frequency synthesizer: the voltage controlled oscillator that makes the frequency signal vibration according to the control voltage of input; This oscillation frequency signal is carried out the frequency divider of frequency division; The signal of this frequency division is carried out the AD converter of analog/digital conversion; To the phase place through the signal of this analog/digital conversion and sine wave signal compare and detected phase poor, the phase place rating unit of output and the corresponding phase signal of this phase difference; This phase signal is carried out the DA converter of digital-to-analog conversion; Remove the loop filter of the noise of high fdrequency component; The phase place rating unit is equipped with multiplier as automatic gain control circuit on the back segment of AD converter; And the amplitude information test section of detecting the amplitude information of the gain be used to control this multiplier, have the value of keeping watch on amplitude information, when this value reaches specific scope, detect the release detecting unit of release.

The invention is characterized in: in the said frequencies synthesizer, the release detecting unit is kept watch on the maximum of detected amplitude information in the amplitude information test section in automatic gain control circuit, when this maximum during more than or equal to the 1st particular value, detects release.

The invention is characterized in: in the said frequencies synthesizer, the release detecting unit is kept watch on the minimum value of the detected amplitude information in amplitude information test section in automatic gain control circuit, when this minimum value during smaller or equal to the 2nd particular value, detects release.

The invention is characterized in: in the said frequencies synthesizer; The phase place rating unit possesses: orthogonal detection is carried out in the output to from the AD converter, the difference of the frequency of the signal that extraction and application is used from the output signal and the detection of AD converter and the carrier wave of the rotating vector that rotates is removed device (キヤリアリ system-Block); Rotating vector is multiplied by the counter-rotating vector multiplying part of counter-rotating vector; The time difference test section of the phase place of the phase difference in rotating vector each sampling time of detection that multiplying is slowed down according to process; From detected phase difference, deduct the adder of fine setting frequency; And certain hour adds up from the accumulator of the phase difference of the output of adder, and the release detecting unit is kept watch on the value of the output that divides from the vectorial multiplier of counter-rotating being carried out the amplitude information that the amplitude information test section branch of branch's input obtains.

According to the present invention, because frequency synthesizer is provided with as follows: possess the voltage controlled oscillator that makes the frequency signal vibration according to the control voltage of input; This oscillation frequency signal is carried out the frequency divider of frequency division; The signal of this frequency division is carried out the AD converter of analog/digital conversion; Phase place to through the signal of this analog/digital conversion and sine wave signal compares, detected phase is poor, the phase place rating unit of output and the corresponding phase signal of this phase difference; This phase signal is carried out the DA converter of digital-to-analog conversion; Remove the loop filter of the noise of high fdrequency component; The phase place rating unit possesses multiplier as automatic gain control circuit on the back segment of AD converter; And the amplitude information test section of detecting the amplitude information of the gain be used to control this multiplier; Have the value of keeping watch on amplitude information, the release detecting unit that when this value becomes specific scope, detects release, so, when making the automatic gain Control work, improving frequency accuracy; When becoming the scope of automatic gain control irregular working, carry out release and detect, so have the effect that can prevent to produce frequency shift (FS).

According to the present invention; Because the said frequencies synthesizer is provided with as follows: the phase place rating unit possesses orthogonal detection is carried out in the output from the AD converter, the difference on the frequency of the signal that extraction and application is used from the output signal and the detection of AD converter and the carrier wave of the rotating vector that rotates is removed device (キヤリアリ system-Block); Rotating vector is multiplied by the counter-rotating vector multiplying part of counter-rotating vector; Detect the time difference test section of phase place of the phase difference in each sampling time according to the rotating vector that slows down through multiplying; From detected phase difference, deduct the adder of fine setting frequency; Certain hour adds up from the part that adds up of the phase difference of the output of adder; The release detecting unit is kept watch on carry out the value of the resulting amplitude information in amplitude information test section of branch's input from the output of the vectorial multiplying part of counter-rotating; So, have the value that can utilize based on through the phase difference of the signal of orthogonal detection and carry out the effect that release detects.

Description of drawings

Fig. 1 is the block diagram of the frequency synthesizer of execution mode of the present invention.

Fig. 2 is the block diagram of existing frequency synthesizer.

Fig. 3 is the incoming level of expression ADC and the figure of frequency error.

Embodiment

With reference to description of drawings execution mode of the present invention.

The frequency synthesizer of execution mode of the present invention becomes constant mode with the output of AD converter automatic gain control circuit (agc circuit) is set; Utilization is judged the incoming level to the AD converter to the correction value of agc circuit; If this correction value is in optimum range; When then being controlled at the gain on the deferent segment of AD converter by agc circuit, the locking of carrying out in PLL control (synchronously) is handled, if should be worth outside optimum range; Then the release in PLL control is detected, therefore can prevent frequency shift (FS).

[formation of execution mode: Fig. 1]

The frequency synthesizer of execution mode of the present invention is described with reference to Fig. 1.Fig. 1 is the block diagram of the frequency synthesizer of execution mode of the present invention.

The frequency synthesizer (this frequency synthesizer) of execution mode of the present invention is as shown in Figure 1, comprising: VCO11; Frequency divider (NN) 12; LPF (Low Pass Filter, low pass filter) 13; AD converter (A/D) 14; Reference clock generates part 15; DA converter (D/A) 22; Voltage output 23; Adder 24; Part, carrier wave as being made up of FPGA (Field ProgrammableGate Array, field programmable gate array) are removed device (キヤリアリ system-Block) 16; The vectorial multiplying part 17 of reversing; The time difference test section 18 of phase place; Adder 19; The part 20 that adds up of phase difference; Loop filter 21; Parameter output 25; Amplitude information test section 26; Filter 27; And multiplier 28.

At this, constitute automatic gain control circuit (agc circuit) by amplitude information test section 26, filter 27, multiplier 28.

VCO11 be from the input of adder 24 as control voltage, make the desirable frequency (voltage controlled oscillator of vibration of 450MHz～1000MHz).

Frequency divider (NN) 12 is the output frequency division of VCO11 1/NN and outputs to LPF13 according to the frequency division value (NN) of the input from the outside.

LPF13 is the filter that the signal for frequency division in frequency divider 12 passes through the frequency of low frequency.

AD converter 14 is numeral through by the clock that generates the 40MHz (fs) of part 15 from reference clock the signal from LPF13 being sampled from analog converting, and the carrier wave that outputs to FPGA is removed device (キヤリアリ system-Block) 16.

DA converter 22 is to be the unit of simulation with the control signal of having been carried out adjustment control by FPGA from digital conversion, is 0～0.85V from the signal voltage of DA converter 22.

Voltage output 23 is based on magnitude of voltage and the unit of output voltage of autoregressive parameter output 25, its formation be output voltage for example along with the time through rising to predetermined voltage together linearly.

Adder 24 usefulness from the control signal of DA converter 22 output to revising, as the control voltage of VCO11 is exported from the voltage of voltage output 23 outputs.

The basic function of FPGA is, the rotating vector under desirable output frequency (setpoint frequency) and poor from rotating vector, the detected phase of the signal of AD converter 14 relatively generates the control signal of the frequency of oscillation of controlling VCO11 according to this phase difference.

Carrier wave is removed device (キヤリアリ system-Block) the 16th, such unit; To by from the digital signal of AD converter 14 specific sine wave signal, use the sine wave signal of 4MHz to carry out orthogonal detection, the frequency of the difference of the frequency of the frequency of the frequency signal that the digital signal of extraction and application AD converter 14 is specific and the sine wave signal that in detection, uses and the rotating vector V that rotates.

The vectorial multiplying part 17 of reversing is that rotating vector V is multiplied by from the unit of the counter-rotating vector V ' of parameter output 25 outputs.

The phase difference in each sampling time is detected according to the rotating vector V that in the vectorial multiplying part 17 of counter-rotating, slows down in the time difference test section 18 of phase place.This phase difference becomes the corresponding value of frequency with the rotating vector V that slows down.In addition, when the time difference test section 18 of phase place becomes zero at this phase difference, detect the locking in PLL, output to exterior portions to lock detecting signal.

Adder 19 deducts the value near desirable fine tuning of oscillating frequency frequency that is used for of in calculating in advance, trying to achieve from the output of the time difference test section 18 of phase place, and phase difference output.

The part 20 that adds up of phase difference is that certain hour adds up from the go forward side by side unit of line output of the output of adder 19.The part 20 usefulness filters that add up of phase difference constitute, and are set in optimum value to decay (damping).

And add up part 20 and parameter output 25 that carrier wave is removed time difference test section 18, adder 19, the phase difference of device (キヤリアリ system-Block) 16, the vectorial multiplying part of counter-rotating 17, phase place are equivalent to the described phase place rating unit of claim.

Loop filter 21 is basis accumulated values from the part 20 that adds up of phase difference, generates the data of control VCO11 and the unit of exporting as control signal.The control of carrying out loop filter 21 according to accumulated value is the output for stabilizing ring path filter 21.

Parameter output 25 is according to the frequency setting information (information of desirable frequency of oscillation) of input; As the output of VCO11, can obtain the mode of this frequency; As frequency parameter calculate frequency division value (NN), to the counter-rotating vector V ' of the vectorial multiplying part 17 of reversing, to the fine setting frequency of adder 19; And to the magnitude of voltage of voltage output 23, by the timing output above-mentioned parameter that further calculates etc.The vectorial V ' that reverses calculates according to rotating vector V and frequency setting information.Parameter output 25 can be stored in various parameters in advance in table etc. and read.

Amplitude information test section 26 input is from the output of the vectorial multiplying part 17 of counter-rotating, and the real part I and the imaginary part Q of rotating vector carried out I ²+ Q ²Calculating, output to filter 27 to the correction value of the AGC that tries to achieve from this result of calculation (amplitude information).Obtain the correction value in agc circuit according to amplitude information.

And then; The input amplitude scope that amplitude information test section 26 decision can be controlled, at set inside release detecting unit, and then setting threshold (PLL control become the value of the amplitude information that moves) undesiredly; The release detecting unit judges whether input amplitude has surpassed this threshold value; When surpassing, detect and output release detection signal, its synchronous release is handled.

And, detect though carry out release with the value of amplitude information, also can carry out release and detect with the correction value of the AGC that obtains based on amplitude information.

Filter 27 becomes the such characteristic of suitable automatic gain control, outputs to multiplier 28 to gain with the amplitude information of in amplitude information test section 26, trying to achieve relatively.

28 pairs of outputs from AD converter 14 of multiplier are multiplied by the output (gain) from filter 27, and output to carrier wave and remove device (キヤリアリ system-Block) 16.Be adjusted at the multiplying of the gain in this multiplier 28, it is constant to make that amplitude information becomes usually.

Below, the characteristic in this frequency synthesizer is described particularly.

In this frequency synthesizer; Though it is not shown; But the release detecting unit in the amplitude information test section 26 is kept watch on the value of amplitude information; Judge that whether these values become the value of particular range (value of the scope of the value of predefined scope=PLL control malfunction), if become the value of specific scope, then detect as release.

This release detecting unit also can be arranged in the amplitude information test section 26, but also can in FPGA, independently be provided with, and in addition, also can be arranged in other control circuit in the FPGA.

Like this in this frequency synthesizer; When the incoming level to AD converter 14 changes; The release detecting unit is utilized in the value of the amplitude information that obtains in the amplitude information test section 26, relevant incoming level to AD converter 14 judges whether PLL control is the scope of malfunction; When PLL control is the scope of malfunction, carries out release and detect.

In this frequency synthesizer; For example from keeping watch on maximum or the minimum value that is input to the value the filter 27 by the value of amplitude information test section 26 resultant amplitude informations; When its maximum become make PLL control malfunction more than or equal to the 1st particular value the time; Perhaps, when its minimum value become make PLL control malfunction smaller or equal to the 2nd particular value the time, carry out the detection of release.

That is,, when being the level of predefined scope (not making the scope of PLL control regular event), in this frequency synthesizer, detect, also can carry out alarm detection (alarm sound, output alarm shows) as release for the output signal level of AD converter 14.

According to this frequency synthesizer, when the incoming level to AD converter 14 has surpassed the scope of regular event of PLL control, carry out release and detect, have an effect that can prevent to produce frequency shift (FS).

The present invention is suitable for when the incoming level to the A/D converter changes, preventing the situation of PLL control malfunction, and can preventing to produce the frequency synthesizer of frequency shift (FS).

Claims

1. frequency synthesizer is characterized in that having:

Make the voltage controlled oscillator of frequency signal vibration according to the control voltage of input; This oscillation frequency signal is carried out the frequency divider of frequency division; The signal of this frequency division is carried out the AD converter of analog/digital conversion; To the phase place through the signal of this analog/digital conversion and sine wave signal compare and detected phase poor, the phase place rating unit of output and the corresponding phase signal of this phase difference; This phase signal is carried out the DA converter of digital-to-analog conversion; Remove the loop filter of the noise of high fdrequency component,

Above-mentioned phase place rating unit possesses multiplier as automatic gain control circuit on the back segment of above-mentioned AD converter; Be used to control the amplitude information test section of amplitude information of the gain of this multiplier with detection, and have the value of keeping watch on above-mentioned amplitude information, when this value becomes specific scope, carry out the release detecting unit that release detects.

2. frequency synthesizer as claimed in claim 1; It is characterized in that: the release detecting unit is kept watch on the maximum by the detected amplitude information in amplitude information test section in the automatic gain control circuit; When this maximum during, carry out release and detect more than or equal to the 1st particular value.

3. frequency synthesizer as claimed in claim 1; It is characterized in that: the release detecting unit is kept watch on the minimum value by the detected amplitude information in amplitude information test section in the automatic gain control circuit; When this minimum value during, carry out release and detect smaller or equal to the 2nd particular value.

4. like each described frequency synthesizer of claim 1 to 3, it is characterized in that:

The phase place rating unit possesses: the output signal to from the AD converter carries out orthogonal detection, the difference of the frequency of the signal that extraction and application is used from the output signal frequency and the detection of above-mentioned AD converter and the carrier wave of the rotating vector that rotates is removed device; Rotating vector is multiplied by the counter-rotating vector multiplying part of counter-rotating vector; The time difference test section of the phase place of the rotating vector that multiplying is slowed down based on process, the phase difference that detects each sampling time; From detected phase difference, deduct the adder of fine setting frequency; Certain hour adds up from the part that adds up of the phase difference of the output of above-mentioned adder; Wherein, the release detecting unit is kept watch on by to carry out the value of the resulting amplitude information in amplitude information test section of branch's input from the output of above-mentioned counter-rotating vector multiplying part.