JP2010166605A - Frequency synthesizer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a frequency synthesizer capable of preventing the generation of a frequency shift on the occurrence of changes in the level of an input to an A-D converter by preventing phase-locked loop (PLL) control from not properly being operated. <P>SOLUTION: The frequency synthesizer includes a carrier remove 16, an inverse rotational vector multiplier 17, a phase time difference detector 18, an adder 19, a phase difference accumulator 20, a loop filter 21, a parameter output part 25, an amplitude information detector 26, a filter 27, and a multiplier 28 configured of a field programmable gate array (FPGA). An unlock detection means monitors a value of amplitude information detected by the amplitude information detector 26. When the value lies within a proper range, a lock (synthesization) processing is performed under PLL control and when the value is off the proper range, an unlock state in PLL control is detected, thereby performing alarm detection in accordance with the unlock detection. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a frequency synthesizer that can obtain an oscillation output of a desired frequency, and in particular, when an input level to an AD (analog / digital) converter changes, PLL (Phase Locked Loop) control does not operate normally. The present invention relates to a frequency synthesizer that can prevent the occurrence of frequency deviation by preventing the situation.

A conventional frequency synthesizer will be described with reference to FIG. FIG. 4 is a configuration block diagram of a conventional frequency synthesizer.
As shown in FIG. 4, a conventional frequency synthesizer includes a VCO (Voltage Controlled Oscillator) 1, a frequency divider 2, a reference oscillation circuit 3, an A / D (Analogue / Digital) converter 4, , A phase comparator 5, a digital filter 6, a D / A (Digital / Analogue) converter 7, and an analog filter 8.

The VCO 1 is a voltage controlled oscillator that oscillates at a desired frequency Fout using the input from the analog filter 8 as a control voltage.
The frequency divider 2 divides the oscillation frequency Fout generated by the VCO 1 by 1 / N and outputs it to the A / D converter 3.
The reference oscillation circuit 3 oscillates a reference signal (reference clock) Fref.

The A / D converter 4 converts the analog signal from the frequency divider 2 into a digital signal according to the reference clock provided from the reference oscillation circuit 3.
The phase comparator 5 compares the frequency digitally converted by the A / D converter 4 with the phase of the reference signal from the reference oscillation circuit 3, and outputs a phase difference signal.
The digital filter 6 filters the phase difference signal from the phase comparator 5.

The D / A converter 7 converts the digital signal from the digital filter 6 into an analog signal according to the reference clock provided from the reference oscillation circuit 3.
The analog filter 8 is a loop filter that smoothes the analog signal from the D / A converter 7 to remove a noise component and outputs the smoothed signal to the VCO 1 as a control voltage.

  Japanese Patent Laid-Open No. 5-22131 describes a lock detection circuit of a PLL circuit that monitors a first value and a second value of a PLL and detects a lock state in a PLL frequency synthesizer (patent) Reference 1).

  Japanese Patent Application Laid-Open No. 7-2011137 describes a lock detection method and a lock detection device for a phase locked loop that monitors the AD value count of a VCO and detects a locked state or a non-locked state in a PLL phase locked loop. (See Patent Document 2).

JP-A-5-22131 Japanese Patent Laid-Open No. 7-2011137

  However, in the above conventional frequency synthesizer, when the input level to the A / D converter changes greatly, the PLL control in the phase comparator may not operate normally, and as a result, a frequency shift occurs. There was a point.

  Specifically, as shown in FIG. 3, when the input level to the ADC (A / D converter) is a signal amplitude ranging from 0 to P (Peak) with 4134 steps as a reference, the frequency error is When the input level is 90% and 80%, the frequency error is negatively increased, and when the input level is 110% and 120%, the frequency error is positively increased.

  Thus, if the input level to the ADC fluctuates greatly with respect to the reference value, there arises a problem that the frequency error becomes large.

  In Patent Document 1, information indicating that the PLL circuit has been unlocked before the lock is actually released is output. However, in the digital phase comparator, the input level to the A / D converter is changed. On the other hand, it does not prevent the occurrence of frequency deviation.

  In Patent Document 2, a reproduction signal is converted into a digital signal in synchronization with a sampling clock based on a clock reproduced in a phase-locked loop, and the vicinity of the edge of the clock pattern in the sampling value corresponding to the clock pattern is converted. Compare at least two sample values, count the number of the same comparison results, detect the lock state when the number is equal to or greater than a predetermined threshold, and after the comparison result is inverted in the lock state, A non-lock state is detected when the number of times is equal to or greater than a predetermined threshold, but the comparison target is a delayed input signal. This prior art is also used for a change in the input level to the A / D converter. It does not prevent frequency shift.

  The present invention has been made in view of the above circumstances, and when the input level to the A / D converter changes, a frequency synthesizer capable of preventing the occurrence of frequency deviation by preventing the situation where the PLL control does not operate normally. The purpose is to provide.

The present invention for solving the problems of the above conventional example is a frequency synthesizer, a voltage controlled oscillator that oscillates a frequency signal according to an input control voltage, a frequency divider that divides the frequency signal, An AD converter for analog / digital conversion of the frequency-divided signal, a phase difference signal corresponding to the phase difference detected by comparing the phase of the analog / digital converted signal and the sine wave signal A phase comparison unit that outputs high-frequency component noise in the phase difference signal, and a DA converter that performs digital / analog conversion on the phase difference signal from which the noise has been removed. as an automatic gain control circuit comprises a multiplier in the subsequent stage of the AD converter, and the amplitude information detector that detects amplitude information for controlling the gain of the multiplier, to monitor the values of the amplitude information, the There when it becomes a specific range and the unlock detection means for detecting the unlocked, characterized in that it has a means for performing the alarm detected by an unlock detection.

The present invention is characterized in that the frequency synthesizer outputs an alarm sound as an alarm detection .

The present invention is characterized in that the frequency synthesizer outputs an alarm display as an alarm detection .

According to the present invention, a voltage-controlled oscillator that oscillates a frequency signal according to an input control voltage, a frequency divider that divides the frequency signal, and AD conversion that performs analog / digital conversion on the frequency-divided signal A phase comparator for comparing the phase of the analog / digital converted signal and the sine wave signal to detect a phase difference and outputting a phase difference signal corresponding to the phase difference, and a high frequency in the phase difference signal A loop filter for removing component noise and a DA converter for digital / analog conversion of the phase difference signal from which the noise has been removed are provided, and the phase comparison unit multiplies the subsequent stage of the AD converter as an automatic gain control circuit. and vessels, and a amplitude information detector that detects amplitude information for controlling the gain of the multiplier, when monitoring the value of the amplitude information, the value becomes a specific range, the unlock Anro to detect A click detecting unit, since the frequency synthesizer and means for performing an alarm detected by an unlock detection, together with increasing the frequency accuracy exercising automatic gain control, Ann if automatic gain control becomes a range not operate properly Since an alarm is detected by performing lock detection, there is an effect of preventing occurrence of a frequency shift.

1 is a configuration block diagram of a frequency synthesizer according to an embodiment of the present invention. It is a block diagram of a conventional frequency synthesizer. It is a figure which shows the input level and frequency error of ADC.

[Summary of Invention]
Embodiments of the present invention will be described with reference to the drawings.
The frequency synthesizer according to the embodiment of the present invention is provided with an automatic gain control circuit (AGC circuit) so that the output from the AD converter becomes constant, and the input level to the AD converter is determined by the correction value to the AGC circuit. If the correction value is within the proper range, the AGC circuit controls the gain (gain) at the output stage of the AD converter while performing the lock (synchronization) processing in the PLL control, and the value is out of the proper range. If so, an unlock in the PLL control is detected, and a frequency shift can be prevented.

[Configuration of Embodiment: FIG. 1]
A frequency synthesizer according to an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a configuration block diagram of a frequency synthesizer according to an embodiment of the present invention.
As shown in FIG. 1, a frequency synthesizer according to an embodiment of the present invention includes a VCO 11, a frequency divider (NN) 12, an LPF (Low Pass Filter) 13, an AD converter (A / D) 14, a reference clock generator 15, a DA converter (D / A) 22, a voltage output unit 23, an adder 24, and a field programmable gate array (FPGA). Remove 16, reverse rotation vector multiplication unit 17, phase time difference detection unit 18, adder 19, phase difference cumulative addition unit 20, loop filter 21, parameter output unit 25, and amplitude information detection unit 26 A filter 27 and a multiplier 28.
Here, the amplitude information detection unit 26, the filter 27, and the multiplier 28 constitute an automatic gain control circuit (AGC circuit).

The VCO 11 is a voltage controlled oscillator that oscillates at a desired frequency (450 MHz to 1000 MHz) using the input from the adder 24 as a control voltage.
The frequency divider (NN) 12 divides the output of the VCO 11 into 1 / NN based on the frequency division value (NN) input from the outside, and outputs it to the LPF 13.

The LPF 13 is a filter that allows a low frequency to pass through the signal divided by the frequency divider 12.
The AD converter 14 samples the signal from the LPF 13 with a 40 MHz (fs) clock from the reference clock generator 15 to convert the signal from analog to digital, and outputs it to the carrier remove 16 of the FPGA.

  The DA converter 22 converts the control signal adjusted and controlled by the FPGA from digital to analog. The signal voltage from the DA converter 22 is 0 to 0.85V.

The voltage output unit 23 outputs a voltage based on the voltage value from the parameter output unit 25, and is configured such that the output voltage rises linearly to a predetermined voltage over time, for example.
The adder 24 corrects the voltage output from the voltage output unit 23 with the control signal output from the DA converter 22 and outputs the corrected voltage as a control voltage to the VCO 11.

  The basic function of the FPGA is to detect a phase difference by comparing a rotation vector at a desired output frequency (set frequency) with a rotation vector of a signal from the AD converter 14, and based on the phase difference, the VCO 11 A control signal for controlling the oscillation frequency is generated.

  The carrier remove 16 performs quadrature detection using a 4 MHz sine wave signal on the sine wave signal specified by the digital signal from the AD converter 14, and generates a frequency signal specified by the digital signal of the AD converter 14. This is means for extracting a rotation vector V that rotates at a frequency that is the difference between the frequency and the frequency of the sine wave signal used for detection.

The reverse rotation vector multiplication unit 17 multiplies the rotation vector V by the reverse rotation vector V ′ output from the parameter output unit 25.
The phase time difference detector 18 detects a phase difference for each sampling time based on the rotation vector V decelerated in the reverse rotation vector multiplier 17. This phase difference becomes a value corresponding to the frequency of the decelerated rotation vector V. Further, when the phase difference becomes zero, the phase time difference detection unit 18 detects a lock in the PLL and outputs a lock detection signal to the outside.

The adder 19 subtracts the value of the fine adjustment frequency for approaching the desired oscillation frequency obtained in advance from the output of the phase time difference detector 18 and outputs the phase difference.
The phase difference accumulator 20 accumulates and outputs the output from the adder 19 for a predetermined time. The phase difference accumulating unit 20 includes a filter, and sets damping to an optimum value.
The carrier remove 16, the reverse rotation vector multiplication unit 17, the phase time difference detection unit 18, the adder 19, the phase difference cumulative addition unit 20, and the parameter output unit 25 correspond to the phase comparison unit described in the claims. Yes.

  The loop filter 21 generates data for controlling the VCO 11 based on the cumulative addition value from the phase difference cumulative addition unit 20 and outputs the data as a control signal. The reason why the loop filter 21 is controlled based on the cumulative addition value is to stabilize the output of the loop filter 21.

  The parameter output unit 25 multiplies a frequency division value (NN) and a reverse rotation vector as frequency parameters so that the frequency is obtained as an output of the VCO 11 based on the input frequency setting information (information on a desired oscillation frequency). The reverse rotation vector V ′ to the unit 17, the fine adjustment frequency to the adder 19, and the voltage value to the voltage output unit 23 are calculated, and the above parameters and the like are output at the calculated timing. The reverse rotation vector V ′ is calculated based on the rotation vector V and the frequency setting information. The parameter output unit 25 may read various parameters in advance in a table or the like.

The amplitude information detection unit 26 receives the output from the reverse rotation vector multiplication unit 17, calculates the real part I and the imaginary part Q of the rotation vector by calculating I ² + Q ² , and obtains the result from the calculation result (amplitude information). The corrected AGC value is output to the filter 27. Based on the amplitude information, a correction value in the AGC circuit is obtained.

Further, the amplitude information detecting unit 26 has a controllable input amplitude range, an unlock detecting means is provided inside, and a threshold value (a value of amplitude information at which PLL control does not operate normally) is set. The unlock detection means determines whether or not the value of the input amplitude exceeds the threshold value, and when it exceeds, detects and outputs an unlock detection signal, and performs an unlock process that does not synchronize.
Although the unlock detection is performed using the amplitude information value, the unlock detection may be performed using an AGC correction value obtained based on the amplitude information.

The filter 27 outputs the gain to the multiplier 28 with a characteristic that allows appropriate automatic gain control with respect to the amplitude information obtained by the amplitude information detector 26.
The multiplier 28 multiplies the output (gain) from the filter 27 by the output from the AD converter 14 and outputs the result to the carrier remove 16. The multiplication of the gain in the multiplier 28 is adjusted so that the amplitude information is always constant.

Next, the characteristic part in this frequency synthesizer is demonstrated concretely.
In this frequency synthesizer, although not shown, the unlock detection means in the amplitude information detection unit 26 monitors the value of the amplitude information, and these values are values in a specific range (preset range value = PLL). It is determined whether or not the value is within a range in which control does not operate normally. When the value is within a specific range, it is detected as unlocked.
The unlock detection means may be provided in the amplitude information detection unit 26, but may be provided independently in the FPGA, or may be provided in another control circuit in the FPGA.

  Thus, in this frequency synthesizer, if the input level to the AD converter 14 fluctuates, is the unlock detection means within the range where the PLL control does not operate normally for the input level to the AD converter 14? Is determined based on the value of the amplitude information obtained by the amplitude information detection unit 26, and unlock detection is performed when the PLL control is within a range where the PLL control does not operate normally.

  In this frequency synthesizer, for example, the maximum value or the minimum value of the value input to the filter 27 is monitored from the value of the amplitude information obtained by the amplitude information detection unit 26, and the maximum value does not cause the PLL control to operate normally. When the value is equal to or greater than a specific value of 1, or when the minimum value is equal to or less than a second specific value that does not cause the PLL control to operate normally, unlock is detected.

  That is, when the output signal level of the AD converter 14 is in a preset range (a range in which the PLL control is not normally operated), the frequency synthesizer detects that the signal is unlocked and detects an alarm (alarm sound). An alarm display may be output).

  According to this frequency synthesizer, when the input level to the AD converter 14 exceeds the normal operation range of the PLL control, unlock detection is performed, and the occurrence of frequency deviation can be prevented.

  The present invention is suitable for a frequency synthesizer that can prevent occurrence of frequency deviation by preventing a situation in which PLL control does not operate normally when the input level to the A / D converter changes.

  DESCRIPTION OF SYMBOLS 1 ... VCO, 2 ... Frequency divider, 3 ... Reference oscillation circuit, 4 ... A / D converter, 5 ... Phase comparator, 6 ... Digital filter, 7 ... D / A converter, 8 ... Analog filter, 11 ... VCO, 12 ... frequency divider, 13 ... LPF, 14 ... AD converter, 15 ... reference clock generator, 16 ... carrier remover, 17 ... reverse rotation vector multiplier, 18 ... phase time difference detector, 19 ... adder 20 ... Phase difference cumulative addition unit, 21 ... Loop filter, 22 ... DA converter, 23 ... Voltage output unit, 24 ... Adder, 25 ... Parameter output unit, 26 ... Amplitude information detection unit, 27 ... Filter, 28 ... multiplier

Claims (3)

A voltage controlled oscillator that oscillates a frequency signal according to the input control voltage; and
A frequency divider for dividing the frequency signal;
An AD converter for analog / digital conversion of the divided signal;
A phase comparator that detects a phase difference by comparing phases of the analog / digital converted signal and the sine wave signal and outputs a phase difference signal corresponding to the phase difference;
A loop filter for removing high-frequency noise in the phase difference signal;
A DA converter for digital / analog conversion of the phase difference signal from which the noise has been removed,
The phase comparator includes, as an automatic gain control circuit comprises a multiplier in the subsequent stage of the AD converter, and the amplitude information detector that detects amplitude information for controlling the gain of the multiplier, the amplitude information A frequency synthesizer comprising: an unlock detection means for monitoring an unlock value when the value falls within a specific range; and a means for detecting an alarm by detecting the unlock .   The frequency synthesizer according to claim 1, wherein an alarm sound is output as the alarm detection.   2. The frequency synthesizer according to claim 1, wherein an alarm display is output as alarm detection.

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