KR200157538Y1 - Phase locked loop circuit with not-controlling vco - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

A voltage controlled oscillator of a phase control loop circuit.

2. The technical problem the invention is trying to solve

The present invention provides a phase control loop circuit having an unregulated voltage controlled oscillator for automatically adjusting the free running frequency.

3. Summary of solution of design

Phase detection means for comparing and detecting a phase of an input signal to be processed and a reference frequency; Voltage controlled oscillation means for generating the reference frequency; N dividing means for dividing the reference frequency by N to generate N dividing frequency; System frequency generating means for generating a system frequency; M dividing means for dividing the system frequency by M to generate an M dividing frequency; An enable frequency generator for inputting the M divided frequency and the N divided frequency to generate an enable frequency; A counter enabled by the enable frequency to generate a counting signal; And an oscillation frequency output means for generating an oscillation frequency corresponding to the counting signal and outputting the oscillation frequency corresponding to the counting signal as an analog value.

4 . Important uses of the devise

It is used in the voltage controlled oscillator of the phase control loop circuit.

Description

Phase Control Loop Circuit with Unregulated Voltage Controlled Oscillator

1 is a block diagram of a voltage controlled oscillator in a conventional phase control loop circuit.

2 is a block diagram of an exemplary unregulated voltage controlled oscillator according to the present invention.

3 is a block diagram of another example voltage-free voltage controlled oscillator according to the present invention.

4 is an operation waveform diagram of each part according to the present invention.

FIG. 5 is a diagram showing the configuration of the ROM table shown in FIG.

TECHNICAL FIELD The present invention relates to an analog phase locked loop circuit, and more particularly, to a phase controlled loop circuit having a voltage controlled oscillator that automatically adjusts a free running frequency. .

In general, the phase control loop circuit includes a phase detector, a loop filter, and a voltage controlled oscillator. The phase detector compares the signal to be processed with the output of the voltage controlled oscillator. The loop filter determines the operating band of the phase control loop circuit and removes unwanted signals from the output of the phase comparator. The output of the loop filter is a low frequency component near DC. The voltage controlled oscillator controls the output of the oscillation frequency in response to the DC output of the loop filter.

A diagram showing the configuration of a voltage controlled oscillator of a conventional phase control loop circuit is shown in FIG.

Referring to FIG. 1, the phase detector 10 compares an input signal IS to be processed with a phase of an output of the voltage controlled oscillator 30. The low pass filter 20 low pass filters the output of the phase detector 10 to generate a low pass signal. The voltage / current converter 31 of the voltage controlled oscillator 30 converts the low-frequency signal into an oscillation current and inputs it to the oscillator 32. The oscillator 32 generates an oscillation frequency corresponding to the oscillation current. The amplifier 33 amplifies and outputs the oscillation frequency. On the other hand, since the voltage controlled oscillator 30 of the phase control loop circuit generates an oscillation frequency mainly by using the charge and discharge time of the capacitor, a significant error occurs between the design value and the result value. Therefore, to reduce this error, the oscillation frequency is adjusted using the variable resistance VR. This oscillation frequency is generated by adjusting the variable resistor VR in a state in which the input signal IS of the phase detector 10 is blocked. In this adjustment process, as the band of the input signal IS of the phase detector 10 becomes far from the band of the free running frequency of the voltage controlled oscillator 30, the detection range of the phase control loop circuit becomes narrower and the input signal is detected. This problem becomes impossible.

Accordingly, an object of the present invention is to provide a phase control loop circuit having an unregulated voltage controlled oscillator for automatically adjusting the free running frequency.

Here, the free running frequency represents the frequency generated by the center voltage of the inputtable voltage of the voltage controlled oscillator. That is, it represents the frequency when no output is output from the phase detector.

Hereinafter, a detailed description of a preferred embodiment of the present invention will be described with reference to the accompanying drawings.

First, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals have the same reference numerals as much as possible even if displayed on different drawings. In addition, in the following description, many specific details such as components of a specific circuit are shown, which will not only be provided to help a more general understanding of the present invention, but also that the present invention can be implemented without specific details. It will be obvious to those skilled in the art. And in describing the present invention, if it is determined that the detailed description of the related known function or configuration may obscure the subject matter of the present invention, the detailed description thereof will be omitted.

2 is a block diagram of a phase control loop circuit having an example unregulated voltage controlled oscillator according to the present invention. The following description will be made in the test mode of the phase control loop circuit. Here, the test mode of the phase control loop circuit indicates a state in which the input signal does not exist or is forcibly removed from the phase detector before the phase control loop circuit is operated. That is, it shows the ready state for fixing the free running frequency of the voltage controlled oscillator.

Referring to FIG. 2, the phase detector 10 compares the phase of the input signal IS and the phase f of the output of the unregulated voltage controlled oscillator (VCO) 130. The low pass filter 20 performs low pass filtering on the output of the phase detector 10 and inputs it to one end of the adder 140. The adder 140 inputs the output of the low pass filter 20 and the output of the digital / analog converter 80, which are not described, to the other side and adds them.

The unregulated voltage controlled oscillator 130 is provided with an analog-to-digital converter, and generates an oscillation frequency corresponding to the output value of the adder 140 and outputs it as a digital oscillation frequency signal f. At this time, since the PLL Test mode in which the input signal does not exist in the phase detector 10, the digital oscillation frequency signal may be fixed to a specific value. The oscillation frequency f is converted into a pulse signal having a 50% duty between high and low by the analog-to-digital converter. The N divider 40 divides the digital oscillation frequency signal f by M and outputs the result as f / N. The waveform diagrams of the digital oscillation frequencies f and f / N are shown in FIG. As shown in the drawing, the f / N is composed of a pulse signal having a high and low period of a period larger than the digital oscillation frequency f. The enable unit 50 inputs the f / N, and also synchronizes the f / N to ft / m described later for an easy counting operation at the counter 60, and an edge at the f / N. Outputs the counter enable signal. As a result, the counter 60 performs a counting operation on the ft / m to be described later as soon as the counter enable signal is active.

On the other hand, the crystal oscillator 90 generates a system frequency ft. The m divider 100 divides the system frequency ft by m and outputs the ft / m. In this case, when the enable signal is input, the counter 60 performs a counting operation on the ft / m. In this case, the counting period of the counter 60 may be operated only in the high section or the low section of f / N of FIG. 4B. Because the counter 60 counts the period of f / N, for example, even if only the high period of the period of f / N of FIG. 4B is counted, the period of f / N can be estimated and the digital oscillation is performed. This is because the frequency f can also be estimated.

4C shows an example in which the counter 60 performs a counting operation on the ft / m input to the high section of the f / N according to an embodiment of the present invention.

As shown, the counting time period for the ft / m during the high period of f / N can be represented by the following equation (1).

(Equation 1)

Counting time period for ft / m = n × 1 / ft

Here, n is a counting value of the counter 60 during the counting time period for the ft / m.

Therefore, one period of f / N can be estimated by the following equation (2).

(Equation 2)

Therefore, the frequency of f / N can be estimated by the following formula (3).

(Equation 3)

Therefore, the frequency of f can be estimated by the following formula (4).

(Equation 4)

The ROM table 70 stores a value corresponding to the error voltage or error current information of the unregulated voltage controlled oscillator 130 to be compensated by inputting the counting value, and corresponds to the counting value of the counter 60. Print the value. The digital-to-analog converter 80 outputs the output value of the ROM table 70 as an analog value and inputs it to the other side of the adder 140. As a result, the unregulated voltage controlled oscillator 130 automatically adjusts the digital oscillation frequency f in response to the output of the adder 140.

On the other hand, the method of selecting the division ratios N and m can be determined as follows.

That is, since the counter 60 is a k-bit counter and its counting capability is 2 ^k , the ft / d during the high period of f / N when the target digital oscillation frequency f passes through the N divider 40 is designed. The division ratio N can be determined such that the counting value for m is 2 ^k-1 .

The system frequency ft may be selected to a value close to an integer multiple of the design target value f among high frequency clocks used in the system. For example, if the target digital oscillation frequency f according to the embodiment of the present invention is 4.3218 MHz in a 1x compact disc player, a system clock 16.9344 MHz close to f x 4 = 17.28 MHz can be selected. The division ratio m may be 1 or 2, and may be frequency multiplication such as 0.5 or 0.25.

For example, suppose that the design target f is 4.3218 MHz and the selected system clock ft is 16.9344 MHz, for example, for an EFM PLL in a double speed comeback disc player. When the division ratio N is 64, if the counting value of the counter 60 of the phase control loop circuit according to the embodiment of the present invention is 126, the estimated f value may be estimated by referring to Equation 4 below. It can be represented by Equation (5).

(Equation 5)

In the ROM table 70 according to an embodiment of the present invention, when the counter value is 126, a value corresponding to the difference between the currently estimated f value and the design target value f may be preset and stored by experiment.

On the other hand, the minimum adjustable frequency unit of the phase control loop circuit according to an embodiment of the present invention May represent how the output of the unregulated voltage-controlled oscillator 130 may change when the counter value changes by one. The minimum adjustable frequency unit of the phase control loop circuit can be expressed by the following equation (6).

(Equation 6)

The oscillation frequency f of the unregulated voltage-controlled oscillator 130 is in a state where the controller 110 is ready to fix the free running frequency, after a predetermined time or the counting value of the counter 60 falls within a preset error. Similarly, if it is determined that the adjustment is appropriate, the control unit 110 may instruct the enable unit 50 and the counter 60 to hold the current counting value. Alternatively, the controller 110 may turn off the enable unit 50 and the counter 60 to operate a normal state of the phase control loop.

3 is a block diagram of a phase control loop circuit having another unregulated voltage controlled oscillator according to the present invention.

Referring to FIG. 3, the method of counting the counter 60 is the same as the operation of the counter 60 shown in FIG. That is, when the counter enable signal is input from the enable unit 50, the counter 60 performs a counting operation on ft / m output from the m divider 100. In this case, the enable unit 50 inputs the ft / m and is synchronized with the ft / m to generate a counter enable signal at the edge of f / N.

Meanwhile, in FIG. 3, the digital signal processor 120 is present to process the output value of the low pass filter 20 of the phase control loop circuit shown in FIG. The digital signal processor 120 stores a value corresponding to the error of the unregulated voltage controlled oscillator 130, and outputs a value corresponding to the output value of the counter 60 in the test mode of the voltage phase control loop circuit. do.

5 is a diagram showing the configuration of the ROM table shown in FIG.

Referring to FIG. 5, when the counting value is n ₀ +1, the oscillation amount of the unregulated voltage controlled oscillator is insufficient, and the data is increased by d ₁ . And if n ₀ -1, the output of the unregulated voltage controlled oscillator shows oscillation fast, and decelerates by d ₁ .

As described above, the present invention provides an unregulated voltage controlled oscillator that automatically adjusts a free running frequency, and has an advantage of ICizing a phase control loop circuit.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the embodiments described, but should be defined by the equivalents of the utility model registration claims described below and equivalents thereof.

Claims (2)

In the phase control loop circuit, Phase detection means for comparing and detecting a phase of an input signal to be processed and a reference frequency; A low pass filter residue connected to the phase detection means and low pass filtering the phase compared output value; Voltage controlled oscillation means for receiving the low-filtered output value and generating the reference frequency; N dividing means for dividing the reference frequency by N to generate N dividing frequency; System frequency generating means for generating a system frequency; M division means for generating M division frequency by M division of the system frequency; Counter enable generating means for generating a counter enable signal by inputting the N division frequency; A counter for generating a counting signal by performing a counting operation on the M division frequency when the counter enable signal is input; An oscillation frequency output means for storing a value corresponding to an error of the voltage controlled oscillation means and outputting an error oscillation frequency corresponding to the counting signal; Digital / analog conversion means for outputting the oscillation frequency as an analog value; And adding means for inputting and adding the analog value and the low-pass filtered value to generate an addition signal. In the phase control loop circuit, Phase detection means for comparing and detecting a phase of an input signal to be processed and a reference frequency; Voltage controlled oscillation means for generating the reference frequency; N dividing means for dividing the reference frequency by N to generate N dividing frequency; System frequency generating means for generating a system frequency; M division means for generating M division frequency by M division of the system frequency; Counter enable generating means for inputting the N division frequency to generate a counter enable signal; A counter for generating a counting signal by performing a counting operation on the M division frequency when the counter enable signal is input; And a oscillation frequency output means for generating an error oscillation frequency corresponding to the counting signal and outputting the analog oscillation frequency, the value corresponding to the error of the voltage controlled oscillation means.