JPH0548453A - Frequency synthesizer - Google Patents

Abstract

PURPOSE:To realize the frequency synthesizer synchronously with an object frequency at a high speed whose operation is attained with small power consumption. CONSTITUTION:The configuration of a reference frequency generating means 1 in the frequency synthesizer of this invention is provided with a phase accumulator 3 integrating a frequency data K from a data input circuit 2 and giving the result of calculation to a ROM 4 as its address, the ROM 4 giving a waveform data to be stored to a D/A converter 5 according to the address, the converter 5 converting the waveform data into an analog waveform and a band pass filter 7 extracting one of higher harmonics outputted from the converter 5. Thus, a reference frequency furef is switched by switching a frequency data K thereby switching an output frequency fout generated by the frequency synthesizer and it is possible to set the reference frequency fref far higher than an inter-channel interval.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer used for a local oscillator of a wireless communication device.

[0002]

2. Description of the Related Art In the field of conventional wireless communication, for example, when a TDMA (time division multiple access) system or an intermittent transmission / reception system is adopted, a frequency synthesizer used in these systems is used until it synchronizes with a target frequency. There is a demand for a short period of time, operation with a small amount of power, and the like.

FIG. 5 shows, for example, Japanese Patent Laid-Open No. 63-296522.
The conventional direct digital
Phase locked loop (abbreviated as PLL) using synthesizer (abbreviated as DDS) Frequency synthesizer (DD)
3 is a block diagram showing a configuration of an S-PLL frequency synthesizer). In the figure, 2 is a data input circuit, 3 is a phase accumulator, 4 is a ROM, and 5 is a D.
/ A converter, 6 is a reference oscillator, 8 is a phase comparator, 9
Is a loop filter, 10 is a voltage controlled oscillator, 11 is a frequency divider, 12 is a low-pass filter, and 13 is a DDS.

FIG. 6 is a diagram showing the relationship between the frequency spectrum of the reference frequency generated by the DDS and the low-pass filter characteristic of the low-pass filter in the DDS-PLL frequency synthesizer of FIG.

Next, the operation of the conventional DDS-PLL frequency synthesizer will be described. The reference oscillator 6 generates a clock frequency f _c . The phase accumulator 3 is a counter having a bit length L, and uses the frequency data K (word length L) from the data input circuit 2 as a reference oscillator 6.
There integrating every 1 / f _c of the generated clock frequency f _c. The value accumulated by the phase accumulator 3 is given to the ROM 4 as an address, and the ROM 4 outputs sine wave waveform data. This waveform data is D / A
The converter 5 converts the analog waveform of the frequency f _DA , and then the low pass filter 12 removes harmonics to obtain the reference frequency f _ref . The division cycle 11 divides the output of the voltage controlled oscillator 10 by an integer N to generate a frequency divider output having a frequency f _D. The phase comparator 8 compares the frequency f _D of the frequency divider output of the frequency divider 11 with the phase of the reference frequency f _ref, and outputs a voltage proportional thereto as a phase comparison signal. The loop filter 9 takes out the low-frequency component of the phase comparison signal from the phase comparator 8, supplies this to the voltage control oscillator 10 as a frequency control voltage, changes the oscillation frequency of the voltage control oscillator 10, and thereby the frequency divider. The frequency f _D of the frequency divider output of 11 is changed in phase. The PLL is constructed in this way.

[0006] At this time, the output frequency f _{ou t} is frequency DDS13 is generated conventional DDS-PLL frequency synthesizer is generated, i.e. becomes N times the reference frequency f _ref, the output frequency f _out is the register length of the phase accumulator 3 L And the frequency data K can be determined as shown in the following equation. f _out = f _c · N · K / 2 ^L

[0007] Without being bound by channel spacing Unlike normal PLL, the reference frequency f _{re f} high it can be set. Therefore, the natural frequency ω _n of the loop can be increased, and the operation of the loop can be speeded up, so that the target frequency can be synchronized at high speed.

[0008]

DISCLOSURE OF THE INVENTION The conventional DDS described above
-The PLL frequency synthesizer is configured as described above, and when the loop is operated at high speed, the DDS1
The reference frequency f _ref , which is the frequency at which 3 is generated, must be increased. Therefore, it is necessary to make the clock frequency f _c generated by the reference oscillator 6 higher than or equal to the reference frequency f _ref generated by the DDS 13, but for that purpose, the high-speed D / A converter 5 and the like must be used. As a result, there is a problem that the power consumed by the DDS 13 becomes very large.

The present invention has been made to solve the above problems, and one of the harmonics of the output generated by the D / A converter of the reference frequency generating means is extracted and used as the reference frequency. It is an object of the present invention to provide a frequency synthesizer that suppresses the operating speed of the D / A converter and reduces the power consumption.

[0010]

A frequency synthesizer according to the present invention is a phase accumulator which integrates frequency data from a data input circuit into a structure of a reference frequency generating means for generating a reference frequency and gives the value as an address to a ROM. A ROM for giving the waveform data stored according to the address to the D / A converter, a D / A converter for converting the waveform data into an analog waveform, and a reference among the harmonics output by the D / A converter. It is configured by a bandpass filter that extracts only the frequency band used as a frequency, and lowers the frequency of the output generated by the D / A converter without lowering the reference frequency generated by the reference frequency generating means.

The frequency synthesizer according to the present invention is
One of the harmonics of the output generated by the D / A converter in the reference frequency generating means is extracted by a bandpass filter, and the extracted frequency is used as the reference frequency, so that the clock frequency of the D / A converter is suppressed low. As it is, it is possible to obtain a high-frequency reference frequency, which allows the frequency synthesizer to synchronize with the target frequency at high speed while keeping the power consumption low.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a frequency synthesizer which is an embodiment of the present invention. In the figure, 1 is a reference frequency generating means, 2 is a data input circuit, 3 is a phase accumulator, 4 is a ROM, 5 is a D / A converter,
6 is a reference oscillator, 7 is a band pass filter, 8 is a phase comparator, 9 is a loop filter, 10 is a voltage controlled oscillator, 1
1 is a minute cycle.

FIG. 2 is a diagram showing the frequency spectrum of the output of the D / A converter in the frequency synthesizer of FIG.
3 is a diagram showing the frequency spectrum of the bandpass filter in the frequency synthesizer of FIG. 1, and FIG. 4 is a diagram showing the frequency spectrum of the reference frequency generated by the reference frequency generating means in the frequency synthesizer of FIG.

Next, the operation of the frequency synthesizer according to the embodiment of the present invention will be described. In the frequency synthesizer shown in FIG. 1, the phase comparator 8, the loop filter 9, the voltage controlled oscillator 10, and the division period 11 are the same as those shown in FIG.
It is equivalent to the conventional example shown in FIG. The reference frequency generating means 1 comprises a data input circuit 2, a reference oscillator 6, a phase accumulator 3, a ROM 4, a D / A converter 5 and a bandpass filter 7. Of these, reference oscillator 6, phase accumulator 3, ROM 4, D
The A / A converter 5 is equivalent to the conventional example shown in FIG. The frequency characteristic of the frequency f _DA of the analog waveform output by the D / A converter 5 is as shown in FIG. Thus harmonics of a frequency f _DA, by the band-pass filter 7 having a frequency characteristic of the band width B, as shown in FIG. 3, taken out as a reference frequency f _ref as shown in FIG. 4, the reference frequency f _ref It is input to the phase comparator 8, and the reference frequency f _ref and the frequency divider 1 are input by the phase comparator 8.
The phase of the frequency divider output of 1 is compared with the frequency f _D, and a voltage proportional thereto is output from the phase comparator 8 as a phase comparison signal, whereby the PLL is configured.

Here, the output frequency f _out generated by the frequency synthesizer is expressed by the following equation, and the frequency data K to be output by the data input circuit 2 is determined. f _ref = f _c −f _c · K / 2 ^L f _out = (f _c −f _c · K / 2 ^L ) · N

[0016] When the variable range width of the frequency of the output frequency f _^out △ f ^out, and a variable range width that must change the frequency of the reference frequency _{f re} f △ and _{f ref, △ f ref = △} f _out / N, and the bandwidth B of the bandpass filter 7 also becomes B = Δf _out / N.

Therefore, when considering the relationship between the frequency spectrum of the reference frequency f _ref generated by the DDS 13 of the conventional example and the low-pass filter characteristic of the low-pass filter 12 as shown in FIG. Judge
It can be seen that in the frequency synthesizer of the present invention, it is possible to generate the same reference frequency f _ref as in the above-mentioned conventional example at a lower clock frequency f _c .

As described above, the reference frequency generating means 1 of the frequency synthesizer of the present invention is the D / A converter 5
It is possible to obtain a reference frequency f _ref that is about twice as high as the clock frequency f _{c of}

[0019]

As described above, according to the frequency synthesizer of the present invention, the configuration of the reference frequency generating means for generating the reference frequency is such that the frequency data from the data input circuit is integrated and the value is stored in the ROM as an address. A phase accumulator to be given, a ROM for giving waveform data stored according to the address to the D / A converter, a D / A converter for converting the waveform data into an analog waveform, and a harmonic wave output by the D / A converter. Since it is configured by a bandpass filter that extracts only the frequency band used as the reference frequency from the inside, by generating the reference frequency using the bandpass filter, D
Since the clock frequency of the A / A converter can be lower than the reference frequency, the clock frequency according to the present invention can be made lower than the clock frequency of the same reference frequency as that of the conventional example of this kind. It is possible to obtain a frequency synthesizer that can be operated with smaller power and that operates at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a frequency synthesizer which is an embodiment of the present invention.

2 is a diagram showing a frequency spectrum of an output of a D / A converter in the frequency synthesizer of FIG.

3 is a diagram showing a frequency spectrum of a bandpass filter in the frequency synthesizer of FIG.

4 is a diagram showing a frequency spectrum of a reference frequency generated by a reference frequency generating means in the frequency synthesizer of FIG.

FIG. 5 is a block diagram showing a configuration of a conventional DDS-PLL frequency synthesizer.

6 is a diagram showing a relationship between a frequency spectrum of a reference frequency generated by DDS and a low pass filter characteristic of a low pass filter in the DDS-PLL frequency synthesizer of FIG.

[Description of Reference Signs] 1 reference frequency generating means 2 data input circuit 3 phase accumulator 4 ROM 5 D / A converter 6 reference oscillator 7 band pass filter 8 phase comparator 9 loop filter 10 voltage controlled oscillator 11 frequency divider 12 low pass filter 13 DDS (Direct Digital Synthesizer)

Claims (1)

[Claims] 1. A reference frequency generating means for generating a reference frequency, a voltage controlled oscillator for outputting a frequency corresponding to a control voltage, a frequency divider for dividing the output of the voltage controlled oscillator, and a frequency divider for the frequency divider. A frequency synthesizer configured by comparing a phase of an output with a phase of an output of the reference frequency generating means, and a phase comparator controlling the voltage controlled oscillator through a loop filter, wherein the reference frequency generating means is a data input circuit. And a reference oscillator, an arithmetic circuit for arithmetically operating the frequency data from the data input circuit in correspondence with the cycle of the output of the reference oscillator, and outputting waveform data stored in advance based on the arithmetic result by the arithmetic circuit. Storage device, D / A converter for converting the output of the storage device into an analog waveform, and harmonics of the output of the D / A converter Frequency synthesizer, characterized by being configured by a band-pass filter for extracting an output.