JPS62146020A - Pll frequency synthesizer - Google Patents

Abstract

PURPOSE:To raise the response speed and reduce the phase noise by adding a voltage corresponding to a desired frequency to give it to a voltage controlled oscillator and giving required frequency division ratio data to a programmable counter. CONSTITUTION:An adding amplifier 7 adds the output of a low pass filter 2 and that of a DA converter 11 and amplifies the addition result, and the output is given to a voltage controlled oscillator 3. The first code converter 8 converts the output code of a latch 9 to such frequency division ratio code that a programmable counter 4 is a frequency divider corresponding to a set frequency. There is little difference between this operation and the operation that the set frequency is outputted to the voltage controlled oscillator 3 from the outside of a system through the DA converter 11 at a switching time. The output voltage of the low pass filter is not quickly changed and its time constant is made larger, and the phase jitter of the output frequency is reduced. The timing of setting (switching) of the output frequency is synchronized with that of phase comparison of the programmable counter 4 to minimize the disturbance.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention is a PLL (PHASE LOCKEDLO
This invention relates to a frequency synthesizer using OP), and particularly relates to improving response characteristics when switching frequencies.

(Prior Art) A PLL frequency synthesizer has been well known in the past, and its basic configuration is shown in FIG.

In the figure, 1 is a phase detector, 2 is a low-pass filter,
3 is a voltage controlled oscillator, and 4 is a 1/N frequency division programmable counter.

The voltage controlled oscillator 3 outputs a signal of a certain frequency, and the frequency increases or decreases depending on the output voltage of the phase detector 1 applied via the low-pass filter 2. Programmable counter 4 reduces the output frequency of voltage controlled oscillator 3 by 1/N.
Divide the frequency into The phase detector 1 uses the reference clock (RIEF
, CLOCK) and the frequency signal given by the programmable counter 4 (!! difference in lead and lead)
Outputs a signal (voltage signal) related to.

In such a configuration, the phase difference between the reference standard [1] and the output signal of the programmable counter 4! , and as a result, the front′・pressure tl
A stable frequency rout (N times ν1+0) can be obtained from the I-controlled generator 3. (Problem to be solved by the invention) In such a circuit, the frequency division ratio is 1/N. The response characteristic of the output frequency fout when changing is almost determined by the characteristics of the low-pass filter, and generally the low-pass filter is the only response-related parameter that can be adjusted by the designer.

On the other hand, when considering the phase noise of the output frequency (short-term stability of the output frequency), the speed of response time and phase jitter are in a reciprocal relationship; the faster the response time, the more phase jitter increases, and the slower the response time becomes. This will reduce the phase jitter.

For this reason, if the response of the low-pass filter is made faster in order to increase the response speed, phase jitter will increase. Therefore, there has been a problem in that it is difficult to realize a PLL frequency synthesizer with fast response speed and low phase jitter.

In view of these points, an object of the present invention is to provide a PLL frequency synthesizer that has a high response speed and low phase noise.

(Means for Solving the Problems) The present invention to solve the above problems divides the output frequency of the voltage controlled oscillator into 1/N using a programmable counter,
The phase difference between this frequency-divided output and the reference clock is detected by a phase detector, and an output voltage corresponding to the phase difference is applied to the voltage-controlled oscillator via a low-pass filter to control the output frequency, thereby controlling the voltage. In a PLL frequency synthesizer that obtains a signal with a frequency N times that of a reference clock from an oscillator, a voltage corresponding to a desired frequency related to the characteristics of the voltage controlled oscillator is generated in synchronization with the timing of phase comparison in a phase detector. is added to the output of the low-pass filter and given to the voltage controlled oscillator, and also includes means for giving the programmable counter the frequency division ratio data necessary to obtain the desired frequency.

(Example) Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, parts equivalent to those in FIG. 3 are given the same reference numerals. In the figure, 5 is a reference oscillator using a crystal or the like, 6 is a frequency divider, and 7
is a summing amplifier, 8 is a first code converter, 9 is a latch,
10 is a second code converter, and 11 is a DA converter.

A frequency divider 6 divides the output frequency of the reference oscillator 5 into a clock having a desired reference frequency. The output frequency of the voltage controlled oscillator 3 is N times that of this clock, but the response time, which will be described later, is never shorter than one cycle of this frequency.

The latch 9 receives the externally applied frequency e! lSetting data (
The bit length code corresponding to the set frequency width and variable frequency step) is latched and supplied to the code converter 8°1o. The timing at which the latch 9 takes in data is synchronized with the output pulse of the programmable counter.

The second code converter 10 converts the output code of the latch 9 into a code according to the characteristics of the voltage controlled oscillator 3.
The DA converter 11 converts the output of the code converter 10 into an analog signal and outputs it.

A summing amplifier 7 adds and amplifies the output of the low-pass filter 2 and the output of the DA converter 11. This output is given to the voltage controlled oscillator 3. The output of the DA converter 11 changes according to the set frequency as described above, but this change is caused by the code converter so that the output of the voltage controlled oscillator 3 becomes the desired frequency (the set frequency or a frequency close to it) at the time of switching. 10.

The first code converter 8 converts the output code of the latch 9 into a code with a frequency division ratio such that the programmable counter 4 becomes a frequency divider corresponding to the set frequency.

The operation in such a configuration will be described with particular attention to the features of the present invention. As shown in FIG. 2(C), the frequency setting data given from the outside changes at any timing, but the data is changed by the fout/N pulse (FIG. 2(C)) output from the programmable counter 4.
The signal is taken into the latch 9 at the timing of b)) and converted by the code converters 8 and 10. The DA converter 11 converts the output code of the code converter 10 into an analog signal (FIG. 2(E)), so that the output of the summing amplifier 7 is as shown in FIG.
), the voltage controlled oscillator 3 changes stepwise so that the set frequency or a frequency close to it is output. At the same time, a code is set in the programmable counter 4 by the code converter 8, and its frequency division ratio is set. A feedback loop operates at such a set value, and an output frequency corresponding to the frequency setting data is obtained from the voltage controlled oscillator 3.

According to such a configuration, it is possible to apply a voltage that is not much different from outputting the set frequency to the voltage controlled oscillator 3 from outside the system via the DA converter 11 at the time of switching, so even immediately after switching, the phase The phase difference between the input signals to the detector 1 is small, and the output voltage of the low-pass filter 2 does not change suddenly. Therefore, the time constant of the low-pass filter 2 can be made large, and the phase jitter of the output frequency can be kept small.

In addition, since the timing of setting (switching) the output frequency is synchronized with the timing of phase comparison of the programmable counter 4, the disturbance given to the system can be minimized, and the smaller the disturbance, the closer to the steady state it will be. Steady state (locked state) with short response time (for several clock cycles)
become.

Note that the reference oscillator 5 and the frequency divider 6 may not be provided internally, but may be arranged externally so that only the reference clocks REF and CLOCK are received. Further, the code converters 8 and 10 may be of the type that uses a ROM (read only memory) and performs conversion using a code conversion table.

(Effects of the Invention) As described above, the present invention has the following effects.

A) Conventional PLL frequency synthesizers require several tens of periods of the reference clock until the output becomes stable when switching the output frequency, but with the present invention, only a few cycles are required and a fast response can be obtained.

B) In the conventional filter, when achieving a fast response, the time constant of the low-pass filter was reduced to some extent, making it susceptible to noise and having large phase jitter, but in the present invention, the response is provided by input from outside the loop. PLL with high spectral purity, which allows the time constant of the low-pass filter to be kept large, is resistant to noise, and has low phase jitter.
A frequency synthesizer can be realized.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention, FIG. 2 is a time chart for explaining the operation, and FIG. 3 is a diagram not showing an example of a conventional PLL frequency synthesizer. 1... Phase detector 2... Low pass filter 3
... Voltage III control oscillator 4 ... Programmable counter 5 ... Reference oscillator 6 ... Frequency divider 7 ... Disturbing amplifier 8 ... First code converter 9 ... Latch 10 ...Second code converter 11...DA converter

Claims (1)

[Claims] The output frequency of the voltage controlled oscillator is divided into 1/N by a programmable counter, the phase difference between the divided output and the reference clock is detected by a phase detector, and the output voltage according to the phase difference is passed through a low-pass filter. In a PLL frequency synthesizer, the output frequency of the voltage controlled oscillator is controlled by applying it to the voltage controlled oscillator to obtain a signal with a frequency N times that of the reference clock from the voltage controlled oscillator. In synchronization with the voltage controlled oscillator, a voltage corresponding to the desired frequency related to the characteristics of the voltage controlled oscillator is added to the output of the low-pass filter and applied to the voltage controlled oscillator. A PLL frequency synthesizer comprising means for providing frequency division ratio data.