JP2829180B2 - Frequency synthesizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer used for a local oscillator of a radio communication device.

[0002]

2. Description of the Related Art FIG. 2 shows, for example, JP-A-63-296522.
FIG. 1 is a configuration diagram showing a conventional frequency synthesizer using a phase locked loop (PLL) disclosed in Japanese Patent Application Laid-Open Publication No. H10-110,026. In the figure, reference numeral 1 denotes a direct digital synthesizer (hereinafter abbreviated as DDS) for outputting a reference signal having a frequency _fref .

[0003] DDS1, the data input circuit 2 for generating frequency setting data K of word length L, the reference oscillator 3 for generating a clock signal of a frequency f _c, the data input circuit 2
Is integrated in synchronization with the clock signal from the reference oscillator 3, and the integrated value is added to the address signal A.
A phase accumulator 4 to be output as D; a storage device 5 for reading out the stored waveform data FD in accordance with the address signal AD from the phase accumulator 4 in synchronization with the clock signal from the reference oscillator 3; From a reference oscillator 3 in synchronization with a clock signal, and a D / A converter 6 for outputting the converted signal as a reference signal having a frequency _FDDS .

Reference numeral 1c denotes a phase-locked loop (PLL), and reference numeral 8 denotes a frequency f _ref from the DDS1.
(= F _DDS ) and a frequency- _divided signal of frequency f _{o obtained} by _dividing the output signal of frequency f _OUT output from the voltage-controlled oscillator described later by a fixed frequency divider 16 having a frequency division number NF. A phase comparator which compares the phases and outputs a phase comparison error signal S _E proportional to the phase difference;
Loop filter for outputting a frequency control voltage V _fc takes out low-frequency components of the _E, 10 is controlled its oscillation frequency according to a frequency control voltage V _fc, in the voltage controlled oscillator for generating an output signal having a predetermined frequency f _out is there.

Next, the operation will be described. The phase accumulator 4 integrates the frequency setting data K from the data input circuit 2 for each oscillation period 1 / fc of the clock signal generated by the reference oscillator 3, and outputs the integrated value to the storage device 5 as an address signal AD. .

The storage device 5 stores waveform data forming a sine wave waveform for each address. The waveform data is read out from the storage device 5 at a predetermined read cycle from each address signal AD from the phase accumulator 3. By reading, sine wave waveform data FD having a frequency corresponding to the period is read. The digital / analog conversion of the waveform data FD by the D / A converter 5 generates an analog sine wave of a predetermined frequency, and the frequency f _DDS (= f
_ref ) as a reference signal.

The reference signal having the frequency f _ref is supplied to one input side of the phase comparator 8, and the output signal of the voltage control comparator 10 is divided by the fixed frequency divider 16 to the other input side of the phase comparator 8. The divided signal is input and the phases of both signals are compared.

[0008] The phase comparator 8 inputs a phase comparison error signal S _E as a phase comparison result to the loop filter 9. The low-pass loop filter 9 extracts the low-frequency component of the phase comparison error signal S _E and _applies it to the voltage-controlled oscillator 10 as the frequency control voltage _Vfc . The voltage controlled oscillator 10 changes its oscillating frequency in accordance with the input frequency control voltage _{Vfc, that} is, an error, and generates an output signal having a predetermined frequency _fout at its output side.

[0009] The output signal generated at this time phase period circuit I _c frequency fout becomes NF times the reference signal frequency fDDS to occurrence of DDS1, its frequency is phase Achim regulator 4 register length L from the data input circuit 2 of From frequency setting data K, fDDS = (fc · K) / 2 ^L
Therefore, unlike the ordinary PLL, the reference frequency _fref can be set high without being restricted by the channel interval. Therefore, the natural frequency ω of the loop
Since n can be set high and the operation of the loop can be performed at high speed, it is possible to synchronize with the target frequency at high speed.

[0010]

When a conventional frequency synthesizer PLL is operated at high speed, the frequency at which DDS is generated must be increased, and a high-speed D / A converter or the like must be used. D /
Since the A converter consumes a large amount of power, the power consumed by the DDS becomes very large, and there is a problem that the power consumption of the entire synthesizer also becomes large.

The present invention has been made to solve such a problem, and an object of the present invention is to provide a frequency synthesizer which can be operated with lower power consumption and operates at high speed.

[0012]

A frequency synthesizer according to the present invention converts a waveform data called from a storage device at a predetermined cycle into an analog signal, and separates a D / A converter and a clock signal which are output as a first reference signal. A frequency divider that divides the frequency and outputs it as a second reference signal;
Reference signal generating means having a selection device for selecting a reference signal, a voltage-controlled oscillator for generating an output signal having a frequency corresponding to the control voltage, and dividing a signal from the voltage-controlled oscillator to output a divided signal A variable frequency divider, a switch unit for controlling the output of the frequency-divided signal from the variable frequency divider and the reference signal output from the selector to a phase comparator, and a phase comparison error signal output from the phase comparator. A phase locked loop having a loop filter for smoothing and outputting the control voltage to the voltage controlled oscillator; and opening control of the switch unit when detecting that the frequency of the output signal of the voltage controlled oscillator is synchronized with a target frequency. And a control unit that switches the selection device to selectively output the second reference signal, and then controls the closing of the switch unit.

[0013]

In the present invention, at the time of frequency switching, the frequency dividing number of the variable frequency divider is set to a predetermined frequency dividing number, and the target frequency which is more than the set frequency dividing number is set by the D / A converter. By generating the reference signal of a certain frequency, the frequency synthesizer is synchronized with the target frequency at high speed. After the frequency switching is completed, the control section opens the switch section to open the PLL, and the control voltage to the voltage controlled oscillator is held at the output of the loop filter so that the frequency of the output signal of the voltage controlled oscillator becomes the target frequency. Hold, during which the reference signal is switched to the second reference signal from the frequency divider, and the frequency division number of the variable frequency divider of the phase locked loop is set to the frequency division number corresponding to the frequency of the second reference signal. Then, the operation of the D / A converter is stopped, and the switch section is closed again to operate the phase-locked loop, so that the D / A converter operates only at the time of frequency switching.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram of the frequency synthesizer according to the present embodiment. In the figure, the same reference numerals as those in FIG. 2 indicate the same or corresponding parts. In Fig, 1a is a clock of a frequency f _c from the reference signal the first reference signal of DDS, 7 as generator frequency f _DDS output from D / A converter 5 or the reference oscillator 6, according to this embodiment selection device frequencies by dividing the output frequency divider for generating a signal to select and output one of the second reference signal f _f, 12 will divides the frequency f _c of the clock signal, that amount the frequency signal is a frequency divider for outputting a second reference signal having a frequency f _f.

Reference numeral 1b denotes a phase locked loop circuit as a PLL according to the present embodiment, and reference numeral 11 denotes a variable divider for _dividing the frequency f _{out of the} output signal output from the voltage controlled oscillator 10 and outputting a frequency- _divided signal of frequency f _v. divider, 13 a reset device to reset the variable frequency divider 1 1, 14 when the frequency of the output signal of the voltage controlled oscillator 10 has reached the target frequency, the input of the PLL with an open loop to the phase comparator 8 Switch section for shutting off 1
A control unit 5 controls switching of the selection device 7 and the switch unit 14 when detecting that the frequency f _out of the output signal of the voltage controlled oscillator 10 has reached the target frequency _fe .

Next, the operation will be described. At the time of frequency switching, the selection device 7 converts the first reference signal of the frequency f _DDS output from the D / A converter 5 to the reference frequency f _ref.
Is input to one input side of the phase comparator 8 through the switch 14 as a true reference signal. Also, the phase comparator 8
The the other input divided signal of the frequency f _V outputted from the variable frequency divider 11 is inputted, the voltage controlled oscillator with respect to the reference signal from DDS1a as in the prior art by performing a phase comparison between the signals The phase of the output signal is synchronized, and an output signal having a frequency f _out matching the target frequency f _e is generated at the output side of the voltage controlled oscillator 10.

In this embodiment, like the conventional frequency synthesizer, the first frequency f _DDS of the frequency f _DDS is
Also in DDS mode for capturing a reference signal as a true reference signal of the reference frequency f _ref, the target frequency f _e is first
Is set by the reference signal frequency f _DDS, from the following equation and the target frequency f _e, the frequency setting data K is determined.

F _e = f _c · N · K / 2 ^L (1) where f _c : frequency of clock signal N: frequency dividing number fixed by variable frequency divider 11 K: Frequency setting data L: Word length of frequency data

[0019] After synchronizing frequency f _out of the output signal of the voltage controlled oscillator 10 by DDS mode to the target frequency f _e, true of the second reference signal a reference frequency f _ref of the frequency f _f from the frequency divider 12 frequency settings in divider mode for taking as a reference signal is performed by dividing number of the variable frequency divider 11, the dividing number N _V with respect to the target frequency f _e is determined from the following equation.

F _e = f _f · N _V (2) where _ff is the frequency of the second reference signal output from the frequency divider 12, and N _V is set by the variable frequency divider 11. It is a division number. Further, channel spacing f _d of the synthesizer from the equation (2) becomes f _d = f _f.

Next, the operation in the frequency divider mode after the completion of the frequency switching will be described based on the above equations. Control unit 1
5 takes in the output signal of the voltage controlled oscillator 10 and, when judging that the frequency f _out has reached the target frequency _fe in the DDS mode, first sets the switch section 14 to an open state to open the PLL into an open loop.

As a result, the voltage control oscillator 10 receives the frequency control voltage _Vfc from the loop filter 9 storing the output voltage, and holds the oscillation frequency at the target frequency _fe . Switch unit as a reference signal of the second reference signal a reference frequency f _ref of the frequency f _f control unit 15 that is being output a selection device 7 from the switching frequency divider 12 while holding the target frequency f _e Add to 14.

Furthermore, if the reference frequency f _ref is changed to a frequency f _f, (2) As is clear from equation in order to obtain a target frequency f _e, which was observed in this frequency f _f, the variable frequency divider 11 Is set to N _V, and the operation of the D / A converter 5 is stopped. After that, the reset device 13 resets the variable frequency divider 11 in accordance with the timing of the reference frequency f _ref to reset the phase, then closes the switch unit 14 by the control unit 15 and operates the PLL again, The frequency f _out of the output signal of the voltage controlled oscillator 10 is synchronized with the reference frequency f _ref to obtain the target frequency f _e .

[0024]

As described above, according to the present invention, the D / A converter which converts the waveform data called from the storage device at a predetermined cycle into an analog signal and outputs it as the first reference signal, and the clock signal are frequency-divided. A frequency divider for outputting as a second reference signal, a reference signal generating means having a selection device for selecting the second reference signal, and an output signal having a frequency corresponding to the control voltage; A voltage-controlled oscillator, a frequency divider that divides a signal from the voltage-controlled oscillator and outputs a frequency-divided signal, and compares a phase of the frequency-divided signal from the variable frequency divider with a reference signal output from the selection device. A phase-locked loop having a switch unit for controlling output to a voltage comparator, a loop filter for smoothing a phase comparison error signal output from the phase comparator, and outputting as a control voltage to the voltage-controlled oscillator; When it is detected that the frequency of the output signal of the oscillator is synchronized with the target frequency, the switch unit is controlled to be opened, the selector is switched, the second reference signal is selectively output, and then the switch unit is closed. Since the D / A converter is used only at the time of frequency switching, it is possible to operate with lower power and obtain a frequency synthesizer that operates at high speed. To play.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of a frequency synthesizer of the present invention.

FIG. 2 is a configuration diagram showing a conventional frequency synthesizer.

[Explanation of symbols]

1a Direct digital synthesizer (DD
S) 1b Phase locked loop (PLL) 3 Reference oscillator 5 Storage device 6 D / A converter 7 Selection device 8 Phase comparator 9 Loop filter 10 Voltage controlled oscillator 11 Variable frequency divider 12 Frequency divider 14 Switch section

Claims (1)

(57) [Claims] 1. A D / A converter for converting waveform data called from a storage device at a predetermined cycle and outputting the converted data as a first reference signal, and a D / A converter for dividing a clock signal and outputting the same as a second reference signal. A reference signal generating means having a frequency divider and a selection device for selecting the first or second reference signal; a voltage-controlled oscillator for generating an output signal having a frequency corresponding to the control voltage; A variable frequency divider that divides a signal and outputs a frequency-divided signal, a switch unit that controls output of a frequency-divided signal from the variable frequency divider and a reference signal output from the selection device to a phase comparator, and A phase locked loop circuit having a loop filter for smoothing a phase comparison error signal output from a phase comparator and outputting the phase comparison error signal as the control voltage to the voltage controlled oscillator; A control unit for controlling the opening of the switch unit when detecting the synchronization with the frequency, switching the selection device to selectively output the second reference signal, and thereafter controlling the closing of the switch unit. A frequency synthesizer.