JPH1022827A - Analog/digital conversion device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an A/D (analog/digital) conversion device which can generate a clock with high-frequency accuracy and also can reduce the product cost. SOLUTION: An A/D converter 1 converts an analog audio signal A into a digital signal D. At the same time, the sampling is performed by means of a stable 1st clock CLK1 of a crystal oscillator 21. Then the signal D, received from the converter 1, is inputted to a rate converter 6 by the timing of the CLK1. Then the converter 6 converts and outputs the sampling rate of the signal D by a 2nd clock CLK2 that is given from a voltage control oscillator 50 and synchronous with the CLK1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to analog / digital (hereinafter referred to as "A") corresponding to a plurality of sampling frequencies.
/ D ").

[0002]

2. Description of the Related Art Conventionally, as this type of A / D converter, for example, there is a technique shown in FIG. This A / D converter corresponds to three sampling frequencies of 48 KHz, 44.1 KHz, and 32 KHz, and includes an A / D conversion circuit 1 and a voltage controlled crystal oscillator 2 controlled by a CPU 9.
And a phase locked loop section 3.

An A / D conversion circuit 1 is a circuit for converting an input analog audio signal A into a digital signal D.
A clock CLK for sampling is supplied from the voltage controlled crystal oscillator 2. The voltage controlled crystal oscillator 2 includes a crystal oscillator 21 that oscillates a clock CLK that is 512 times 48 kHz, a crystal oscillator 22 that oscillates a clock CLK that is 512 times 44.1 kHz, and 32 KH.
crystal oscillator 2 that oscillates a clock CLK 512 times as large as z
The clock CLK of any frequency is selected by switching the switch SW.

The phase locked loop section 3 is a section for comparing the phases of the clock CLK from the voltage controlled crystal oscillation section 2 and a 27 MHz clock RC synchronized with the input reference video signal. 32, a phase comparator 33 and a low-pass filter 34 (denoted as “LPF” in the figure) 34. As a result, the clock CLK from the voltage controlled crystal oscillator 2 is
The frequency is divided into 1 / M (where M = integer) and RC is divided by the frequency divider 3
In 2, the frequency is divided by 1 / N (where N = integer), and each is input to the phase comparator 33. Then, the output of the phase comparator 33 is phase-voltage-converted by the low-pass filter 34, and the crystal oscillator 2 of the voltage-controlled crystal oscillator 2 is
1 to 23 to form a synchronous loop.

The CPU 9 controls the switch SW of the voltage-controlled crystal oscillator 2 and the frequency dividers 31 and 32 of the phase-locked loop unit 3. The CPU 9 switches the switch SW in accordance with the sampling frequency. , "M" are set. Specifically, when the crystal oscillator 21 is selected, (N, M) is set to (1125, 1024), and a clock of 24 KHz is input to the phase comparator 33. When the crystal oscillator 22 is selected, (N,
M) is set to (1875,1568) and 14.4K
Hz clock is input to the phase comparator 33. further,
When the crystal oscillator 23 is selected, (N, M) is changed to (3
375, 2048) and an 8 KHz clock is input to the phase comparator 33.

FIG. 4 shows a circuit for generating a 27 MHz clock RC synchronized with an input reference video signal. In FIG. 4, reference symbol RV is an input reference video signal, and this input reference video signal RV is
The signal is input to the synchronization separation circuit 100, and the synchronization separation circuit 10
The horizontal synchronization signal separated by 0 is supplied to the phase comparator 101. Reference numeral 102 denotes a voltage-controlled crystal oscillator, which outputs a 27-MHz clock RC to the frequency divider 32 in FIG. 3 and the frequency divider 104 in FIG. The clock RC is divided by the frequency divider 104 into 1 / J (where J = integer), and then supplied to the phase comparator 101, where
1 is input to the low-pass filter 105. Thereby, in the low-pass filter 105,
The phase-voltage-converted signal is input to the voltage-controlled crystal oscillator 102 to form a synchronous loop. Note that the frequency divider 1
04 is set by the CPU 9, and "J" is set to the input reference video signal RV.
It is set according to the method of. Specifically, in the case of the 525 system, “J” is set to “1716” and 15.7
A clock of 34 KHz is supplied to the phase comparator 101.
In the case of the 625 system, "J" is set to "1728" and a clock of 15.625 KHz is supplied to the phase comparator 101.

[0007]

However, the above-mentioned conventional A / D converter has the following problems. A / D
In the conversion device, the characteristics of the clock CLK supplied to the A / D conversion circuit 1 greatly affect the A / D conversion performance of the A / D conversion circuit 1. Therefore, it is necessary to supply the clock CLK having good frequency accuracy and no jitter component to the A / D conversion circuit 1 as the clock CLK. However, the conventional A / D converter has a configuration in which three crystal oscillators 21 to 23 are provided in the voltage controlled crystal oscillator 2 and any one of the clocks CLK oscillated by these crystal oscillators 21 to 23 is selected. Therefore, the clocks CLK oscillated from the three crystal oscillators 21 to 23 interfere with each other, and the clock CLK with low frequency accuracy is supplied to the A / D conversion circuit 1. Further, since three expensive crystal oscillators 21 to 23 are used, the product cost is high.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and provides an analog / digital converter capable of generating a clock with high frequency accuracy and reducing the cost of a product. It is intended to be.

[0009]

In order to solve the above-mentioned problems, an A / D converter according to the present invention comprises a first clock generator for generating a first clock having a specific frequency; A / D converter for converting an analog signal into a digital signal using the frequency of the first clock as a sampling frequency, and a second clock generator capable of generating a plurality of second clocks having different frequencies in synchronization with the first clock And a rate converter that inputs the digital signal from the A / D converter at the timing of the first clock and outputs the digital signal at the timing of the second clock.

According to the present invention, the A / D converter converts an analog signal into a digital signal using the frequency of the first clock generated by the first clock generator as a sampling frequency. The digital signal is input at the timing of the first clock in the rate converter, and is output at the timing of the second clock generated by the second clock generator.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a block diagram showing an A / D converter according to a first embodiment of the present invention. For easy understanding, the same elements as those shown in FIG. As shown in FIG.
This A / D converter includes an A / D conversion circuit 1 as an A / D conversion unit, a phase-locked loop unit 3 and a voltage controlled crystal oscillation unit 4 as a first clock generation unit, and a second clock generation unit. , A rate converter 6 as a rate converter, and a CPU 7.

The A / D conversion circuit 1 is a circuit for converting an analog audio signal A into a digital signal D, and uses the frequency of the first clock CLK1 from the voltage controlled crystal oscillator 4 as a sampling frequency.

The voltage controlled crystal oscillating section 4 is a section for generating a first clock having a specific frequency, and comprises only a crystal oscillator 21. Thereby, the maximum frequency 4
A first clock CLK1 512 times 8 KHz is input from the crystal oscillator 21 to the A / D conversion circuit 1, the phase locked loop unit 3, and the phase locked loop unit 5. Phase locked loop 3
Has the same configuration as that shown in FIG.
Is set to 1/1024, and the division ratio of the frequency divider 32 is set to 1/1125. As a result, the first clock CLK1 from the voltage-controlled crystal oscillator 4 is frequency-divided by the frequency divider 31 into 1/1024, and is input to the phase comparator 33 as a 24-kHz clock. Also,
The 27 MHz clock RC synchronized with the input reference video signal RV (see FIG. 4)
The frequency is divided by 1125, and is input to the phase comparator 33 as a 24 KHz clock. Then, the output of the phase comparator 33 is phase-voltage-converted in the low-pass filter 34 and is input to the voltage-controlled crystal oscillation unit 4 to form a synchronous loop.

The phase-locked loop section 5 has a first clock CL
In synchronization with K1, a plurality of second clocks C having different frequencies
It is a portion that can generate LK2, and includes a voltage controlled oscillator 50, frequency dividers 51 and 52, a phase comparator 53, and a low-pass filter 54.

The voltage controlled oscillator 50 is an oscillator having a wide lock range and does not use a crystal. Dividers 51 and 5
2, the phase comparator 53 and the low-pass filter 54 constitute a phase-locked loop unit, and compare the phases of a second clock CLK2 from the voltage controlled oscillator 50 and a first clock CLK1 from the crystal oscillator 21. These are synchronized. Hereinafter, the frequency of 48 KHz is set to 512
The second clock CLK2 having the doubled frequency is simply referred to as “48 KH”.
The second clock CLK2 having a frequency of 512 times the frequency of 44.1 KHz is simply referred to as the "second clock CLK2 of 44.1 kHz," and the second clock CLK2 having a frequency of 512 times the frequency of 32 KHz. The second clock CLK2 is simply referred to as “the second clock CL of 32 kHz”.
K2 ". The frequency divider 51 is a device that frequency-divides the second clock CLK2 from the voltage controlled oscillator 50 into 1 / K (where K = integer) and inputs the frequency to the phase comparator 53. First clock CLK1 from crystal oscillator 21
Is divided into 1 / L (where L = integer), and the phase comparator 5
3 is a device to be input. These division ratios 1 / K, 1 /
L is set by the CPU 7 according to the frequency of the second clock CLK2 output from the voltage controlled oscillator 50. Specifically, when (K, L) is set to (1, 1), the clock of 24.576 MHz is divided into frequency dividers 51 and 52.
Is input to the phase comparator 33, the output of the phase comparator 53 is phase-voltage-converted in the low-pass filter 54, and is input to the voltage-controlled oscillator 50 to form a synchronous loop. As a result, the voltage controlled oscillator 50
Hz second clock CLK2 is output. Also,
When (K, L) is set to (147, 160), 0.
A 1536 MHz clock is input from the frequency dividers 51 and 52 to the phase comparator 33, and the voltage controlled oscillator 50
A second clock CLK2 of 4.1 KHz is output. Further, when (K, L) is set to (2, 3), 8.1
A 92 MHz clock is input to the phase comparator 33 from the frequency dividers 51 and 52, and the voltage controlled oscillator 50
The second clock CLK2 of z is output.

The rate converter 6 inputs the digital signal D from the A / D conversion circuit 1 at the timing of the first clock CLK1 from the crystal oscillator 21, performs a known rate conversion under the control of the CPU 7, and performs voltage control. The digital signal D at the timing of the second clock CLK2 from the oscillator 50
Is a device that outputs

Next, the operation of the A / D converter of this embodiment will be described. When the first clock CLK1 is oscillated from the crystal oscillator 21 and is input to the phase locked loop unit 3, a locked loop is formed. As a result, the first clock CLK1 is synchronized with the clock RC, phase-locked, and the 48 KHz first clock CLK1 is
The signals are output to the D conversion circuit 1, the phase locked loop unit 5, and the rate converter 6. When the first clock CLK1 is input to the A / D conversion circuit 1, the analog audio signal A is converted into a digital signal D using the frequency of the first clock CLK1 as a sampling frequency. On the other hand, when the first clock CLK1 is input to the frequency divider 52 of the phase locked loop unit 5, the first clock CLK1 is frequency-divided by the frequency divider 52 to 1 / L and output to the phase comparator 53. . The second clock CLK2 from the voltage controlled oscillator 50 is supplied to the frequency divider 51.
, And is output to the phase comparator 53. As a result, the output of the phase comparator 53 is input to the voltage controlled oscillator 50 via the low pass filter 54, and a synchronous loop is formed. As a result, the second clock CLK2 is synchronized with the first clock CLK1 to perform phase lock, and the second clock CLK2 having a frequency corresponding to the division ratios 1 / M and 1 / L is output from the voltage controlled oscillator 50. Become like That is, (K,
L) by (1,1), (147,160), (2,3)
48K corresponding to each
Hz, 44.1 KHz, 32 KHz second clock CL
K2 is output.

The second clock CLK2 and the first clock CLK1 are input to the rate converter 6. As a result, the rate converter 6 controlled by the CPU 7 converts the A / D
The digital signal D from the conversion circuit 1 is converted to a first clock CLK
1 and output at the timing of the second clock CLK2. That is, when the second clock CLK2 of 44.1 KHz is input to the rate converter 6, the digital signal D having the sample rate of 48 KHz × 512 is converted into the sample rate of 44.1 KHz × 512. Output from the rate converter 6.

As described above, according to the A / D converter of this embodiment, the oscillator that supplies the clock of the sampling frequency to the A / D conversion circuit 1 has only one crystal oscillator 2.
Therefore, the first clock CLK1 supplied from the crystal oscillator 21 to the A / D conversion circuit 1 does not receive interference from other oscillators. As a result, the first clock CLK1
However, since it has high frequency accuracy and does not include a jitter component due to interference, the A / D conversion circuit 1 can achieve stable and accurate A / D conversion. Also,
The second clock CLK2 from the voltage controlled oscillator 50
Synchronizing with the clock CLK1, keeping the frequency ratio constant,
Since the rate conversion is performed, it is not necessary to use a highly accurate and expensive device such as a crystal oscillator as the voltage controlled oscillator 50. That is, the A / D of the present embodiment
In the converter, only one crystal oscillator 21 and an inexpensive voltage controlled oscillator 50 can be used as oscillators, so that product cost can be reduced.

(Second Embodiment) FIG. 2 shows a second embodiment of the present invention.
FIG. 2 is a block diagram illustrating an A / D converter according to the embodiment. The same elements as those shown in FIG. 1 will be described with the same reference numerals. The A / D converter of the present embodiment is different from the A / D converter of the first embodiment in that the rate converter 6 is not provided and the rate conversion is performed by the CPU.

In FIG. 2, reference numeral 8 denotes a CPU, and an input side of the CPU 8 is an interface 81 (in the figure,
The I / F is connected to the output side of the A / D conversion circuit 1, and the output side of the CPU 8 is connected to the interface 82. The interface 81 is a port that reads the digital signal D at the timing of the first clock CLK1 and outputs the digital signal D to the CPU 8 on the clock of the CPU 8. The CPU 8 has an A / D converter as a functional block. The CPU 8 converts the rate of the digital signal D received from the interface 81 by software processing and outputs the converted signal to the interface 82. The interface 82 is a CPU
8 is converted to a second clock C
LK2 is a port for output. Other configurations,
Since the operation and effect are the same as those of the first embodiment, the description is omitted.

[0022]

As described in detail above, the A of the present invention
According to the / D conversion device, the oscillation unit that supplies the clock of the sampling frequency to the A / D conversion unit is only one first clock generation unit.
The first clock supplied to the D conversion unit does not receive interference from another oscillator. As a result, the first clock has high frequency accuracy and does not include a jitter component due to interference.
There is an effect that D conversion can be achieved. Also, since the second clock from the second clock generator is configured to perform the rate conversion by synchronizing the second clock with the first clock, a highly accurate and expensive device such as a crystal oscillator is used as the second clock generator. There is also an effect that the cost of the product can be reduced without using.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an A / D conversion device according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating an A / D converter according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing an A / D converter according to a conventional example.

FIG. 4 is a block diagram of a circuit that generates a clock synchronized with an input reference video signal.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... A / D conversion circuit, 3 ... Phase locked loop part, 5 ... Phase locked loop part, 6 ... Rate converter, 7 ... CPU, 21 ... Crystal oscillator,
50: voltage controlled oscillator, A: analog audio signal, CLK1: first clock, CLK2
... Second clock, D ... Digital signal.

Claims (1)

[Claims] A first clock generating unit that generates a first clock having a specific frequency; and an analog / digital converter that converts an analog signal into a digital signal using the frequency of the first clock as a sampling frequency.
A digital conversion unit; a second clock generation unit that can generate a plurality of second clocks having different frequencies in synchronization with the first clock; and a digital signal from the analog / digital conversion unit, An analog / digital conversion device, comprising: a rate converter that inputs at the timing of (2) and outputs at the timing of the second clock.