JPH1188156A - Pll circuit for generating clock signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL circuit for generating a clock signal where a phase shift of the clock signal is improved without the need for adjustment of a phase control range of the clock signal even when the operating condition is subject to change. SOLUTION: The PLL circuit consisting of a phase comparator 1, an LPF 2, a VCO 3 and a frequency divider 4 generates a clock signal fck. The PLL circuit consisting of a phase comparator 8, an LPF 9, a VCO 10 and a frequency divider 11 generates a clock signal fsub. A shift register 6 shifts an output of the frequency divider 4 based on the clock signal fsub. An output of the frequency divider 4 is given to an input terminal (a) of a changeover circuit 7 and an output of the shift register 6 is given to an input terminal (b). The changeover circuit 7 selects either of the signals selectively and provides an output of a compared signal to the phase comparator 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generating PL for generating a clock locked to an input reference signal.
The present invention relates to an L circuit, and particularly to a clock generator for generating a clock locked to a horizontal synchronization signal, which is suitable for use in a display device or a television receiver which performs digital signal processing by inputting a signal from a personal computer (personal computer). It relates to a PLL circuit.

[0002]

2. Description of the Related Art An analog personal computer signal output from a personal computer is converted into a digital signal by an A / D converter or the like, and subjected to digital signal processing required for display on a display device such as a display device or a television receiver. , On the display device. The conversion of an analog signal to a digital signal by the A / D converter is as follows.
This is performed by sampling an analog signal. At this time, it is necessary that the frequency and phase of the sampling clock be correctly matched with the input analog personal computer signal as the original signal.

For example, in the case of an SVGA standard personal computer signal, the number of display pixels is 800 (horizontal) × 600 (vertical). Since the total number of pixels in one horizontal period is 1056,
Sampling by the A / D converter is normally performed by a clock in which one horizontal period is locked to 1056 horizontal synchronization signals. At this time, if not only the clock frequency but also the phase of the clock does not properly match the data phase of the personal computer signal, correct data cannot be obtained, and the following problems occur.

If the clock frequency is not correct (one horizontal period is not 1056), characters and the like may be partially unclear or unstable. The clock frequency is correct,
If the clock phase is not appropriate, characters and the like become thinner as a whole, the hue changes, and data error-like noise occurs.

Now, here, a conventional clock generating PL is described.
The configuration and operation of an example of the L circuit will be described with reference to FIG.
FIG. 4 shows a PLL circuit which receives a video horizontal synchronization signal as a reference signal and obtains a clock locked to the horizontal synchronization signal.

In FIG. 4, one input terminal of a phase comparator 1 has a horizontal synchronizing signal (frequency Fref) as a reference signal.
) Is input, and a horizontal synchronous reproduction signal obtained as described later is input to the other input terminal. Phase comparator 1
Performs a phase comparison between the input horizontal synchronization signal and the input horizontal synchronization reproduction signal, and inputs a detection voltage (error signal) corresponding to the phase difference to a low-pass filter (LPF) 2. LP
F2 smoothes the output of the phase comparator 1 and outputs a control voltage.

The control voltage output from LPF 2 is input to voltage shift circuit 5. The voltage shift circuit 5 arbitrarily offsets the control voltage by a predetermined value, and inputs the offset to the voltage controlled oscillator (VCO) 3. The offset voltage by the voltage shift circuit 5 is externally controlled. The voltage shift circuit 5 is generally realized by a combination of differential amplifiers using transistors.

The VCO 3 has a control voltage input terminal, and the control voltage from the voltage shift circuit 5 is input to the control voltage input terminal. The VCO 3 oscillates according to the input control voltage and outputs a clock. This clock is input to the frequency divider 4, and the frequency divider 4 divides (ie, counts) the input clock. If the count value of the frequency divider 4 is N, the clock frequency Fck is given by Fck = N × Fref.

The frequency-divided output of the frequency divider 4 is input to the phase comparator 1 as the above-described horizontal synchronous reproduction signal (compared signal). In the PLL circuit configured as described above, when a voltage shift is applied by the voltage shift circuit 5, the phase comparator 1 generates an output voltage that cancels the shift voltage. , The phase of the reference pulse (horizontal synchronization signal) and the comparison pulse (horizontal synchronization reproduction signal) from the frequency divider 4 change relatively,
The phase of the clock output from the VCO 3 changes. As described above, the PLL circuit shown in FIG. 4 can obtain a clock locked to the horizontal synchronization signal, and can control the phase of this clock.

The voltage shift circuit 5 does not need to be provided in a normal PLL circuit that does not need to perform clock phase control.

[0011]

By the way, if the phase of the clock is generally changed in the range of 0 ° to 180 °,
The input analog PC signal can be sampled at the optimum phase. The shift voltage for controlling the phase of the clock changes according to the period of the reference pulse and the pulse width, or the frequency of the clock and the count number of the frequency divider 4.

Therefore, the shift voltages need to be individually set with high accuracy according to the operating conditions of the PLL circuit. Therefore, 0 ° to 180 ° corresponding to each mode (operating condition).
180 ° phase shift to achieve a phase shift of 180 °
The maximum value Vmax of the shift voltage for obtaining
For memory functions such as microcomputers,
It is necessary to store the maximum value Vmax for each operating condition.
Then, it is necessary to generate an arbitrary shift voltage in the range of the minimum value 0 to the maximum value Vmax for each mode.

As a result, in the PLL circuit shown in FIG.
Although phase control can be performed from the outside, it is necessary to obtain a preset value corresponding to each mode and store it in advance, so that there is a problem that adjustment work is involved and productivity is poor. In addition, a memory for storing the preset value is required, which increases the cost. Further, since the maximum value Vmax of the shift voltage varies depending on each mode, the control structure becomes complicated. This control is executed by the microcomputer program and D
When using the / A converter, the program becomes complicated.

The present invention has been made in view of such a problem, and it is not necessary to adjust the range of clock phase control even if the operating conditions change, and the clock phase shift can be improved. An object of the present invention is to provide a clock generation PLL circuit.

[0015]

According to the present invention, there is provided a clock generating PLL circuit for generating a clock locked to an input reference signal. A first phase comparator (1) for comparing the phase with the signal to be compared, and a first low-pass filter (2) for smoothing an output of the first phase comparator to obtain a first control voltage. , The first control voltage is input, and a first clock (fc c) corresponding to the first control voltage is input.
a first voltage-controlled oscillator for generating and outputting k) (3)
A first frequency divider for dividing the first clock (4)
A second phase comparator (8) for comparing the phases of the reference signal and the second signal to be compared; and a second phase comparator for smoothing an output of the second phase comparator to obtain a second control voltage. A second low-pass filter (9), a second voltage-controlled oscillator (10) to which the second control voltage is inputted, and which generates and outputs a second clock (fsub) corresponding to the second control voltage. A second frequency divider for dividing the second clock and inputting the divided second clock to the second phase comparator as the second signal to be compared.
A shift register (6) for shifting the output of the first frequency divider by the second clock; and inputting the output of the first frequency divider to one input terminal, And a switching circuit (7) for inputting the outputs of the above to the other input terminals and inputting the selective outputs of these inputs to the first phase comparator as the first signals to be compared. Another object of the present invention is to provide a clock generating PLL circuit.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a clock generation P according to the present invention will be described.
The LL circuit will be described with reference to the accompanying drawings. FIG.
FIG. 2 is a block diagram showing an embodiment of a clock generating PLL circuit according to the present invention. FIGS.
FIG. 5 is a timing chart for explaining the operation of the LL circuit.
In FIG. 1, the same parts as those in FIG. 4 are denoted by the same reference numerals.

In FIG. 1, one input terminal of the phase comparator 1 receives a horizontal synchronizing signal as a reference signal, and the other input terminal receives a compared signal obtained as described later. . The phase comparator 1 compares the phase of the input reference signal and the phase of the input signal to be compared, and outputs a detection voltage (error signal) corresponding to the phase difference to a low-pass filter (LPF) 2.
To enter. LPF2 smoothes the output of phase comparator 1,
Outputs control voltage. The control voltage output from the LPF 2 is input to a voltage controlled oscillator (VCO) 3.

The VCO 3 has a control voltage input terminal, and the control voltage from the LPF 2 is input to the control voltage input terminal. The VCO 3 oscillates according to the input control voltage and outputs a clock fck. This clock fck is input to the frequency divider 4, and the frequency divider 4 receives the input clock fck
Is divided by 1 / N (that is, counted).

The frequency-divided output of the frequency divider 4 is input to the input terminal a of the shift register 6 and the switching circuit 7. The output of the shift register 6 is input to the input terminal b of the switching circuit 7. The selective switching output of the switching circuit 7 is input to the phase comparator 1 as the above-described signal to be compared.

Further, one input terminal of the phase comparator 8 receives a horizontal synchronizing signal as a reference signal, and the other input terminal receives a compared signal obtained as described later. The phase comparator 8 compares the phase of the input reference signal with the phase of the input signal to be compared, and inputs a detection voltage (error signal) corresponding to the phase difference to a low-pass filter (LPF) 9. The LPF 9 smoothes the output of the phase comparator 8 and outputs a control voltage. The control voltage output from the LPF 9 is input to a voltage controlled oscillator (VCO) 10.

The VCO 10 has a control voltage input terminal, and the control voltage from the LPF 9 is input to the control voltage input terminal. The VCO 10 oscillates according to the input control voltage and outputs a clock fsub. This clock fsu
b is input to the frequency divider 11, and the frequency divider 4 divides the input clock by 1 / M (that is, counts). And
The divided output of the frequency divider 11 is used as a signal to be compared.
Is input to

The clock fsu output from the phase comparator 8
b is input to the shift register 6. The shift register 6 operates using the clock fsub as a driving clock. A phase selection signal is also input to the shift register 6,
The phase of the clock fck output from the VCO 3 is varied according to the phase selection signal.

Next, each operation when the switching circuit 7 selects the input terminals a and b will be described with reference to FIGS.

In FIG. 2, (A) is a horizontal synchronizing signal (reference signal) input to the phase comparator 1, and (B) is an input to the phase comparator 1 when the switching circuit 7 selects the input terminal a. The compared signal (C) is the clock fc output from the VCO 3 when the switching circuit 7 selects the input terminal a.
k and (D) show the output of the frequency divider 4 when the switching circuit 7 selects the input terminal a, (E) shows the output of the shift register 6, and (F) shows that the switching circuit 7 selects the input terminal b. The output of the frequency divider 4 at the time (G) indicates that the switching circuit 7 has the input terminal b.
Is selected, the clock f output from the VCO 3
ck is shown.

FIG. 3A shows the switching circuit 7.
The output of the frequency divider 4 when the input terminal b is selected,
(B) shows the state when V is selected when the switching circuit 7 selects the input terminal b.
A clock fck output from CO3, (C) is a clock fsub output from the VCO 10 when the switching circuit 7 selects the input terminal b, and (D) is a clock fsub when the switching circuit 7 selects the input terminal b. 3 shows a compared signal input to the phase comparator 1 (that is, the output of the shift register 6).

First, a switching signal SW from the outside gives
When the switching circuit 7 selects the input terminal a, the phase comparator 1, LPF2, VCO
3, frequency divider 4. The phase comparator 1 compares the reference signal shown in FIG. 2A with the compared signal shown in FIG. The clock fck from the VCO 3 and the output of the frequency divider 4 have the waveforms shown in FIGS. FIG.
The output of the frequency divider 4 shown in (D) becomes the compared signal input to the phase comparator 1.

On the other hand, according to the switching signal SW from the outside,
When the switching circuit 7 selects the input terminal b, the loop of the PLL circuit is constituted by the phase comparator 1, LPF2, VCO
3, a frequency divider 4 and a shift register 6. The shift register 6 is driven by a clock fsub generated by the VCO 10 and shown in FIG.

The phase comparator 8 compares the reference signal shown in FIG. 2A with the compared signal output from the frequency divider 11. The clock fsub from the VCO 10 is shown in FIG.
The waveform shown in FIG.

Here, the clock f generated by the VCO 10
sub is set to satisfy the following conditions. fck> fsub (1) fck ≠ n × fsub (n is an integer) (2)

For example, the cycle of the clock fck generated by the VCO 3 shown in FIG. 3B is 25 ns (frequency 40 MHz).
z), the period of the clock fsub generated by the VCO 10 shown in FIG. 3C is about 26.56 ns (frequency about 3
7.65 MHz), the VCO 10 and the frequency divider 11 are set. At this time, the clock fsub output from the VCO 10 is the clock fsub output from the VCO 3
ck is delayed by 22.5 ° for each clock.

For this reason, FIG.
The output of the frequency divider 4 shown in (A) is latched by the shift register 6 with the clock fsub. For example, the output shifted by two clocks is, as shown in FIG. ° The phase is delayed.

Thus, when the PLL circuit is locked, the output of the shift register 6 shown in FIG.
At the timing shown in (E), the output of the frequency divider 4 is
The timing shown in FIG. As a result, the clock fck output from the VCO 3 has the phase shown in FIG. This is because the phase of the clock fck shown in FIG.
° advanced.

That is, according to the present invention, the input terminal b is selected by the switching circuit 7 and the shift value of the shift register 6 is appropriately set by a phase selection signal input from the outside, thereby outputting from the VCO 3. The phase of the clock fck can be arbitrarily selected.

Incidentally, the PLL circuit of the present invention operates even if the condition of the above formula (1) is not satisfied. However, when the condition of the above formula (1) is satisfied, the operation and effect of the configuration of the present invention can be reduced. Demonstrate effectively. That is, the phase comparator 1, L
Even if the first PLL circuit constituted by the PF2, the VCO 3, and the frequency divider 4 is driven at the highest frequency, the phase comparator 8, L driven at a lower frequency is used.
By using the clock obtained from the second PLL circuit constituted by the PF 9, the VCO 10, and the frequency divider 11, the phase of the clock obtained from the first PLL circuit can be changed.

[0035]

As described above in detail, the clock generating PLL circuit of the present invention comprises a first phase comparator for comparing the phase of a reference signal with a phase of a first signal to be compared, A first low-pass filter that obtains a first control voltage by smoothing the output of the phase comparator;
A first voltage controlled oscillator that generates and outputs a first clock corresponding to the control voltage of the first clock, a first frequency divider that divides the first clock, a reference signal, a second signal to be compared, , A second low-pass filter that smoothes the output of the second phase comparator to obtain a second control voltage, and a second control voltage, A second voltage controlled oscillator that generates and outputs a second clock corresponding to the second control voltage, and divides the second clock and inputs the second clock to the second phase comparator as a second compared signal. A second frequency divider, a shift register that shifts an output of the first frequency divider by a second clock, and an output of the first frequency divider that is input to one input terminal. Outputs to the other input terminals, and selectively outputs these inputs to the first compared signal. And a switching circuit for inputting the signal to the first phase comparator. Therefore, even if the operating conditions change, there is no need to adjust the range of the phase control. The deviation from the phase of the sampling clock to be performed can be improved. Further, this configuration can be realized with a very simple circuit configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the present invention.

FIG. 3 is a timing chart for explaining the operation of the present invention.

FIG. 4 is a block diagram showing a conventional example.

[Explanation of symbols]

 1,8 Phase comparator 2,9 Low-pass filter 3,10 Voltage-controlled oscillator 4,11 Divider 6 Shift register 7 Switching circuit

Claims (2)

[Claims] 1. A clock generating PLL circuit for generating a clock locked to an input reference signal, comprising: a first phase comparator for comparing the phases of the reference signal and a first signal to be compared; A first low-pass filter that obtains a first control voltage by smoothing an output of the first phase comparator; and a first clock that receives the first control voltage and generates a first clock corresponding to the first control voltage A first voltage-controlled oscillator for dividing and outputting the first clock, a first frequency divider for dividing the first clock, and a second phase comparison for comparing the phases of the reference signal and a second signal to be compared A second low-pass filter that obtains a second control voltage by smoothing the output of the second phase comparator; and a second control voltage that is input to the second low-pass filter according to the second control voltage. A second voltage-controlled oscillator that generates and outputs two clocks; A second frequency divider that divides the second clock and inputs the second clock as the second signal to be compared to the second phase comparator; and outputs the output of the first frequency divider to the second A shift register that shifts according to the following clock; and an output of the first frequency divider is input to one input terminal, and an output of the shift register is input to the other input terminal. And a switching circuit for inputting the first compared signal to the first phase comparator.
circuit. 2. The method according to claim 1, wherein the frequency of the first clock is set to the second frequency.
2. The clock generation PLL circuit according to claim 1, wherein the frequency is set to be higher than the frequency of the second clock and not to be an integral multiple of the frequency of the second clock.