JPH0759052A - Automatic frequency tracking device - Google Patents

Abstract

PURPOSE:To obtain an automatic frequency tracking device revising an interpolation clock of a memory write clock signal generating IC of a time base collector used for correcting jitter for a VTR or the like. CONSTITUTION:The automatic frequency tracking device made into IC is provided with a phase comparator circuit 7 receiving a horizontal synchronizing signal obtained by separating an input video signal at a horizontal synchronizing separator circuit 6 and an output of a fixed 1/N frequency division counter 10 and with a clock generating circuit 9 applying a clock generated through the control of an oscillated frequency based on an output of the phase comparator circuit to the fixed 1/N frequency division counter 10. In order to insert clock signals of the same number for a horizontal synchronization period, a clock operation circuit 11 is provided with a changeover device 15 selecting and outputting a predetermined number of periods among inserted clocks of the outputs of 1/2, 1/4... frequency dividers 12, 13... connected in parallel with an output of the clock generating circuit 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic frequency tracking device in a write clock signal generating circuit of a time base collector (hereinafter referred to as TBC) used for jitter correction of a video tape recorder or the like.

[0002]

2. Description of the Related Art Conventional video tape recorders (hereinafter referred to as VT
Called R. ), A constant clock is always inserted in the interval of the horizontal synchronizing signal and the TBC is used for writing to the memory, etc., but the frequency of the clock signal generator automatically follows the horizontal synchronizing signal. A circuit as shown in FIG. 4 is known as an automatic frequency tracking device (hereinafter, referred to as AFC) for performing the operation.

In the AFC circuit shown in FIG. 4, a horizontal sync separation circuit 1 separates a horizontal sync signal from an input video signal and inputs it to a phase comparison circuit 2. On the other hand, the interpolated clock signal is generated by the clock generation circuit 4 and input to the 1 / N frequency division counter 5. The signal divided by 1 / N is input to the phase comparison circuit 2 and compared in phase with the input horizontal synchronizing signal. The phase difference detected by the phase comparison circuit 2 is input to the clock generation circuit 4 as an error component through the low-pass filter / amplification circuit (active filter) 3, and the clock frequency is controlled by the error component, so that one horizontal N clocks in the synchronization signal period, for example N =
If 6 is set, 6 clocks can be interpolated.

Most of the AFC circuits are integrated, and the 1 / N frequency dividing counter 5 is built in the integrated circuit as N having a fixed value. Therefore, when the number of clock interpolations is changed externally, for example, the NTS in the TBC is changed.
When the C method (910f _H ) is changed to the PAL method (908f _H ), the fixed integrated circuit cannot be used because the write clock frequency is different, and the inside of the integrated circuit must be changed.

[0005]

In view of the above problems, the present invention provides an AFC circuit which can change the number of interpolations by operating a clock input from the outside without changing the inside of the integrated circuit. It is in the point of providing.

[0006]

According to the present invention, a horizontal sync separation circuit for separating a horizontal sync signal from an input video signal, a horizontal sync signal separated by the horizontal sync separation circuit, and an output of a fixed frequency division counter are input. A phase comparison circuit for performing phase comparison, an oscillation frequency is controlled based on the output of the phase comparison circuit, and a clock generation means for supplying the generated clock to the fixed frequency dividing counter; and an output of the clock generation means. In the automatic frequency tracking device having a terminal, clock operating means for interpolating the same number of clocks in a horizontal synchronization section is provided between the clock generating means and the fixed frequency dividing counter, operating ^{means, 1/2 n (n = 1,2,3,} ··) connected in parallel with the dividing means are inserted into the dividing means and said parallel connected to the horizontal synchronization period black It and a switching means for switching outputs selectively dividing the clock of a predetermined number cycles of the click, or parallel connection the ^{2 n (n = 1,2,3, ··} ) and multiplying means, said The multiplying means connected in parallel is provided with a switching means for selectively multiplying a clock of a predetermined number of cycles among the clocks interpolated in the horizontal synchronization section and switching and outputting.

[0007]

1 is a block diagram of an embodiment of the present invention. In FIG. 1A, the horizontal sync signal is separated from the input video signal by the horizontal sync signal separation circuit 6,
It is input to the phase comparison circuit 7. On the other hand, although the clock signal is generated in the clock generation circuit 9, it is input to the 1 / N frequency division counter 10 via the clock operation circuit 11 described later.

The output of the 1 / N frequency division counter 10 is input to the phase comparison circuit 7, and the phase error component is detected. The detected phase error component passes through the low-pass filter / amplifier circuit (active filter) 8 and is taken out as the frequency control voltage of the clock generation circuit 9.

Next, the clock operating circuit 11 which is a feature of the present invention will be described below. Clock operation circuit 1
1 is configured as shown in (B) of FIG. 1 and the block diagram of FIG. 2 depending on the application. FIG. 1B shows an example of a clock operation circuit when the number of interpolated clocks is greater than N,
FIG. 2 shows an example of a clock operation circuit when the number of interpolated clocks is less than N.

First, a case where the number of interpolated clocks shown in FIG. 1B is greater than N and the number of interpolated signals is N + M will be described. In the clock operation circuit 11, the 1/2 dividers 12 and 1/4 that divide the clock generated by the clock generation circuit 9 and input to the clock input terminal.
The frequency divider 13 and the 1/8 frequency divider 14 ... Are respectively input to the 1/2 ⁿ frequency dividers (n = 1, 2, 3 ...) And the frequency-divided clocks are output. The input clock and the divided clock are input to the switch 15, and the switched clock is output and input to the 1 / N frequency division counter 10.

FIG. 5 shows a time chart when N = 6 and M = 2 when the clock operating circuit 11 is used. In the time chart, (a) is a horizontal synchronizing signal separated from an input video signal, (b) is a conventional clock when N = 6 is a clock generated by a clock generation circuit 9 before the clock operation. It is no different from the clock that the example occurs. (C) is a 1/2 divider 12 which divides the signal of the clock (b) before the operation into 1/2,
The clock divided by two is shown.

The operation of the clock operating unit 11 is
Here, the operation is performed by fixing the operation of “switching four cycles of the clock (b) before operation in one cycle of the horizontal synchronizing signal before hatching to the clock divided by ½”. A waveform as shown in (d) is obtained as a clock. This (d)
In the case of the waveform of, the four clocks immediately before the horizontal synchronization are switched by the above operation. Note that the four clocks immediately after horizontal synchronization may be switched by the above operation.

By the way, the basic operation of the AFC circuit is to automatically control the frequency of the clock so that the interpolation number N is constant, and in this case N = 6. When stabilized, the operation clock after AFC stabilization is 1
6 clocks including 2 clocks divided by 2 are generated, and a waveform as shown in (e) is obtained.

This AFC system must operate in a stable manner for 6 clocks, but the clock operating circuit 11
The clock generation circuit 9 (FIG. 1) generates eight clocks in one horizontal cycle by adding the 1/2 frequency division operation in (1) to the clocks after the operation as shown in (f).
Eight clocks are interpolated in one horizontal period, and N = 6 and M = 2 are achieved.

Generally, when the number of interpolations for M clocks is increased, it can be realized by replacing with 2M clocks of N clocks. However, at this time, N ≧
There is a limitation that it is impossible to replace with a divided clock of 2M, that is, half or more of the originally interpolated number.

Therefore, the present invention can be interpolated even under the condition of N <2M by performing the operation shown in the time chart of FIG. In FIG. 6, (a) is a horizontal synchronizing signal, (b) is the output of the 1/2 frequency divider 12, and (c) is 1/4.
This is the output of the frequency divider 13. When the operation in the clock operation circuit 11 is fixed to the operation of "switching a 1/4 frequency-divided clock in one cycle of horizontal synchronization to 1 cycle and another to 1/2 frequency-divided clock", an operation as shown in FIG. The generated clock is output from the clock operation circuit 11.

By the way, the basic operation of the AFC circuit is to automatically control the frequency of the clock so that the interpolation number N is constant, and in this case N = 6. When stabilized, the operation clock after AFC stabilization is 1
6 clocks including 1 clock divided by 2 are generated, and the operation clock after AFC stabilization has a waveform as shown in (e).

The AFC system must operate so as to be stable in 6 clocks, but the clock generating circuit 9 adds 1 and 2 in the 1/4 frequency division operation, so that the clock generating circuit 9 outputs 1 horizontal signal. Fourteen clocks are generated in the cycle, and the clock after the operation has 14 clocks interpolated in one horizontal cycle as shown in (f), and N = 6. = 8, which means that a clock exceeding the limit is interpolated.

Next, an explanation will be given of the case where the operation circuit shown in FIG. FIG. 2 shows the operation circuit, and the clock input from the clock generation circuit 9 is a doubler 16, a 4th multiplier 17, an 8th multiplier 18 ,.
・ And is input to the 2 ⁿ multiplier and outputs the multiplied clock. The input clock and the multiplied clock are switched by the switch 19
The clock that is input to and switched is output.

FIG. 7 shows a time chart in the case of N = 3 and M = 1 by the clock operating circuit 11. In FIG. 7, (a) is a horizontal sync signal separated from the input video signal, (b) is a clock generated by the clock generator 9 before the clock operation, and (c) is a doubled clock of the clock. Shows.

The operation of the clock operating circuit 11 is described as follows.
If fixed to the operation of "replace with multiplied clock", (d)
A clock like this is output from the clock operation circuit 11. If the AFC is stabilized as it is, the operation clock becomes as shown in (e), and at this time, the output of the clock (f) after the operation, that is, the output in which the two clocks are interpolated is obtained from the clock generation circuit 9.

If the clock (b) before the operation is completely replaced with the doubled clock (c) as shown in FIG. 8, the output of the clock generation circuit 9 after the operation is finally as shown in (e). Therefore, it is possible to obtain a clock with three cycles of N = 3 for four horizontal synchronizations, and it is possible to have a degree of freedom beyond the interpolation of an integral multiple of the clock.

By the way, since the operation circuit including the multiplier has a complicated structure, a viable circuit is changed to a frequency dividing type circuit as shown in FIG. 3 before operation. Generated clock of 1/2 by 1/2 divider 21
If the frequency is divided and used as the reference clock, the switching device 20 is switched to the basic clock side 22 and the operating clock is output from the switching device 20, which is equivalent to doubling. Used as an operation circuit. Also, by switching the switch 20 to the 1/4 frequency divider 23 side, a 1/2 frequency divided clock can be obtained, and the multiplied and frequency divided clocks can be output as operation clocks.

As described above, in general, when changing the AFC of the interpolation number N to the interpolation number N + M, N + M ≧ 2M, that is, if N ≧ M, M cycles of N cycles of the AFC input clock. Should be replaced with a clock divided by 1/2. If N <M, the AFC clock is first replaced by a frequency-divided one. As a result, this AFC can be interpolated by 2N, and therefore N + M can be interpolated by replacing the half of M and the period of M / 2 with a quarter-divided clock.

However, when M is an odd number, if only the integer part of M / 2 is replaced and the basic clock is inserted for one cycle, as shown in FIG. 9, N = 6 and M = 7 are set. Looking at this, in this case, since N = 6, the 1 / N frequency division counter becomes a 1/6 frequency division counter. Figure 9
If the clock divided by ½ as shown in (b) is used as an operated clock, 12 clocks generated by the clock generation circuit 9 are included in one horizontal period. When one clock of the basic clock is switched to 1/4 frequency division, 14 generated clocks are inserted, and N + M =
6 + 7 = 13 cannot be inserted.

Therefore, if one wave of the basic clock of the generated clock is inserted as shown in FIG. 9C before switching to the 1/4 frequency division, 1 wave of the basic clock and 1 wave of the 1/4 frequency divided clock are inserted. , AFC is stable by counting 4 waves of 1/2 divided clock, the clock after AFC stabilization is as shown in FIG. 9E, and the clock (f) after the operation is 1 × 1 + 4 × in basic clock units. 1 + 2 × 4 = 13, and 13 clocks can be inserted. 9 (d), the period of the horizontal synchronizing signal is described large, but this is a problem in drawing and is substantially the same as that of FIG. 9 (a).

Generally, 1 × a + 2 × b + 2 ² × c + 2 ×
The number of insertions is determined by d ..., a + b + c + d + ... N
As long as a, b, c, d, ... Are determined, an arbitrary number of insertions can be made.

Similarly, when the interpolation number exceeds 2N, the AF
The operation may be performed by replacing the C clock with a 1/4 frequency-divided clock. On the contrary, when changing the AFC of the interpolation number N to the interpolation number N−M, if N ≧ 2M, the operation for switching the M cycles to the double clock is performed. N-1 when N is an odd number
= 2M, the clock after operation can be shifted by a half cycle to interpolate an odd number of waves in two horizontal cycles.

If N <2M, the clock is multiplied by 2 and 4
The same operation may be performed during multiplication. That is, AFC
If the input clock is first replaced by a doubled clock, this AFC can be changed to N / 2 interpolation. If the (2N-2M) cycle is switched to 4 times, NM
Can be interpolated. As described above, it is apparent that the operation circuit can set an arbitrary number of clocks to be interpolated by switching the frequency division and multiplication and selecting the switching timing.

[0030]

(1) Since the number of interpolations is changed by operating the input clock without changing the inside of the existing integrated AFC circuit, arbitrary interpolation can be performed with a relatively inexpensive circuit. Can generate a clock. (2) The AFC circuit can be realized with a simple circuit because the clock operation has a simple configuration in which the basic clock and its divided frequency or multiplied wave are switched. (3) By increasing the interpolation clock, oversampling or data thinning can be realized with the same AFC circuit.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a block diagram of a second embodiment of the present invention.

FIG. 3 is a block diagram of a third embodiment of the present invention.

FIG. 4 is a block diagram of a conventional example.

FIG. 5 is a first time chart of the first embodiment of the present invention.

FIG. 6 is a second time chart of the first embodiment of the present invention.

FIG. 7 is a first time chart of the second embodiment of the present invention.

FIG. 8 is a second time chart of the second embodiment of the present invention.

FIG. 9 is a third time chart of the first embodiment of the present invention.

[Explanation of symbols]

 6 Horizontal Sync Separation Circuit 7 Phase Comparison Circuit 8 Low-pass Filter 9 Clock Generation Circuit 10 1 / N Frequency Division Counter 11 Clock Operation Circuit 12 1/2 Frequency Divider 13 1/4 Frequency Divider 14 1/8 Frequency Divider 15 Switching device 16 2 multiplier 17 4 multiplier 18 8 multiplier

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H04N 5/12 A

Claims (3)

[Claims] 1. A horizontal synchronization separation circuit for separating a horizontal synchronization signal from an input video signal, and a phase comparison for inputting the horizontal synchronization signal separated by the horizontal synchronization separation circuit and the output of a fixed frequency dividing counter for phase comparison. A circuit, an automatic frequency tracking device having an oscillation frequency controlled based on the output of the phase comparison circuit and a clock generation means for supplying the generated clock to the fixed frequency dividing counter, and an output terminal of the clock generation means. 2. An automatic frequency tracking device according to claim 1, wherein clock operating means for interpolating the same number of clocks in the horizontal synchronization section is provided between the clock generating means and the fixed frequency dividing counter. 2. The clock operating means is a 1/2 ⁿ (n = 1, 2, 3, ...) Dividing means connected in parallel, and the ^dividing means connected in parallel is interpolated in a horizontal synchronization section. 2. An automatic frequency tracking device according to claim 1, further comprising switching means for selectively dividing a frequency of a predetermined number of clocks among the selected clocks and switching and outputting. 3. The clock operating means comprises 2 ⁿ (n = 1, 2, 3, ...) Multiplying means connected in parallel, and a clock in which the parallel connected multiplying means is interpolated in a horizontal synchronization section. 2. The automatic frequency tracking device according to claim 1, further comprising switching means for selectively multiplying and outputting a clock of a predetermined number of cycles.