JP3222356B2 - Pseudo AFC device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pseudo AFC device, more particularly, to a PAL type magnetic recording / reproducing device, particularly a device in which a video camera and a video cassette recorder are integrated.
In order to execute color alignment correction that occurs during special reproduction such as still, cue, and review, the color difference signal is double-toned (4.43).
(Converting into a PAL system chroma signal of MHz)) and an apparatus for generating a (１ ／) · fH pulse that inverts the reference carrier of the RY signal every horizontal synchronization period.

[0002]

2. Description of the Related Art Conventionally, during normal reproduction of a PAL type magnetic recording / reproducing apparatus (hereinafter, referred to as a normal mode), an AP is used.
A (Automatic Phase Control) and AFC (Automatic Phase Control)
ticfrequency Control). The AFC is a control performed to obtain PLL synchronization between a horizontal synchronization signal and a clock which is an output signal of a voltage controlled oscillator.
LL synchronization is, for example, fvc in the VHS system PAL system.
o = 321 · fH, and in the 8 mm system PAL system, fvco = 375 · fH (fvco: frequency of the output signal of the voltage controlled oscillator, fH: 1 horizontal frequency).

A conventional AFC device for performing AFC in the normal mode will be described below with reference to FIGS. FIG. 3 is a block diagram of a conventional AFC device that generates a (1/2) · fH pulse, and FIG. 4 is an operation waveform diagram of a main part of the AFC device.

In the AFC device shown in FIG. 3, a voltage controlled oscillator 1 outputs a clock CLK, and a half H killer 2
An equivalent pulse is removed from the horizontal synchronization signal HSYNC input to the horizontal synchronization signal input terminal 100. The first reset pulse generator 3 uses the output signal of the half H killer 2 and the clock CLK of the voltage controlled oscillator 1 to generate a first reset pulse at the leading edge of the horizontal synchronization signal HSYNC. The counter 7 has a clock input terminal to which the clock CLK of the voltage-controlled oscillator 1 is applied, a reset input terminal to which the first reset pulse of the first reset pulse generator 3 is applied, and an output from the counter 7 which outputs the half pulse. Input to H killer 2.

The clock CLK of the voltage controlled oscillator 1 is applied to the clock input terminal of another counter 10, and the decoder 11 and the second reset pulse generator 12 reset themselves in one horizontal synchronization period. Second
Generate a reset pulse. Digital phase comparator 13
Detects a phase error between the first reset pulse and the second reset pulse, and a detection signal thereof is fed back to the voltage controlled oscillator 1 from a phase error output terminal 500.

The switch 8 selects a first reset pulse from the first reset pulse generator 3 and a second reset pulse from the second reset pulse generator 12. The switch 8 selects the first reset pulse in the normal mode, but receives a trick mode signal generated at the time of trick play (hereinafter, referred to as trick mode) from its input terminal 200, and sets the second reset pulse at trick mode. Select the reset pulse.

After the reset pulse selected by the switch 8 is divided by １ ／ by the 分 frequency divider 9, (1)
It is externally output from a (1/2) · fH pulse output terminal 300 as a (/ 2) · fH pulse.

When the trick mode signal is generated, the phase comparator 13 receives the signal and holds the output.

Next, the operation of the conventional AFC device will be described with reference to FIG.
It will be described based on FIG.

In FIG. 1, a period from time t1 to time t2 is a normal mode. In this mode, the first reset pulse generator 3 generates a first reset pulse at the leading edge of the horizontal synchronization signal HSYNC, and the first reset pulse resets the counter 7 and resets the first reset pulse. After the pulse is selected by the switch 8, the pulse is divided by で in the で divider 9,
It is output to the (1/2) · fH pulse output terminal 300.

Next, when the mode shifts to the trick mode in the period from time t2 to time t3, the horizontal synchronizing signal HSYNC becomes a noise-like signal.
00 in the normal mode.
The second reset pulse of the self-reset second reset pulse generator 12 constituting C is selected by the switch 8, and the first reset pulse is replaced by the second reset pulse.
Since the second reset pulse is applied to the 1/2 frequency divider 9, the 1/2 frequency dividing operation is continuously performed. At this time, since the cycle of the first reset pulse generated by the first reset pulse generator 3 does not become one horizontal synchronization period,
The output of the phase comparator 13 of the AFC loop is held by the trick mode signal.

Subsequently, when the mode is returned from the trick mode to the normal mode in a period from time t5 to time t6, time t6
The first reset pulse generator 3 generates a first reset pulse at the leading edge of the horizontal synchronization signal HSYNC arriving at the switch 8, and this first reset pulse is
And is applied to the 1/2 frequency divider 9, so that (1
/ 2) · fH pulse is obtained.

That is, in the conventional AFC device, the AFC is performed through both the normal mode and the trick mode.
In the trick mode, the horizontal synchronization signal H
Instead of the information of one horizontal synchronization period by SYNC, AF
The continuity of the (1/2) · fH pulse is guaranteed by using the second reset pulse of the second reset pulse generator 12 in the C loop.

[0014]

However, in the above-mentioned conventional AFC apparatus, although the AFC function is required only in the trick mode, the AFC function is also required in the normal mode.
Since the configuration is such that the function of the FC is operated, another counter 10 and a phase comparator 13 are required separately, the number of pin terminals is increased, and there is a problem of an increase in cost.
There was a disadvantage that the image quality was degraded due to the operation C itself.

[0015] In view of the above, the present invention has a
Without configuring the AFC as the LL loop, accurate one horizontal period information is obtained even in the trick mode, and (1/1)
2) To stably and inexpensively guarantee the continuity of the fH pulse.

[0016]

In order to achieve the above object, the present invention uses only a counter which is reset by a first reset pulse, and based on the output of this counter, a second buffer whose buffer oscillation is 0%. Is generated, and the continuity of the (１ ／) · fH pulse in the trick mode is ensured by the second reset pulse.

That is, the pseudo AFC device according to the first aspect of the present invention includes a voltage controlled oscillator for outputting a clock signal, a half H killer for removing an equivalent pulse from a horizontal synchronizing signal,
A first reset pulse generator for generating a reset pulse based on a clock signal of the voltage controlled oscillator at a leading edge of a signal from which an equivalent pulse has been removed by the half H killer; A counter as an input, a decoder for decoding the output of the counter, and a second reset pulse generation for generating a reset pulse with a buffer oscillation of 0% based on the output of the decoder and a clock signal of the voltage controlled oscillator. The reset pulse generated by the first reset pulse generator in the normal mode, and the second reset signal in the special mode. Select the reset pulse generated by the pulse generator and select the selected reset pulse. A switch that uses a reset pulse selected by the switch as a reset signal of the counter, and a 分 frequency divider that receives the reset pulse and generates a (・) · fH pulse. .

According to a second aspect of the present invention, in the pseudo AFC device according to the first aspect, the switching signal is PAL.
The magnetic recording / reproducing apparatus is characterized in that it is a drop-out signal which becomes "H" level during a noise bar period on a screen in a special mode and becomes "L" level in other periods.

Further, the invention according to claim 3 is the pseudo AFC device according to claim 1 or 2, wherein
A timing shaper for delaying the switching signal by a set time by the output of the half H killer is provided, and the switch is switched by the switching signal timing-shaped by the timing shaper.

[0020]

With the above arrangement, in the first to third aspects of the present invention, in the normal mode, the switch is switched to the first reset pulse generator side. (1/2) · f based on the reset pulse of
An H pulse is obtained. At this time, the counter counts the clock signal of the voltage-controlled oscillator and resets the count value when the first reset pulse is generated.

In this state, if the counter shifts to the special mode during the clock counting operation, the switch is switched to the second reset pulse generator side, and in this state, the set count of the counter (normal Since the second reset pulse generator generates the second reset pulse with the accurate horizontal synchronization period information), the counter value is reset when the counter is reset. At the same time, a (1/2) · fH pulse is generated based on the second reset pulse. Thereafter, the counting operation of the counter, the resetting operation of the counter value, and the generation of the (１ ／) · fH pulse are repeated, so that the continuity of the (１ ／) · fH pulse is guaranteed.

Here, without configuring the AFC as a PLL loop, the oscillation frequency of the clock of the voltage controlled oscillator is kept constant in both the normal mode and the special mode, and accurate one horizontal synchronization period information in the special mode. Therefore, the (1/2) · fH pulse, which is the inversion pulse for one horizontal synchronization period used for color alignment correction, is stable and inexpensive without the need for another counter or phase comparator as in the related art. can get.

In particular, according to the third aspect of the present invention, the switch selects the second reset pulse of the second reset pulse generator during the clock counting operation of the counter, so that the (1/2) .fH pulse is used. Continuity is guaranteed.

[0024]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the overall configuration of a pseudo AFC device according to the present invention. In the figure, 1 is a voltage controlled oscillator that outputs a clock CLK, 2 is a half H killer that removes an equivalent pulse from the horizontal synchronization signal HSYNC input to the horizontal synchronization signal input terminal 100, and 3 is the half H killer 2 A first reset pulse generator that generates a first reset pulse at the leading edge of the horizontal synchronization signal HSYNC using the output signal of the voltage controlled oscillator 1 and the clock CLK of the voltage controlled oscillator 1.

Reference numeral 4 denotes a timing shaper. The shaper 4 receives a dropout signal input to a signal input terminal 200 as an input. Here, the drop-out signal is a signal which becomes "H" level during the noise bar period on the screen in the trick mode (special mode) and becomes "L" level in the other periods including the normal mode (normal mode). It is. The timing shaper 4 includes a half H killer 2
Based on the output, the timing of the dropout signal is shaped so as to be delayed for a set period as shown in FIG.

A counter 7 has a clock input terminal ck connected to the clock CL of the voltage controlled oscillator 1.
K is applied, and the output is input to the half H killer 2. 5 is a decoder for decoding the output of the counter 7, and 6 is a second for generating a second reset pulse having a buffer oscillation of 0% based on the output of the decoder 5 and the clock CLK of the voltage controlled oscillator 1. It is a reset pulse generator.

Reference numeral 8 denotes a switch. The switch 8 receives a timing-shaped dropout signal from the timing shaper 4 as a switching signal. The first reset pulse of the first reset pulse generator 3 is selected, and when the dropout signal is at the “H” level, the second reset pulse of the second reset pulse generator 6 is selected. The reset pulse selected by the switch 8 is applied to a reset input terminal R of the counter 7.

In addition, reference numeral 9 denotes a 1/2 frequency divider which receives the reset signal selected by the switch 8 as an input signal, and the output of the 1/2 frequency divider 9 is (1/2) .multidot.fH. It is externally output from the output terminal 300 as a pulse.

Next, the operation of this embodiment will be described with reference to FIG.

Outside the noise bar period (dropout signal: "L"), the first reset pulse generator 3 generates the first reset pulse at, for example, times t1 and t2 (the leading edge of the horizontal synchronization signal HSYNC). The first reset pulse is selected by the switch 8 and input to the counter 7, and the counter 7 is reset. At the same time, the first reset pulse is supplied to the 1/2 frequency divider 9 and divided by 1/2 to (1/2). ) -Externally output from output terminal 300 as fH pulse.

On the other hand, during the noise bar period (dropout signal: “H”), the switch 8 causes the switch 8 to reset the second reset pulse of the second reset pulse generator 6 by the dropout signal timing-shaped by the timing shaper 4. A pulse is selected, and this pulse is input to the 1/2 frequency divider 9. Therefore, even if the horizontal synchronization signal HSYNC is in a noise-like random state during the noise bar period, the counter 7 keeps the first counter 7 at the time t2 (leading edge of the horizontal synchronization signal HSYNC) immediately before the dropout signal arrives. It is reset by the first reset pulse of the reset pulse generator 3, and the set count of this counter 7, for example, the 321st count in the VHS system,
In the 8 mm system, at the time of the 375th count, the second reset pulse generator 6 generates a second reset pulse, and the second reset pulse causes the counter 7 to perform a self-reset operation, and at the same time, the second reset pulse is generated. A reset pulse is input to the 分 frequency divider 9. Thereafter, the reset pulse generator 6 repeats the generation of the reset pulse until the end of the noise bar period. Therefore, the self-reset operation of the counter 7 and the input of the reset pulse to the 分 frequency divider 9 are also repeated. / 2) The continuity of the fH pulse is guaranteed.

After that, when the dropout signal returns to "Lo" and the noise bar period ends at a time between time t5 and time t6, the switch 8 switches to the first reset pulse generator 3 side. Then, when the normal horizontal synchronizing signal HSYNC is inputted at a time t6 thereafter, the first reset pulse generator 3 generates a first reset pulse at the leading edge thereof, and this pulse is generated by the switch 8
, And is input to the 1/2 frequency divider 9, so that (1/2) ·
An fH pulse is obtained.

Therefore, in a period other than the noise bar period (dropout signal: “L”), the horizontal synchronization signal HSYNC is output.
7 reset at the leading edge of
However, during the noise bar period (dropout signal: “H”), the counter 7 is reset by the self-reset pulse, and the continuous operation of the counter 7 within one horizontal synchronization period is ensured while the color alignment in the trick mode is corrected. Required (1 /
2) The fH pulse can be obtained stably.

Moreover, since the timing shaper 4 shapes the timing of the dropout signal with the output signal of the half H killer 2, the timing of transition to the buffer oscillation 0% mode is always the horizontal synchronization signal H of the counter 7.
It does not overlap with the reset timing by SYNC, and therefore, it is guaranteed that the transition to the buffer oscillation 0% mode is performed during the counting operation of the counter 7.

Note that the reset pulse of the reset pulse generator 6 may not be output during periods other than the noise bar period as shown by broken lines at times t2 and t7 in FIG.
That is, if the arrival timing of the horizontal synchronizing signal HSYNC has a minute change, and this arrival timing is earlier than when the buffer oscillation is 0%, no signal is output. However, there is no problem because the reset pulse of the reset pulse generator 6 is not used in a period other than the noise bar period.

In this embodiment, a dropout signal is used as a switching signal for the switch 8, but a mode switching signal may be used instead.

[0038]

As described above, according to the pseudo AFC device of the present invention, the PLL
Since accurate one horizontal period information can be obtained even in the special mode without forming the AFC as a loop, a P-camera in which the video camera and the video cassette recorder are integrated
In the AL system magnetic recording / reproducing apparatus, the (1/2) .fH pulse for inverting and switching the demodulation carrier of the RY signal in the color difference signal demodulation unit, which is a basic configuration circuit, every horizontal synchronization period is provided stably and at low cost. The effect that can be achieved.

In particular, according to the third aspect of the present invention, during the counting operation of the counter, the buffer oscillation 0
By shifting to the% mode, the continuity of the (１ ／) · fH pulse can be reliably guaranteed.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a block configuration of a pseudo AFC device according to an embodiment of the present invention.

FIG. 2 is a diagram showing operation waveforms of main parts of the pseudo AFC device according to the embodiment of the present invention.

FIG. 3 is a diagram showing a block configuration of a conventional AFC device.

FIG. 4 is a diagram showing operation waveforms of main parts of a conventional AFC device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 voltage controlled oscillator 3 first reset pulse generator 4 timing shaper 6 second reset pulse generator 7 counter 8 switch 9 1/2 frequency divider

Claims (3)

(57) [Claims] A voltage-controlled oscillator for outputting a clock signal; a half-H killer for removing an equivalent pulse from a horizontal synchronizing signal; and a leading edge of the signal from which the equivalent pulse has been removed by the half-H killer. A reset pulse generator that generates a reset pulse based on the clock signal of the above, a counter that receives a clock signal of the voltage-controlled oscillator as a clock input, a decoder that decodes an output of the counter, an output of the decoder, A second reset pulse generator for generating a reset pulse having a buffer oscillation of 0% based on a clock signal of the voltage-controlled oscillator, and a switching signal that changes between a normal mode and a special mode; In the normal mode, the reset pulse generated by the first reset pulse generator is set. And a switch for selecting a reset pulse generated by the second reset pulse generator in the special mode, and using the selected reset pulse as a reset signal of the counter; and a reset pulse selected by the switch. And a 分 divider for generating a (１ ／) · fH pulse. 2. The switching signal is a drop-out signal which becomes "H" level during a noise bar period on a screen in a special reproduction mode in a PAL system magnetic recording / reproducing apparatus, and becomes "L" level in other periods. The pseudo AFC device according to claim 1, wherein: 3. The apparatus according to claim 1, further comprising a timing shaper for delaying a switching signal by a set time by an output of a half H killer, wherein a switch is switched by the switching signal timing-shaped by the timing shaper. 2. The pseudo AFC device according to 2.