JPS6359184A - Video signal recording and reproducing device - Google Patents

Abstract

PURPOSE:To record and reproduce a high quality video signal by providing a reset forming circuit for forming the reset signal of the writing address of a memory means in a time base correction circuit and a pilot extraction circuit for extracting a pilot signal and synchronizing the reset signal with the pilot signal and outputting. CONSTITUTION:Initially, the pilot signal produces a time base error according to the influence of a jitter in a reproducing process and the writing signal of time base correction devices TBC21, 22 better in accuracy than this pilot signal can be formed. With respect to the overflow of a memory, according to the reset signal from a reset signal forming circuit 25 synchronizing with the pilot for every one vertical synchronizing period, a memory address can be constantly reset to a position having a constant relation with a vertical synchronizing signal and the overflow of the memory can be prevented.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a video signal recording and reproducing device, and in particular, a video signal recording and reproducing device that converts a color carrier signal to a low frequency and records it, and performs time axis correction during reproduction. Accurately detects time axis errors,
The present invention relates to a video signal recording and reproducing device suitable for reproducing high quality video signals.

[Conventional technology]

Home VTRs, which are currently widely used, divide the video signal (generally an NTSC color signal) into two frequency bands in order to record and play over long periods of time with low tape consumption. A low frequency conversion color process is performed to mix these signals and record them on tape. . This color process was created by Tokko Akira, l! No. 5-28615. In addition, the carrier color signal recorded after being converted to a low frequency in the above process is subject to time axis fluctuations that occur in the drive system of the tape and head during the reproduction process, and the reproduced carrier color signal includes phase fluctuations. 1. Such phase fluctuations in the carrier color signal have a fatal effect on color reproduction on the screen, making accurate color reproduction impossible. Therefore, in the process of restoring the original high frequency signal from the reproduced carrier color signal through frequency conversion, the color burst signal in the carrier color signal and the output of the stable reference subcarrier frequency oscillator are used to deal with such phase fluctuations. The frequency of the local oscillator for frequency conversion is controlled using a voltage corresponding to the phase difference between the two signals, thereby eliminating phase fluctuations in the reproduced signal (so-called APC).
method).

On the other hand, the luminance signal recorded after one frequency modulation (FM) is demodulated after reproduction and converted to the original baseband band.
It is sent to a TV receiver (or monitor) without any time axis error correction.

As mentioned above, in current home VTRs such as the VJIS system, phase stabilization is performed on the carrier color signal, but no consideration is given to the luminance signal. As a result, a frequency interleaving relationship is established between the luminance signal and the carrier color signal, resulting in a non-standard color signal.

This)/standard color signal is the same as the current TV receiver'
In the case of image-wise reproduction, color shift and screen fluctuation are practically not a problem. However, on the other hand, TV receivers (so-called IDT) using a double-speed scanning method using frame memory, etc., are being developed as a way to improve the image quality of TV images and as next-generation TV receivers.
(V or digital television) uses signal correlation between frames or within frames to improve image quality, so the input video signal must be a standard color signal that does not include time axis fluctuations. be done. Therefore, home VTRs compatible with such next-generation TV receivers are necessarily required to eliminate time axis fluctuations from reproduced video signals and to realize standard color reproduction. To meet this demand, the time axis correction device (Teima Ba5) has traditionally been used in the field of broadcasting VTRs.
e Corrector +hereinafter referred to as TBC. ) have been put into practical use, and various systems are introduced, for example, in ``Broadcasting VTR'' (edited by Japan Broadcasting Corporation, published October 20, 1980). However, when a conventional TBC designed to be connected to a broadcast VTR is connected to the home VTR, the SN ratio of the synchronization signal and color burst signal, which serve as the reference for the time axis of the reproduced signal, becomes There was a problem in that it was not sufficient, causing malfunction of the TBC, and even deteriorating the image quality. In addition, household V
When applying TBC to TR, TB is
It is necessary to reduce the memory capacity of C, but the conventional T
In BC, there was a problem as no consideration was given to this point.

[Problem that the invention seeks to solve]

As mentioned above, current home VTRs use a low frequency conversion color process and use the APC method for demodulating chromaticity signals, so the reproduced signal is a non-standard color signal. Furthermore, even if TBC is used to standardize the non-standard color signal, there is a problem in that the S/N ratio of the reproduced signal is insufficient, leading to deterioration in image quality.

Furthermore, when applying a home VTRK TBC, it is necessary to reduce the memory capacity in order to reduce costs, but conventional TBCs do not take this point into account, which poses a problem.

In view of the above, an object of the present invention is to accurately detect time axis fluctuations (jitter) from a reproduced signal, and thereby generate a high quality reproduced signal from which time axis errors have been removed by using a TBC having a relatively small memory capacity. An object of the present invention is to provide a video signal recording and reproducing device that can be obtained using the present invention.

[Means for solving problems]

Next, the means for achieving the above objective will be described.

In the video signal recording and reproducing apparatus according to the present invention, a pilot signal having a predetermined frequency is recorded on a recording medium along with the video signal during recording, and during reproduction.

The method is to detect time axis errors from the reproduced pilot signal. Further, the phase of the pilot signal is changed by a predetermined phase angle every vertical synchronization period, and the phase of each vertical synchronization signal and the pilot are recorded in such a manner that they always have a constant relationship. Furthermore, in order to prevent overflow or underflow of the memory used in TBC, the memory address is reset once every vertical synchronization period. At this time, the reset signal is generated after being synchronized with the pilot signal.

[Effect]

In the above configuration, first, the pilot signal causes a time base error due to the influence of jitter during the reproduction process, and it is possible to generate a more accurate TBC write signal than this pilot signal. Additionally, in response to memory overflow, a reset signal synchronized with the pilot every vertical synchronization period allows the memory address to be reset at a position that is always in a constant relationship with the vertical synchronization signal, preventing memory overflow. can.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of an embodiment of a video signal recording and reproducing apparatus according to the present invention.

Moreover, FIG. 2 schematically shows the waveforms of various parts in the recording system of FIG.
N corresponds to the reference numerals in FIG. In FIG. 1, a video signal (usually an NTSC signal) inputted to the video signal input terminal 1 during recording is converted into a luminance signal (A) by a low-pass filter (Lpp) 2, and a luminance signal (A) by a bandpass filter (Lpp) 2. BPF)
4, the carrier color signals (b) are respectively extracted and sent to the next stage. The above luminance signal (A) is then sent to the adder circuit (A).
DD) 5, where the pilot signals are added, for example, as shown in (c). In the example shown in ← in FIG. 2, a signal of a predetermined frequency is added in burst form to the pack pouch of the luminance signal. Next, this signal is converted to F in the FM modulation circuit 4.
The signal is M-modulated and output to one terminal of the adder circuit 12.

On the other hand, the carrier color signal (b) is input to the frequency conversion circuit 6, and the input signal near 3.58 MH2 is converted to a predetermined low frequency 1, for example, 629kHz (hereinafter, this signal will be referred to as the low frequency conversion carrier color). signal, or simply low-frequency conversion signal).

As shown in FIG. 1, the luminance signal (a) and carrier color signal (b) described above are processed as follows to generate a pilot signal. First, the carrier color signal (b) is input to the fsc continuous wave generation circuit 7, where a continuous signal of frequencies f and c (color subcarrier frequency) synchronized with the color burst is generated. Next, this continuous signal is frequency-divided by a frequency dividing circuit 8 having a predetermined division ratio, and in a phase switching circuit 10, the phase is shifted by a predetermined phase angle for each vertical synchronization signal detected by the synchronization signal detection circuit 9. be done. In the gate circuit 11,
A continuous signal whose phase angle is shifted for each vertical synchronization signal as shown above? The data is divided into bursts and output to the ADD circuit 3. The luminance signal, burst-shaped pilot signal (burst pilot), and low-pass conversion carrier color signal obtained by K as described above are added in the ADD circuit 3 and the adder circuit 12, and then
The data is recorded on a recording medium 15 such as a magnetic tape by a recording head 14 via a recording amplifier 13. Next, during operation, the signal reproduced from the reproduction head 16 is amplified by the head amplifier 17 to a predetermined level 1, and then the signal is amplified by the BPFI 8 and LPF.
19, an FM-modulated luminance signal and a low-pass conversion carrier chrominance signal are obtained, respectively. Among these, the luminance signal is F
The signal is demodulated by the M demodulation circuit 20 to become the original baseband signal, which is then input to the TEC 21. On the other hand, the low frequency conversion carrier color signal is inputted as is to the TBC 22. here,
As shown in FIG. 1, the burst pilot recorded on the back porch of the luminance signal and reproduced is first extracted only in the burst pilot signal by the burst pilot extraction circuit 26, and a continuous wave is generated from this signal. PLL 24
sent to. The above pilot signal can ensure a good S/N ratio by appropriately selecting one frequency and recording level, and the continuous wave generated from this signal is synchronized with the jitter during playback, so it is used as the TBC write clock. be able to. For example, now as a pilot signal Lc
If a signal with a frequency of /2 is recorded, the PLL 24 generates a continuous wave with a frequency 8 times higher during playback, so that ' fzc , that is, 910 fzr <
A write clock having a frequency of hr (horizontal synchronization frequency) can be obtained. The write clock thus obtained is sent to the TBCs 21 and 22. This write clock is also sent to the reset signal generation circuit 25, where a memory address reset pulse on the write side of the TBC is generated once every vertical synchronization period. next,
The read timing generation circuit 27 generates a read clock with crystal oscillation precision and a memory address reset pulse on the read side, and sends them to the TBC2] and 22. As mentioned above, in the TBC of this embodiment, the memory address is reset (returns to address 0) once every vertical synchronization period, so at this point, the memory address caused by the difference in the frequency of the write and read clocks is Since the difference in values is canceled out, memory overflows and underflows are less likely to occur.

Generation of the reset pulse will be detailed later.

Now, as described above, jitter is removed from the luminance signal and the low frequency conversion carrier color signal by the TBCs 21 and 22. Next, the luminance signal is sent to a pilot removal circuit 2 to remove the pilot signal inserted into the back porch.
9 and its output is added to one end of an adder circuit 60. On the other hand, the low-pass conversion carrier color signal is output from the TBC 22 and input to the 1-frequency conversion circuit 28, and is converted to the original 5.58
After frequency conversion to a signal near MHz, adder circuit 3
added to the other end of 0.

It is combined with the luminance signal and a video signal output is obtained at the terminal 31.

Now, before we get into the detailed explanation of how each part works.

The relationship between the phase of the pilot signal and the phase of the synchronization signal will be explained, and the reason why it is necessary to switch the phase of the pilot signal in the present invention will be shown. First, FIG. 3 is a diagram showing the phase relationship of each signal, in which (α) is a color subcarrier and (b) is a pilot signal, in which the frequency of fzc72 is selected. In addition, (cl indicates a horizontal synchronizing signal. As is well known, there is a relationship between the one-color printing carrier wave frequency fzc and the horizontal synchronizing frequency hrO as f, c = fi, and a one-frequency interleaving relationship is established. Now, as a pilot signal fz c/
When a signal with two frequencies is selected, the phase relationship between the biloft signal and the horizontal synchronization signal is such that the phase of the pilot signal advances by 1π every horizontal opening period, or -
The relationship is that there is a delay. Next, let us look at the relationship between the phase of the pilot signal and the phase of the vertical synchronization signal in FIG. 4. .

In FIG. 4, (d) shows the first H (H is a horizontal synchronizing signal) after the vertical synchronizing pulse of each field, and one field period includes 263H and 262H alternately. (-) is a diagram showing an enlarged waveform of the pilot signal in the vicinity of the falling edge of the first H, for example. The pilot signal that passes through as explained in Fig. 5 is I
Since a phase shift occurs by -π for each H, the phase shifts by π in the case of 263H and -262H in one field period2.

As a result, the phase of the pilot signal becomes different one after another near the edge of the vertical synchronization signal, resulting in a relationship like (#).

Therefore, in order to maintain a constant phase relationship between the vertical synchronization signal and the pilot signal, the phase of the waveform shown in FIG.
You should get a waveform like this. FIG. 5 is a diagram showing the amount of phase shift of the pilot signal for each field period, and this phase relationship is such that it goes around in eight fields. As shown in FIG. 5, if the phase of the pilot signal is 0° in the 11th field of the first field, it is sufficient to generate and send out a pilot signal delayed by - in the second field. By performing similar operations thereafter, the phase of the vertical synchronization signal and the phase of the pilot signal can be controlled so that they always have a constant relationship.

A specific method for performing the above operation is shown in FIG. 1, and will be explained in more detail using FIG. 3. Figure 3 (A
) is a block diagram showing in detail the main parts of the recording system of FIG. 1, and FIG. 3 (J) shows waveforms of each part corresponding to (, 4). First, the carrier color signal is input from the BPF 5 to the fzc continuous wave generation circuit 7, where a continuous wave synchronized with Le in the input color burst is generated (
) corresponding to the waveform).

Next, this continuous wave is input to the doubler circuit 8-1 (E).
A signal such as is obtained, and this signal is input to the frequency divider circuit 8-2 and the clock input terminal CX of the shift register 0-1. The frequency dividing circuit 8-2 divides the frequency of the signal (E) by four to generate a signal (E), that is, a pilot signal having frequencies of f and c/2. Next, the signal (to) is input to the data input terminals of shift registers 0-1. The shift registers 0-1 generate signals (to), ()), (ffi, (I) whose phases are shifted by - from the signal (to), respectively.
JI is output and input to the selector circuit 10-2.

On the other hand, the luminance signal from the LPF 2 is input to the synchronization signal detection circuit 9, where a vertical synchronization signal V and a horizontal synchronization signal I are extracted and input to the selector circuit In-2 and the gate circuit 11, respectively. In the selector circuit 1o-2, a pilot signal of a predetermined phase is selected for each V and input to the gate circuit 11, as described above.

The gate circuit 11 generates a predetermined gate from the horizontal synchronizing signal and outputs the input pilot only during that period, thereby generating a burst pilot signal and sending it to the MIX circuit 5.

Next, FIG. 7 is a block diagram showing in detail the main parts of the reproduction system of FIG. 1, and FIG. 8 is a waveform diagram explaining the operation of FIG. 7. In FIG. 7, the reproduced luminance signal is input to the TBC 21, and the carrier color signal is input to the TBC 22. TBC2+ and TBC22 are AI) converter 2
1-1. Random access memory (RAM) 21-2
, DA converter 21-5.8 write address generation circuit 21-4. It consists of a read address generation circuit 21-5. TBC performs AD conversion and write address setting using the write side clock, and performs DA conversion and read address setting using the read side clock. At this time, generally, a clock synchronized with the jitter of the reproduced signal is used as the write clock, and a jitter-free clock using a crystal oscillator or the like is used as the read clock, so that a video signal from which jitter has been removed can be obtained as an output. However, because the capacity of the RAM used as a buffer memory for absorbing the TBC jitter is limited, and the write and read clocks are asynchronous, there are cases where the RAM overflows. In this example, for this purpose.

As mentioned earlier, the memory address is reset every vertical synchronization, and the design is such that the tolerance against memory overflow due to the difference in clocks is increased. However, if a reset signal is generated every vertical synchronization, it is necessary to reset the address at the same position of the video signal each time. Therefore, in this embodiment, a pulse that rises at the first horizontal synchronization after the end of the vertical synchronization block is generated, and this pulse is further synchronized with a pilot signal to obtain a reset signal. The operation of each part will be explained in detail below using FIG. VCF during playback
The luminance signal output from the M demodulation circuit 2o is input to the burst pilot extraction circuit 23 and the first H detection circuit 25-1. A burst pilot signal included in the luminance signal is extracted by the burst pilot extraction circuit 26 and input to the PLL 214 1c, where, for example, 'f
A continuous wave with a frequency of zc = 910 fH is generated. This continuous wave is used as a write clock in the TBC by the AD converter 21-1 and the write address circuit 21.
-4 is input. - On the other hand, this continuous wave is divided by 8 frequency circuit 25
-4, and is input to the clock terminal of a D-FF (D type flip-flop) 25-5. On the other hand, the first H detection circuit 25-1 detects the first H after the end of the vertical synchronization block, as shown in FIG. 8, and outputs the detection signal to the next monomulti 25-2. mono multi 2
5-2 generates pulses of a predetermined width and outputs the first stage, D-FF.
The above pulse is input to the data input of 25-5. D-F
A signal synchronized with the output of the divide-by-8 circuit 25-4 is obtained as the output of F25-5, and this signal is output as a write address reset pulse to the write address generation circuit. In the read timing generation circuit 27, a signal with crystal oscillation precision is obtained from the 'LcO5C27-5 that generates the frequency of s'fzc, and this signal is used as a read clock to the DA converter 21-5 and the read address generation circuit 21.
Enter -5. Further, a reference synchronization signal is generated in the synchronization signal generation circuit 27-2 based on the crystal oscillation precision signal,
Further, from the reference synchronization signal, the first H after the vertical synchronization block is detected by the first H detection circuit 27-1, similarly to the write side. Since the horizontal synchronization signal on the read side is synchronized with the crystal oscillation frequency 'Lc, resynchronization as on the write side is not required.

With the above configuration, addresses are always reset on both the write and read sides at a fixed position in the video signal, and there is no screen wobbling due to address reset, and jitter is eliminated even with a relatively small memory capacity. It is possible to realize a TBC with a large tolerance for. FIG. 9 is a block diagram showing another embodiment according to the present invention. In FIG. 9, the TBC 21 is arranged after the adder circuit 30, and the time axis correction is performed on the video signal which is a combination of the luminance signal and the carrier color signal. If this method is used, TBC
Although it is possible to reduce the hardware with a single system, the interleaving relationship between the luminance signal and the carrier chrominance signal is usually required due to the APC circuit used in the process of returning the low-frequency conversion carrier chrominance signal to its original frequency. Since this is not true, standard color cannot be created even if time axis correction is performed using TBC. Therefore, in this embodiment, a frequency dividing circuit 24-1 is provided after the PLL 24, and the 4 fsc output from the PLL 2A is
The frequency of the clock is divided by four by the frequency dividing circuit 24-1, and the low-frequency conversion carrier color signal is converted into the original high-frequency signal by f, which is synchronized with the jitter. This configuration establishes an interleaving relationship between the luminance signal and the carrier color signal, and T
Since the jitter is removed by the BC 21, a standard color signal can be obtained as the video signal output.

In addition, in the above embodiment, ft c is used as a pilot signal.
/2 frequency is used, but if one frequency is used as a pilot with nhr (-: natural number, fx: horizontal synchronization frequency), there is no need to switch the phase of the pilot signal during recording. It is clear that the same effects as in the above embodiment can be expected in other cases as well.

〔Effect of the invention〕

As is clear from the above description, the video signal recording and reproducing apparatus according to the present invention uses a pilot signal to generate a TBC write clock and also uses a memory address reset signal synchronized with the pilot. Highly accurate and highly stable time axis correction is possible,
In addition, since the address of the memory is reset every vertical period, it is possible to realize a TBC with a large jitter tolerance with a relatively small memory capacity, so it is possible to record and play back high-quality video signals with excellent reliability. Can be done.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram of each part of FIG. 1, FIGS. 3 and 4 are waveform diagrams showing the phase relationship of ordinary signals, and FIG. Figure 3 is a diagram showing the phase relationship of pilot signals in the field. Figure 3 is a diagram showing the main parts of the recording system in Figure 1 and their waveforms. Figure 7 is a block diagram showing the main parts of the reproduction system in Figure 1. Figure 8. 7 is a waveform diagram for explaining the operation, and FIG. 9 is a block diagram showing another embodiment of the present invention. 3...Addition (AndD) circuit 4...FM modulation circuit 6.
...... Frequency conversion circuit 7...
・・・・・・・・・・・・fzc continuous wave generation circuit 8...
・・・・・・・・・・・・Divide circuit 9・・・・・・・・・
...... Synchronous signal detection circuit 10 ......
...Phase switching circuit 11 ......-
...Gate circuit 20 ...FM demodulation circuit 21.22 ...TEC 123 ......Burst pilot extraction circuit 24 ...・・・・・・・・・・・・ PLL25
・・・・・・－・・・Reset signal generation circuit 28...
...... Frequency conversion circuit 29 ...
・・・・・・・・・Pilot removal circuit agent Patent attorney
Katsuo Ogawa χ zi )\゛-S F Kiyokuchi, )-4a

Claims (1)

[Claims] 1. A time axis correction circuit having a storage means for recording both a video signal and a pilot signal of a predetermined frequency on a recording medium and sequentially storing the reproduced video signal during reproduction, and a reproduction signal from the pilot signal. In a video signal recording and reproducing apparatus, the video signal recording and reproducing apparatus is equipped with a means for detecting a time base error included in a reproduced video signal, and generates a reset signal for a write address of a storage means in the time base correction circuit. What is claimed is: 1. A video signal recording and reproducing device comprising: a reset generating circuit for extracting the pilot signal; and a pilot extracting circuit for extracting the pilot signal, and outputting the reset signal in synchronization with the pilot signal. 2. The pilot signal is a temporally discontinuous burst-like pilot signal, and is equipped with a phase-locked loop circuit that generates a continuous wave from the burst-like pilot signal during reproduction, and a write address reset signal is sent to the phase-locked loop circuit. The video signal recording and reproducing device according to claim 1, wherein the video signal recording and reproducing device is configured to output the video signal in synchronization with the output signal. 3. Equipped with a phase switching circuit that switches the phase of the pilot signal using an external control signal during recording, and shifts the phase of the pilot signal by a predetermined angle for each field to adjust the phase relationship between the horizontal synchronizing signal and the pilot signal in each field. 3. The video signal recording and reproducing apparatus according to claim 1, wherein the video signal recording and reproducing apparatus records the video signal after making it constant. 4. The frequency of the pilot signal is f_s_c/2(f
_s_c: color subcarrier frequency) The video signal recording and reproducing apparatus according to claim 1, 2, or 3.