JP2525883B2 - Sync converter - Google Patents

Description

The present invention relates to a synchronous conversion device suitable as a TBC (time base collector) for removing jitter from a VTR (video tape recorder).

[Prior Art] First, a conventional synchronous conversion device used as a TBC of a VTR will be described.

This synchronous converter performs A / D (analog / digital) conversion of an input video signal such as a VTR playback signal using a clock signal synchronized with itself, and converts the converted video data to a memory circuit by this clock signal. Sequentially write and read the written data sequentially by using a clock signal synchronized with the reference signal, and then D / A (digital / analog) convert to the original video signal. As described above, the writing and reading operations on the memory are performed independently of each other, whereby the video signals are synchronously converted.

By the way, in such a synchronous converter, the address of the memory is reset to the address 0 every time writing and reading of a fixed amount of data (usually, the amount of data of the memory used) are completed, and writing and writing of the next data is performed. Reading is restarted respectively, but if the timings of these write address and read address approach each other and there is an overtaking or overtaking between the write address and the read address, as shown in FIG. Repeated reading or omission occurs. This data over-reading or omission appears as a position shift of the image on the reproduction screen.

In a TBC configured with a memory having a capacity of several lines, when processing a video signal with a lot of jitter such as a VTR reproduction signal, a write reset signal and a read address for resetting the write address to address 0 0
The timing of the read reset signal resetting to the address fluctuates in the vicinity of approximately the same phase, thereby overtaking both.
Overtaking may occur frequently, and as a result, vertical image shifts occur continuously on the screen, making the reproduced image very unsightly.

As a measure for avoiding such a phenomenon, for example, as described in the Journal of the Television Society of Japan, Vol. 31, No. 10, page 772, Section 3.1, a synchronization signal whose phase is advanced from the reference synchronization signal (advanced synchronization signal) is used. As described in the technology of controlling the phase of the VTR capstan motor so that writing and reading on the memory do not overlap, and as described in the Television Society of Japan, Vol. 33, No. 4, page 278, Section 3.2, frame capacity. Using the frame synchronizer with the memory of TBC as the TBC, the phase difference between the reset signal of the write address and the reset signal of the read address is detected, and when the phase difference approaches a certain set value or less, the reset signal and the write address of the write address are detected. If the data is delayed by a few lines, or if it is limited to the frame memory, the write and read vertical addresses are compared,
A technique is known in which the value of the read address is shifted by one field when these addresses match, thereby avoiding overlapping of the timings of the write address and the read address.

[Problems to be Solved by the Invention] However, in the above-mentioned conventional technique for controlling the capstan motor of the VTR by the advance synchronization signal, the amount of phase advance of the advance synchronization signal with respect to the reference synchronization signal is set in the TBC correction range. It needs to be adjusted to maximize. Regarding the above frame synchronizer, if the application is limited to TBC for VTR or synchronous coupling between two VTRs, the required time axis correction range is usually several H (however, 1H is the horizontal scanning period). Since this is sufficient, the memory capacity is obviously too large, and in particular, when this device is built in a VTR, there is a problem in terms of circuit scale.

An object of the present invention is to solve the above problems of the prior art, and to allow a memory having a capacity of several lines to overtake the timing of the write address and the read address of the memory.
An object of the present invention is to provide a period conversion device capable of automatically suppressing overtaking and having a small circuit scale.

[Means for Solving the Problems] In order to achieve the above object, the present invention digitizes a luminance signal and a chrominance signal of a video signal, and synchronizes with a writing reference signal synchronized with the video signal, respectively. When writing to the second memory circuit and reading the digital luminance signal and the digital color signal from the first and second memory circuits respectively in synchronization with the read reference signal, the write address of the first or second memory circuit is set. Detecting means for outputting a detection signal when the time difference between the reset signal for resetting the write signal for resetting and the reset signal for resetting the read address is within a predetermined range; A shift means for shifting the write reset signal or the read reset signal of the memory circuit by 1H is provided.

According to the present invention, the video signal is a reproduction signal of a magnetic recording / reproducing apparatus, the read reference signal generating circuit generates a reference synchronizing signal of a servo circuit of the magnetic recording / reproducing apparatus, and the write reset signal is used. Alternatively, instead of the read reset signal, shift means is provided for shifting the reference synchronizing signal by 1H each time the detection signal is output.

[Operation] When the write reset signal and the read reset signal approach each other, the time difference between these signals falls within the predetermined range.
At this time, the detection signal is output, and the shift means
The write reset signal or read reset signal is forced to shift 1H. As a result, even if the write address and the read address of the first and second memory circuits approach each other,
These are forcibly separated by 1H to avoid overtaking and frequent overtaking.

Further, the reference synchronizing signal is forcibly shifted by 1H by the detection signal, whereby the reproduced video signal of the magnetic recording / reproducing apparatus is shifted by 1H, and the write reset signal is changed.
It is shifted by 1H. Therefore, also in this case, the first and second
It is possible to avoid overtaking write addresses and read addresses in the memory circuit, and avoid frequent overtaking.

According to the above, the capacities of the first and second memory circuits can be set to the minimum necessary for this shift,
This capacity can be significantly reduced.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a synchronous converter according to the present invention, in which 1 is an input terminal, 2 is an A / D converter,
3 is a memory circuit, 4 is a D / A converter, 5 is an output terminal, 6 is a write reference signal generating circuit, 7 is a write reset signal generating circuit, 8 is a read reference signal generating circuit, 9 is a read reset signal generating circuit, 10 is an input terminal, 11 is a decoder, 12a, 12
b is a D / A converter, 13 is a switching switch, 14 is a memory circuit, 15
Is a switching switch, 16a and 16b are D / A converters, 17 is an encoder, 18 is an output terminal, 19a and 19b are switching switches, 20 is a gate signal generating circuit, 21 is an AND circuit, 22 is a flip-flop, and 23 is an input terminal. , 24 and 25 are frequency dividing circuits, and 26 is an output terminal.

In this embodiment, a VTR reproduction signal separated into a luminance signal (hereinafter referred to as Y signal) and a color signal (hereinafter referred to as C signal) is synchronously converted through a memory circuit.

Referring to FIG. 1, first, the Y signal will be described.
The Y signal input from the input terminal 1 is supplied to the A / D converter 2 and the write reference signal generation circuit 6. The write reference signal generating circuit 6 generates a clock signal YWCK and a horizontal synchronizing signal HD which are synchronized with the Y signal, that is, have the same time axis error as the Y signal. Further, in the A / D converter 2, this Y signal is digitalized using the clock signal YWCK as a sampling pulse. The digital data of the Y signal thus obtained is sequentially written in the memory circuit 3 by using the clock signal YWCK as a write clock.
Further, the horizontal synchronizing signal HD and the clock signal YWCK are supplied to the write reset signal generation circuit 7, and the write reset signal YWRS for resetting the write address of the memory circuit 3 to the address 0 is generated.

Data reading from the memory circuit 3 is performed by the read clock YRCK output from the read reference signal generating circuit 8 and the read reset signal YRRS selected by the switching switch 19a. The read reference signal generating circuit 8 generates clock signals YRCK, CRCK and a horizontal synchronizing signal HDR which are synchronized with an external reference signal supplied from an oscillator provided inside or an input terminal 23, and outputs V through an output terminal 26.
A vertical synchronizing signal V-Sync or a composite synchronizing signal C-Sync is supplied as a reference signal to a TR capstan servo circuit (not shown). The read reset signal generation circuit 9 outputs the clock signal.
From the YRCK and the horizontal synchronizing signal HDR, n read reset signals YRRS1 to YRRSn having different phases in 1H (1 line) units are generated and supplied to the switching switch 19a. The read reset signal YRRS output from the switching switch 19a is supplied to the gate signal generation circuit 20 to generate a gate signal GATE having a pulse width centered on the read reset signal YRRS. AN
The D circuit 21 outputs a logical product signal AND of "H" of the gate signal GATE and the write reset signal YWRS from the write reset signal generation circuit 7. The flip-flop 22 is the logical product AND
A switch signal SW is generated which is triggered for each rising edge and whose level is inverted every rising edge. The switch signal SW sequentially selects and selects the input signals YRRS1 to YRRSn of the switching switch 19a.

Data is sequentially read from the memory circuit 3 by the clock signal YRCK and the read reset signal YRRS thus obtained. The read data is converted into an analog Y signal again by the D / A converter 4 using the clock signal YRCK, and output from the output terminal 5.

The above is the processing process for the Y signal, but for the C signal, the following processing is performed in a similar manner.

The C signal input from the input terminal 10 may be either a signal modulated by a color subcarrier having a frequency f _sc , or a low-frequency converted version of this modulated signal. The signals are color difference signals RY, B-
Demodulated to Y. These color difference signals RY and BY are A / D
Digitalized by the converters 12a and 12b. These A / D converters
The clock signals 12a and 12b are the clock signal CWCK generated by the write reference signal generation circuit 6. The two digitalized color difference signals are respectively supplied to the switching switch 13 and are alternately selected by the switch signal obtained by dividing the clock signal by 2 by the frequency divider 24 to perform time division multiplexing. The digital data time-division multiplexed in this way is
The write reset signal CWRS and the clock signal CWCK generated by the write reset signal generation circuit 7 from the clock signal CWCK and the horizontal synchronizing signal HD are sequentially written in the memory circuit 14.

On the other hand, in the read reset signal generation circuit 9, n read reset signals CRRS1 to CRRSn are generated by the read reference signal CRCK and the horizontal synchronizing signal HDR, one of which is a switching switch 19b controlled by a switch signal SW. When selected, the read reset signal CRRS is obtained. Data is sequentially read from the memory circuit 14 by the reset signal CRRS and the clock signal CRCK generated by the read reference signal generation circuit 8. The read data is the switching switch 15
To the color difference signals RY and BY by a switch signal obtained by dividing the read reference signal CRCK by 2 by the frequency divider 25.
Is separated into data. The data of the color difference signal RY is converted by the D / A converter 16a, and the data of the color difference signal BY is converted by the D / A converter 16b into an analog color difference signal with the reference signal CRCK as the clock. The color difference signals RY and BY obtained in this way
Is modulated by the encoder 17 and output from the output terminal 18 as a C signal.

As described above, this embodiment writes this input signal to the memory using the clock signal and the write reset signal which are synchronized with the input signal to be processed, and uses the clock signal and the read reset signal which are synchronized with another reference signal. The signal is read out from the memory by means of this, and by this means, it is possible to carry out synchronous conversion or removal of jitter.

Since the read reference signal generation circuit 8 supplies the vertical sync signal or the composite sync signal as a reference signal to the capstan servo circuit (not shown) of the VTR via the output terminal 26, the reproduced signal from the VTR is reproduced. The frequencies of the reference signal from the read reference signal generating circuit 8 are equal on average, and therefore, in this embodiment, the frequency conversion of the reproduction signal is not performed. In this embodiment, the VTR reproduction signal is processed and the Y signal and the C signal are processed by different systems. However, even if the Y signal and the C signal are processed separately, they are the same. Reference signal generation circuit for writing and reading because it has a time axis error
6, 7 can be commonly used for Y signal and C signal. In addition, input terminal 1
Since the C signal modulated from 0 is demodulated by the decoder 11 and converted into the baseband color difference signals RY and BY for processing, the sampling frequency (clock frequency) of the C signal can be set low and the memory circuit 14 Can be used efficiently and the complexity associated with processing interleaved signals can be avoided. Furthermore, the switching switch 13
The time-division multiplexing of the color difference signals RY and BY by means of can also reduce the number of memories. The switching switch 13 may be used for multiplexing at the stage of analog signals.

Next, the write reference signal generating circuit 6 and the write reset signal generating circuit 7 will be described.

The write reference signal generation circuit 6 is a normal PLL (phase locked loop) circuit. That is, the horizontal synchronizing signals PBHD and VCO separated from the Y signal input from the input terminal 1
A signal obtained by dividing the output signal of the (voltage controlled oscillator), that is, in this embodiment, if the frequency of the VCO is 4 times the frequency f _sc of the color subcarrier (4f _sc ), this signal is divided by 910 And are phase-compared, and form a negative feedback loop that controls the VCO by the phase error. this
The PLL circuit generates a horizontal synchronizing signal HD and clock signals YWCK and CWCK which are phase-synchronized with the input Y signal. Considering the frequency bands of the Y and C signals and the time division multiplexing of the C signal, the frequency of the clock signal YWCK is 4f _sc ,
The frequency of the clock signal CWCK is sufficient as f _sc .

The write reset signal generating circuit 7 is composed of a frequency dividing circuit for dividing the horizontal synchronizing signal HD and an edge detecting circuit,
The frequency division ratio is determined by the capacity ratio of the memory circuits 3 and 14. In this embodiment, assuming that the memory circuits 3 and 14 have a capacity of nH, the frequency division ratio is 1 / n and the write reset signals YWRS and CWRS of nH cycle are generated. Here, for simplification, the write reset signals YWRS and CWRS are assumed to be in phase.

Next, in the read system of the memory circuits 3 and 14, the read reference signal generation circuit 8 operates as a PLL circuit like the write reference signal generation circuit 6 when an external reference signal is input from the input terminal 23. If the external reference signal is not input, the reference horizontal synchronizing signal HDR and the read clock signals YRCK and CRCK are generated by free running. The read reset signal generation circuit 9 divides the horizontal synchronizing signal HDR by 1 / n and generates n read reset signals YRRS1 to YRRSn and CRRS1 to CRRSn which are different in phase by 1H for each of the Y signal and the C signal. .
From these n-phase read reset signals, a set of read reset signals YRRSk, CRRSk (k = 1 to n) having the same phase are selected by the switching switches 19a, 19b.

The selection of the read reset signals YRRS1 to YRRSn by the switching switch 19a, that is, the phase shift of the read reset signal YRRS will be described with reference to FIG. In the figure, for simplification, n = 4, that is, the memory capacity is set to 4H and only the phase shift of the read reset signal YRRS is shown, but the same applies to the read reset signal CRRS.

Now, assuming that the switching switch 19a in FIG. 1 selects the read reset signal YRRS1, the output signal GATE of the gate signal generation circuit 20 is before and after the read reset signal YRRS1 as shown in FIG. It is a "H" signal over the range. If the read reset signal YRRS and the write reset signal YWRS are close to each other in time and the write reset signal YWRS is included in the gate signal GATE, then AN
The output signal AND of the D circuit 21 becomes "H", and as a result, the level of the output signal of the flip-flop 22 is inverted. As a result, the switching switch 19a selects the next read reset signal YRRS2. In this way, when the approach between the read reset signal YRRS and the write reset signal YWRS is detected, the phase of the read reset signal YRRS is shifted by 1H unit, which forces the timing of each reset signal YRRS, YWRS. To avoid overtaking and overtaking by Jiuta. Further, when the gate signal AND becomes "H" from the above state, the next read reset signal YRRS3 is further selected. In this way, by selecting YRRS shifted by 1H each time the gate signal AND becomes "H", the read reset signal YRRS of the optimum phase is selected from the four phases regardless of the amount of jitter. You will be able to choose.

This is because, as shown in FIG. 3, when the shift circuit is composed of only two phases of the read reset signals YRRS1 and YRRS3 out of four phases, the shift operation does not converge between these two phases, However, this embodiment is very advantageous in comparison with this.

As described above, according to this embodiment, it is possible to automatically avoid the timing of the write address and the read address in the memory circuit, the frequent occurrence of the overtaking, and perform the synchronous conversion operation at the most stable point. Therefore, it is not necessary to adjust the phase of the advanced synchronization signal, which is required in the conventional synchronous conversion device using the line memory, and the circuit scale can be reduced.

FIG. 4 is a block diagram showing another embodiment of the synchronous converter according to the present invention, in which 27 and 28 are delay circuits, and
Portions corresponding to those in the figure are denoted by the same reference numerals and redundant description will be omitted.

In the figure, a delay circuit 27 is provided between the switching switch 19a and the gate signal generating circuit 20, and the switching switch 19b is provided.
And a delay circuit 28 is provided between the memory circuit 14 and
The other structure is the same as that of the embodiment shown in FIG.
These circuits 27 and 28 correct the time lag that occurs when the Y signal and the C signal pass through different processing paths outside the synchronous converter by adjusting the read timing from the memory circuits 3 and 14. Is. For example, when the C signal is passed through the 1H comb filter twice, the C signal is delayed by 1H with respect to the Y signal, but by delaying the read timing from the Y signal memory circuit 3 by 1H by the delay circuit 27,
The time shift between the two is corrected, and the color shift in the vertical direction of the screen is corrected.

Further, the time lag of the Y signal and the C signal in the screen direction due to the delay time of the encoder 17 and various filters adjusts the read timing of the memory circuits 3 and 14 with respect to the reference horizontal synchronizing signal HDR by the delay circuits 27 and 28. As a result, it is possible to perform correction in a digital state without image quality deterioration. In addition,
The correction accuracy in this case is that the color difference signals RY and BY have a frequency of 1 / 2f.
_The C signal sampled by _sc is about 0.6 μsec,
It can be inadequate. In such cases, the memory circuit
A latch circuit for latching the data read from 14 with a clock signal faster than 1/2 f _sc may be provided, and the D / A converters 16a and 16b may similarly be supplied with a fast clock.
Alternatively, it is possible to operate the processing system of the C signal with the same clock as the Y signal.

The delay circuits 27 and 28 may be provided inside the read reset signal generation circuit 9. FIG. 5 is a block diagram showing the configuration of the read reset signal generating circuit 9 in this case, in which 29 to 31 are input terminals, 32a and 32b are n frequency dividing circuits, and 33a and 33b.
Is an edge detection circuit, 34 is an Ex-OR (exclusive OR circuit), 40
Is a latch circuit.

In the figure, a read reference signal generating circuit 8 (FIG. 1)
The horizontal synchronizing signal HDR output from the input terminal 30 is input to the horizontal synchronizing signal HDR.
On the other hand, it is delayed by the delay circuit 28 and supplied to the n frequency dividing circuit 32b. In the n frequency dividers 32a and 32b, n-phase pulse signals φ1 to φn whose phases are shifted by 1H from each other are generated based on the delayed horizontal synchronizing signals HDR. These pulse signals .phi.1 to .phi.n have a cycle of nH and are supplied to the edge detection circuits 33a and 33b to generate n-phase read reset signals YRRS1 to YRRSn and CRRS1 to CRRSn, respectively. Even with such a configuration, it is possible to digitally correct the phase shift between the Y signal and the C signal.

In the embodiment of FIG. 5, since the Y signal and the C signal are separately provided with frequency dividers, it is necessary that the frequency division outputs for the Y signal and the C signal have substantially the same phase. . Therefore, the Ex-OR 34 and the latch circuit 35 are provided. E
The x-OR34 compares the phase of the pulse signals φ1 which should be in substantially the same phase from the n frequency dividers 32a and 32b, and when the phases of both are different, "H"
The signal of is output. Since the horizontal synchronizing signals supplied to the respective n frequency dividers 32a and 32b are delayed by the delay circuits 27 and 28 having different delay amounts, these pulse signals φ1 never have the same phase, and the Ex-OR34 Does not always output the "L" signal.

However, the delay circuits 27 and 28 for correcting the phase shift between the Y signal and the C signal delay the horizontal synchronization signal HDR supplied from the input terminal 30 by a little less than 1H, and as a result, the horizontal synchronization signal HDR is delayed. It acts to advance the phase of HDR. Therefore, the rising edges of the output signals of the delay circuits 27 and 28 are always on the same delay side with respect to the original horizontal synchronizing signal HDR. Therefore, by latching the output signal of the Ex-OR 34 with the original horizontal synchronizing signal HDR in the latch circuit 35, the n dividers 32a, 3a
When the output pulse signal φ1 of 2b has substantially the same phase, the output signal RESET of the latch circuit 35 is always "L". When these pulse signals .phi.1 are not substantially in phase, the output signal RESET of the latch circuit 35 becomes "H", whereby the frequency divider is reset. This reset operation causes the n dividers 32a, 32a
These output pulse signals φ regardless of the initial state of b
1 is stably in substantially the same phase, and as a result, the reset signal shift operation will not be erroneous.

FIG. 6 is a block diagram showing another embodiment of the synchronous converter according to the present invention, in which 36 and 37 are delay circuits and 38a and 3a.
8b is a switching switch, 39 is an input terminal, and the parts corresponding to those in FIG.

In this figure, this embodiment is one in which delay circuits 36, 37 and switching switches 38a, 38b are added to the embodiment shown in FIG. 4, which enables simultaneous monitoring of VTRs and recording images. It is the one that enables the immediate check. Here, the simultaneous monitor means that when the VTR has a function of reproducing the recorded video signal while recording the signal, it means that the video signal being recorded and the reproduced video signal are combined and displayed on the same screen at the same time. Say.

The delay circuits 36 and 37 delay the read reset signal for horizontal shifting of the image on the reproduction screen, and the delay amounts are the same. Switch 38
Reference numerals a and 38b are switches for selecting whether or not the read reset signal output from the delay circuits 27 and 28 passes through the delay circuits 36 and 37 by the control signal SM input from the input terminal 39.

The simultaneous monitor function cannot be realized without synchronizing the reproduced video signal with the recorded video signal as a reference.
In this embodiment, synchronization can be performed by using the recorded video signal as the reference signal, and the recorded video signal and the reproduced video signal can be displayed simultaneously on the same reproduction screen.

By the way, the main purpose of the simultaneous monitor function is to confirm the recorded image immediately, but if the simultaneous monitor is to set a window in the playback screen and display the image by the playback video signal in this window part, The image of the playback video signal that the user of the VTR wants to display in the window of the playback screen is the center of the screen of the image of the video signal being recorded. By confirming, it is possible to most safely prevent a recording error due to poor adjustment or head polishing.

In this embodiment, during such simultaneous monitoring, the switching switch 38 is controlled by the control signal SM input from the input terminal 39.
By switching both a and 38b from the upper side to the lower side and selecting the read reset signal that has passed through the delay circuits 36 and 37, the reproduced image is horizontally shifted. The image shift amount is 1 / 3H to 1 / 4H, and the horizontal length of the window is 1/2 of the screen.
By setting it to about 1/4, the central portion of the reproduced image and the recorded image can be displayed at the same time, which is suitable for checking the recorded image by the simultaneous monitoring function.

FIG. 7 is a block diagram showing still another embodiment of the synchronous converter according to the present invention, in which 40 is an n-phase delay circuit, 41 is a switching switch, and the same symbols are given to the portions corresponding to FIG. A duplicate description will be omitted.

In this embodiment, instead of shifting the read reset signals YRRS and CRRS as in the above embodiments, the reference vertical synchronizing signal V-Sync or composite synchronizing signal C-Sync supplied to the capstan servo circuit of the VTR is used. It shifts by 1H unit.

In FIG. 7, the vertical synchronizing signal V-Sync or the composite synchronizing signal C-Sync generated by the read reference signal generating circuit 8 is n.
The n-phase vertical sync signal V-Sync or the composite sync signal C-Sync, which are supplied to the phase delay circuit 40 and have different phases in units of 1H, are generated. These synchronizing signals are supplied to the switching switch 41, and one of them is selected. The control signal of the switching switch 41 is the output signal of the flip-flop 22, and the level is inverted every time the write reset signal YWRS and the read reset signal YRRS approach each other, as in the previous embodiments. Then, every time the output signal of the flip-flop 22 becomes "H", the switching switch 41 is switched, and the phase of the vertical synchronizing signal V-Sync or the composite synchronizing signal C-Sync output from the output terminal 26 is shifted by 1H, It is supplied as a reference signal to the capstan servo circuit (not shown) of the VTR.

In this way, the vertical sync signal V-Sync or composite sync signal C-Sync supplied to the capstan servo circuit of the VTR is
By shifting in 1H units, the phase of the VTR playback signal input from input terminals 1 and 10 is also shifted in 1H units, and as a result, the write reset signal YWRS generated in synchronization with this input signal is in 1H units. Shift with. Even if such a method is used, the reset signal can be shifted, and as in the previous embodiment, the reset signal can be overtaken and the frequent occurrence of the reset signal can be avoided.

FIG. 8 is a block diagram showing still another embodiment of the synchronous converter according to the present invention, in which 42a and 42b are switching switches, and the parts corresponding to those in FIG.

Also in this embodiment, the write reset signal is shifted by 1H as in the embodiment shown in FIG.

In FIG. 8, the write reset signal generation circuit 7 is n
Phase write reset signals YWRS1 to YWRSn and CWRS1 to CWRSn are generated and selected one by one by switches 36a and 36b. As a result, the write reset signals YWRS and CWRS are set to 1
Shift in H units. By shifting the write reset signal in this manner, the same effect as that of the previous embodiment can be obtained.

Further, in this embodiment, the gate signal GATE supplied to the AND circuit 21 is created from the write reset signal YWRS, but this gate signal GATE may also be created by the read reset signal YRRS. In addition, write reset signal CWRS and read reset signal CR
The same effect can be obtained by using RS and.

FIG. 9 is a block diagram showing still another embodiment of the synchronous converter according to the present invention, in which 43 is a timer circuit and 44 is an output terminal, and the parts corresponding to those in FIG. There is.

In this embodiment, as shown in FIG. 9, a timer circuit 43 driven by the output signal AND of the AND circuit 21 as a trigger signal and an output terminal 44 are added to the embodiment shown in FIG. The timer circuit 43 counts the elapsed time after the output signal AND of the AND circuit 21 becomes "H", and outputs a signal to the output terminal 44 when a certain set time is exceeded. If the set time is set to, for example, several frames, it can be known from the output signal from the output terminal 44 that the shift operation of the read reset signal is completed and the stable synchronous conversion operation state is achieved.

As an application example, if the output terminal 44 is connected to a VTR miute circuit or a blue back generation circuit, etc., the read reset signal will be generated due to unstable synchronization until the capstan servo circuit locks when the VTR is started. Since it is possible to prevent the user from seeing the disturbance of the screen caused by the continuous shift operation of, it is effective in relieving the user from discomfort.

It should be noted that such a timer circuit can be provided in the above-mentioned embodiments other than the embodiment shown in FIG. 1 and the same effect can be obtained.

[Effects of the Invention] As described above, according to the present invention, the timing of the write or read reset signal is set every time when the time proximity of the write reset signal and the read reset signal is detected.
Since it shifts in 1H units, it is possible to overtake write and read reset signals with the minimum required memory capacity.
Frequent overtaking can be automatically avoided and synchronous conversion can be performed at the most stable point.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a synchronous converter according to the present invention, FIG. 2 is a waveform diagram showing signals of respective parts in FIG. 1, and FIG. 3 is a read reset of the embodiment shown in FIG. FIG. 4 is a block diagram showing a signal shift operation, FIG. 4 is a block diagram showing another embodiment of the synchronous converter according to the present invention, and FIG. 5 is a read reset signal generating circuit of yet another embodiment of the synchronous converter according to the present invention. FIGS. 6 to 9 are block diagrams showing yet another embodiment of the synchronous converter according to the present invention, and FIG. 10 is a write reset signal and a read reset signal overtaking in the conventional synchronous converter. FIG. 6 is a diagram showing an influence caused by overtaking. 1 ... input terminal, 3 ... memory circuit, 5 ... output terminal,
6 ... Write reference signal generation circuit, 7 ... Write reset signal generation circuit, 8 ... Read reference signal generation circuit, 9 ...
Readout reset signal generation circuit, 10 …… input terminal, 14 ……
Memory circuit, 18 ... Output terminal, 19a, 19b ... Switching switch, 20 ... Gate signal generating circuit, 21 ... AND circuit, 22 ...
… Flip flip, 27,28,36,37 …… Delay circuit, 38a, 3
8b ... switching switch, 40 ... n phase delay circuit, 41 ... switching switch, 42a, 42b ... switching switch, 43 ... timer circuit, 44 ... output terminal.

Claims (13)

(57) [Claims] 1. A first and second converter for converting a luminance signal and a color signal of a video signal into a digital luminance signal and a digital color signal, respectively.
Analog / digital conversion circuit, a write reference signal generation circuit for generating a write reference signal in synchronization with the video signal, and a write reset signal generation for generating the first and second write reset signals based on the write reference signal. A circuit, a read reference signal generation circuit, and first and second read circuits based on the read reference signal.
Read reset signal generating circuit for generating the read reset signal, and the write address is reset by the first write reset signal, the digital luminance signal is written in synchronization with the write reference signal, and the first read reset signal is generated. A first memory circuit for resetting the read address with a signal and reading the digital luminance signal written in synchronization with the read reference signal; and a write address for resetting the write address with the second write reset signal. A second memory circuit in which the digital color signal is written in synchronization with the signal, the read address is reset by the second read reset signal, and the digital color signal written in synchronization with the read reference signal is read out; , The digital luminance signal and the digital color signal read from the first and second memory circuits, First converted into s analog signal, a second
And a digital / analog conversion circuit for obtaining a luminance signal and a chrominance signal in synchronization with the read reference signal, the time difference between the first write reset signal and the first read reset signal. Alternatively, detecting means for detecting a time difference between the second write reset signal and the second read reset signal and outputting a detection signal when the time difference is within a predetermined range, and a detecting means for each time the detection signal is output. 1. A synchronous converter comprising: first and second shift means for shifting the phases of the first and second read reset signals by 1H (where 1H is a horizontal scanning period). 2. The read reset signal generating circuit according to claim 1, wherein the cycle is nH based on the read reference signal.
(Where n is a positive integer) and generates a first and a second signal group consisting of n signals each having a phase difference of 1H from each other, and the first shift means generates the read reset signal generation circuit and the detection signal. A first switching switch means controlled by a signal to select one signal of the first signal group, the second shift means providing the read reset signal generating circuit and the detection signal. And a second switching switch means for controlling one of the second signal groups to be controlled by the second switching switch means. 3. The first and the second according to claim 1 or 2,
2. The synchronous converter according to claim 1, wherein the shift directions of the first and second read reset signals by the shift means are the same. 4. The gate signal generating means for generating a gate signal from the first or second read reset signal according to claim 1, and the first or first gate signal generating means within the period of the gate signal. 2. A synchronous conversion device comprising: a gate means which uses the write reset signal of 2 as the detection signal. 5. A first and a second converting a luminance signal and a color signal of a video signal into a digital luminance signal and a digital color signal, respectively.
Analog / digital conversion circuit, a write reference signal generation circuit for generating a write reference signal in synchronization with the video signal, and a write reset signal generation for generating the first and second write reset signals based on the write reference signal. A circuit, a read reference signal generation circuit for generating a read reference signal, a read reset signal generation circuit for generating first and second read reset signals based on the read reference signal, and a first write reset signal. The write address is reset and the digital luminance signal is written in synchronization with the write reference signal. The read address is reset by the first read reset signal and the digital luminance signal is written in synchronization with the read reference signal. A first memory circuit from which is read,
The write address is reset by the second write reset signal, the digital color signal is written in synchronization with the write reference signal, and the read address is reset by the second read reset signal and synchronized with the read reference signal. A second memory circuit from which the digital color signal written by the above is read, and the digital luminance signal and the digital color signal read from the first and second memory circuits are converted into analog signals, respectively. A first digital reset signal and a first read reset signal in a synchronous conversion device that includes a second digital / analog conversion circuit and obtains a luminance signal and a chrominance signal in synchronization with the read reference signal. Or a time difference between the second write reset signal and the second read reset signal is detected and the time difference is within a predetermined range. A detection means for outputting a detection signal, and first and second shifting means for shifting the first and second write reset signals by 1H each time the detection signal is output. Synchronous converter. 6. The write reset signal generating circuit according to claim 5, wherein the write reset signal generating circuit comprises n signals each having a period of nH and a phase difference of 1H from each other based on the write reference signal.
And a first switching means for generating a signal group of the first reset means for selecting one signal of the first signal group controlled by the write reset signal generating circuit and the detection signal. The second shift means includes the write reset signal generating circuit, and second switching switch means which is controlled by the detection signal and which selects one signal of the second signal group. A synchronous conversion device comprising: 7. The first and second devices according to claim 5 or 6,
2. The synchronous converter according to claim 1, wherein the shift directions of the first and second write reset signals by the shift means are the same. 8. The gate signal generating means for generating a gate signal from the first or second write reset signal, and the first or first detecting means within the period of the gate signal according to claim 5. 2. A synchronous conversion device comprising a gate means for using the read reset signal of No. 2 as the detection signal. 9. The first and the second according to claim 1 or 5,
The write reset signals of are in substantially the same phase, and
A synchronous converter in which the second read reset signals have substantially the same phase. 10. The first and second delay means for delaying each of the first and second write reset signals or each of the first and second read reset signals according to claim 1, A synchronous converter capable of compensating for a time difference between a luminance signal and the color signal. 11. The read reference signal generating circuit according to claim 1, wherein the read reference signal generating circuit generates a reference synchronizing signal of a servo circuit of a magnetic recording / reproducing apparatus, and the first and second write reset signals or the first write reset signal. A delay circuit for delaying each of the first and second read resets by the same amount is provided, and the luminance signal and the chrominance signal supplied to the first and second analog / digital conversion circuits are reproduction signals of the magnetic recording / reproducing apparatus. A luminance signal and a color signal to be recorded in the magnetic recording / reproducing device,
By supplying the luminance signal and the chrominance signal of the first and second digital / analog conversion circuits to the same monitor with a predetermined phase difference by the delay circuit, the recording screen of the magnetic recording / reproducing device is displayed on the same screen. A synchronous conversion device characterized in that a playback screen and a playback screen can be simultaneously displayed. 12. A first and a second analog / digital conversion circuit for converting a luminance signal and a color signal of a video signal reproduced from a magnetic recording / reproducing device into a digital luminance signal and a digital color signal, respectively, and the image. A write reference signal generating circuit for generating a write reference signal in synchronism with the signal, and a write reset signal generating circuit for generating first and second write reset signals for a luminance signal and a chrominance signal based on the write reference signal A read reference signal generation circuit for generating a read reference signal and a reference synchronization signal; and a read reset signal generation circuit for generating a read reset signal based on the read reference signal,
The write address is reset by the first write reset signal, the digital luminance signal is written in synchronization with the write reference signal, the read address is reset by the first read reset signal, and the read reference signal is synchronized with the read reference signal. A first memory circuit from which the written digital luminance signal is read, and a write address is reset by the second write reset signal, and the digital color signal is written in synchronization with the write reference signal. A second memory circuit in which the read address is reset by the read reset signal and the digital color signal written in synchronization with the read reference signal is read out, and the digital read out from the first and second memory circuits First and second digital / analog conversion circuits for converting the luminance signal and the digital color signal into analog signals, respectively And a first and second reset signals and a first write reset signal or a second write reset signal and a first write reset signal and a second write reset signal which are synchronized with the read reference signal. 2 detecting means for detecting a time difference from the read reset signal and outputting a detection signal when the time difference is within a predetermined range; and the reference output by the read reference signal generating circuit every time the detection signal is output. A synchronization conversion device comprising a shift means for shifting a synchronization signal by 1H. 13. The shift means according to claim 12,
It comprises means for generating n signals whose phases are sequentially different by 1H based on the reference synchronization signal, and a switching switch controlled by the detection signal to select one of the n signals. A synchronous conversion device characterized by.