JPH039429Y2 - - Google Patents

Description

[Detailed Description of the Invention] Industrial Application Field The present invention relates to a clock signal generation circuit used in a high-definition digital television receiver.

BACKGROUND TECHNOLOGY Recently, as a method for improving the image quality of television signals on the receiver side, a digitalized composite video signal is stored in line memory or field memory for several lines or fields. 2. Description of the Related Art Digital television receivers that perform digital signal processing such as line-to-line or field-to-field calculations are being developed.

In such digital television receivers, the sampling pulse used for A/D conversion of the composite video signal is conventionally set at four times the color subcarrier frequency by feeding the color burst in the composite video signal to a phase lock loop. It was generating things.

However, the conventional method described above has a problem in that it cannot be applied to monochrome television signals that do not include color bursts.

In addition, in the conventional method described above, a horizontal synchronization signal is generated simultaneously by frequency-dividing the sampling pulse, but in the case of a composite video signal played from a VTR, the time axis deviation is relatively large, so such a composite When a video signal is processed using a horizontal synchronization signal obtained by frequency division of a sampling pulse and which has little deviation on the time axis, there is also the problem that image shake occurs.

Problems to be Solved by the Invention The present invention was devised in view of the problems of the prior art described above, and its purpose is to always provide optimal sampling pulses according to the type and characteristics of the television signal to be processed. An object of the present invention is to provide a highly versatile clock signal generation circuit capable of selectively supplying a clock signal and a horizontal synchronization signal.

Structure of the Invention The present invention which achieves the above object includes a first phase lock loop that generates a sampling pulse and a horizontal synchronization signal from a color burst, and a second phase lock loop that generates a sampling pulse and a horizontal synchronization signal from a horizontal synchronization signal. The lock loop and the selection means for selectively outputting one of the sampling pulse and the horizontal synchronization signal generated by the first and second phase lock loops according to the type of processing target.

Hereinafter, the present invention will be explained in more detail with reference to Examples.

Embodiment of the invention FIG. 1 is a block diagram showing the configuration of an embodiment of the invention. In FIG. 1, 1 is a burst gate, 2 is a burst amplification circuit, 3 is a first phase lock loop, 4 is a second phase lock loop, 5 is a clamp circuit, 6 is a synchronous separation circuit, 7 is a delay circuit, 8 , 9 is a frequency dividing circuit, 10 is a color killer circuit, 11 is an OR gate, 12, 13, and 14 are selection signals, and 20 to 24 are switch circuits.

Composite video signals can be processed using line memory or frame memory.
The signal is branched from a signal processing system (not shown) including a memory and input to the burst gate 1. burst·
The color burst signal extracted by the gate 1 is amplified by the burst amplification circuit 2 and then supplied to the first phase lock loop 3. At the same time, the composite video signal is also input to the clamp circuit 5. From the composite video signal clamped by the clamp circuit 6, only the horizontal synchronization signal is extracted by the synchronization separation circuit 6, and the extracted horizontal synchronization signal is supplied to the second phase lock loop 4. Further, the horizontal synchronization signal extracted by the synchronization separation circuit 6 passes through a delay circuit 7 and drives the burst gate 1.

The color burst signal supplied to the first phase lock loop 3 is outputted to the phase detection circuit 31.
Color subcarrier frequency fsc which is the output of the frequency dividing circuit 35
Phase detection is performed using the This phase detection output is integrated by an integrating circuit 32 and then controls the oscillation frequency of a voltage controlled oscillation circuit (VOC) 33. This voltage controlled oscillation circuit 33 outputs a clock signal (8fsc) having a frequency eight times the color subcarrier frequency. This 8fsc is frequency-divided by two in the next-stage frequency divider circuit 34 to generate a clock signal (4fsc) having a frequency four times the color subcarrier frequency. The next-stage frequency divider circuit 35 further divides this 4fsc by 4 to output a clock signal (fsc) at the color subcarrier frequency. This fsc is fed back to the phase detection circuit 31.

8fsc generated within the first phase lock loop 3
is supplied to one input terminal of the switch 20, and 4fsc is supplied to one input terminal of the switch 21 and the frequency divider circuit 8. 4fss supplied to frequency divider circuit 8
is frequency-divided by 455 to become a clock signal 2fh having a frequency twice the horizontal frequency, and is supplied to one input terminal of the switch 22 and the frequency divider 9. A horizontal frequency clock signal (fh) generated by the divide-by-2 circuit 9 is supplied to one input terminal of the switch 23.

On the other hand, the horizontal synchronization signal supplied to the second phase lock loop 4 is transmitted to the phase detection circuit 41 by two
Phase detection is performed using the horizontal frequency clock signal fh, which is the output of the frequency dividing circuit 46, as a reference. This phase detection output is integrated by an integrating circuit 42 and then controls the oscillation frequency of a voltage controlled oscillation circuit (VCO) 43. This voltage controlled oscillation circuit 43, like the voltage controlled oscillation circuit in the first phase lock loop, outputs a clock signal (8fsc) having a frequency eight times the color subcarrier frequency. This 8fsc is frequency-divided by two in the next-stage frequency divider circuit 44 to generate a clock signal (4fsc) having a frequency four times the color subcarrier frequency. The frequency dividing circuit 45 at the next stage divides this 4fsc by 455 and outputs a clock signal (2fh) having a frequency twice the horizontal frequency. This 2fh is the next stage 2
The frequency is further divided by two in the frequency divider circuit 46 to obtain a horizontal frequency clock signal (fh), which is sent to the phase detection circuit 4.
Returned to 1.

8fsc generated within the second phase lock loop 4
is supplied to the other input terminal of switch 20, and 4fsc is supplied to the other input terminal of switch 21. Further, the output 2fh of the frequency dividing circuit 45 is supplied to the other input terminal of the switch 22. fh generated by the divide-by-2 circuit 46 is supplied to the other input terminal of the switch 23.

In this way, only one of the four sets of clock signals 8fsc, 4fsc, 2fh, and fh generated in the first and second phase lock loops 3 and 4 is output from one of the phase lock loops. is selected as the output from this clock signal generation circuit by the selection signal 13 supplied to the switches 21-23.

That is, in the case of a color television signal, each clock signal generated by the first phase lock loop 3 is selected by the switches 20-23. On the other hand, in the case of a monochrome television signal or during the processing of a color television signal, the color killer circuit 10
When the switch 2 is activated, the selection signal 13 is inverted by the manual selection signal 12 input to the OR gate 11 or the color killer signal, and the switch 2 is activated.
Switch between 0 and 23. Therefore, in this case each clock signal generated by the second phase lock loop 4 is selected. Furthermore, even when digitizing a composite video signal that has been played back from a VTR and has not been subjected to time base correction processing, the horizontal synchronization signal has a relatively large deviation on the time axis. The clock signal generated by the phase lock loop 4 is selected.

Further, of the clock signals 8fsc and 2fh selected as described above, a switch 24 which is switched by a manual selection signal 14 selects whether or not the output thereof is appropriate. That is, when performing digital processing for each odd and even field, the switch 24 is opened by the manual selection signal 14, and the output of 8fsc and 2fh is blocked. On the other hand, if a memory with a capacity that can store at least one frame's worth of signals consisting of odd and even fields is provided and sequential scanning A/D conversion is performed for all lines within one frame, 4fsc for sampling and In addition to fh, 8fsc and 2fh for use in time axis compression are output when the switch 24 is closed.

Such 8fsc and 2fh clock signals are not limited to this example, but are also used when performing a line memory type progressive scanning A/D, for example, as seen in Japanese Patent Application No. 156890/1983 for "Progressive Scanning Conversion Device". The same applies.

Although an example has been shown above in which the frequency of the sampling pulse for A/D conversion is four times the color subcarrier frequency, it can also be set to an appropriate integer multiple, such as twice the color subcarrier frequency.

Effects of the invention As explained in detail above, the invention provides two phase-locked loops that generate clock signals from the color burst and horizontal synchronization signals, respectively, and adjusts the timing according to the type and characteristics of the digitization processing target. Since it is configured to selectively output a clock signal from either system, it has the advantage of being extremely versatile.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. 3...First phase lock loop, 4...Second phase lock loop, 8, 9...Frequency divider circuit, 10...
...color killer circuit, 12,14...manual selection signal, 20-24...switch circuit.

Claims (1)

[Claims for Utility Model Registration] In a clock signal generation circuit that generates a sampling pulse and a horizontal synchronization signal having a frequency that is an integral multiple of the color subcarrier frequency of a television signal, the sampling pulse and the horizontal synchronization signal are generated from a color burst of a composite video signal. a first phase-lock loop that generates a horizontal synchronization signal; a second phase-lock loop that generates the sampling pulse and the horizontal synchronization signal from the horizontal synchronization signal of a composite video signal; and the first and second phase-lock loops. Selectively digitize one of the set of the generated sampling pulse and horizontal synchronizing signal depending on the type of the television video signal, including whether or not the television video signal to be digitized is a playback signal from a video tape recorder. 1. A clock signal generation circuit for a digital television receiver, comprising: selection means for outputting a clock signal to a digital television receiver.