JPS583482A - Video signal digital processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an apparatus for digitally processing video signals, and also to a television signal receiver comprising such an apparatus.

For example, in television signal transmission systems, when a line processing sequence is required (this means that the original video signal is stored in a storage device and after processing the video signal is processed with a delay of one or more line periods). (meaning to regenerate the signal), it is necessary to introduce a sampling clock signal into this television signal transmission system.0 Line-by-line sampling operation bias that may produce horizontal stripes in the television image In order to eliminate this shift, the locked signal is formed by a phase-locked loop whose oscillation frequency is controlled by a DC voltage, as shown in Figure 1 and explained in more detail below. - a frequency divider that adjusts this oscillation frequency to the line frequency, and a phase comparison that controls the oscillation frequency and produces a DC voltage that equalizes the phase of the line synchronization signal and the signal obtained by frequency division from the oscillation signal. and a filter that prevents sudden fluctuations from occurring due to integration.

However, the stability of the oscillator is usually insufficient to obtain a defect-free display of the television picture between two successive comparisons. For example, when digitizing and processing a composite video signal, instantaneous instability of the oscillator will appear as phase transients in the signal to be displayed after one processing, and these will appear in the image after demodulation as l-, go-on. It appears as a very noticeable blemish. Furthermore, it is highly sensitive to disturbances from the power supply. These disturbances are difficult to remove;
It becomes too expensive to mass produce.

SUMMARY OF THE INVENTION It is an object of the invention to provide a video signal digital processing device of the aforementioned kind, which minimizes the above-mentioned disadvantages, has a high degree of stability, is easy to use and is compatible with mass-produced equipment. Yes, the present invention includes a synchronization separation circuit that separates a line synchronization signal from an input video signal, a digital storage device for this input video signal, a write control circuit that writes to this storage device, and a digital storage device that stores data in the storage device. A video signal digital processing device comprising a processing circuit for processing a signal output from the storage device and a continuous output control circuit for reproducing an output video signal by sequentially inputting the output video signal from the storage device, the video signal digital processing device is configured to process a line synchronizing signal. An independent clock circuit is provided, the clock circuit having an oscillator, the output signal of the oscillator being supplied to a write control circuit, a continuation control circuit, and a delay counter, the delay counter being The line synchronization signal is configured to provide a delay equal to an integral multiple of the television line period, and the output signal of the synchronization separation circuit for separating the line synchronization signal is supplied to the write control circuit and after passing through a delay counter. It is characterized in that only the output signal is supplied to the continuous output control circuit.

The line sync signal separated from the human video signal is 64μ
Since there is an instantaneous fluctuation (jitter) near the end of the theoretical line period of seconds, the start of the write control circuit that writes into the storage device (memory) is also 1 minute from the theoretical line period.
It becomes irregular at instants that are shifted by a sampling clock period or more. If the start-up of the readout control circuit for successive reading of the storage device is performed by the same synchronization signal separated from the original video signal, the phase shift of the synchronization signal for each line of the displayed video signal will be John may appear in the image. However, by providing a delay counter, it is possible to generate a starting pulse for the read control circuit that is delayed by an integral multiple of the line period with great precision with respect to the start pulse of the write control circuit, thus starting the write process. Since any shift in time will occur in the succession process as well, defects due to this shift will not occur in the image.

In the known video signal digital processing device shown in FIG. 1, a video signal supplied to a terminal r is converted from analog to digital by a converter 10 and then stored in a storage device 11. Circuit l! This processing operation in this case is not so important and does not constitute the essence of the present invention, nor does it limit the present invention, so a description thereof will be omitted. After passing through 18, the output video signal is played back to terminal S. Sync separator 1
A sampling clock signal synchronized with the line synchronization signal produced by 4 is formed by a phase-locked loop with a phase comparator 15. A first input terminal of the phase comparator 16 is supplied with the line synchronization signal, and a second input terminal is supplied with the output signal of this phase-locked loop originating from a circuit 17, as will be explained later. This phase-locked loop further includes an oscillator 16 whose oscillation frequency is controlled via a filter 19 by the DC output voltage of the comparator IIs.
is provided. The circuit 17 is a frequency divider and continuous output control circuit, and the output terminal of this circuit 17 is connected to the second input terminal of the comparator 1815 and is also connected to the input terminal of the write control circuit 18 in order to start the write control circuit 18. (the write control circuit itself is connected to the storage device 111 and the processing circuit 12), and is further connected to the storage device 11. A filter 19 is provided between the comparator 15 and the oscillator 16 and absorbs sudden excessive fluctuations due to examination of the amount of phase shift in different lines (horizontal scan II).

The device according to the invention shown in FIG. 2 includes the elements 10° 11.1! of FIG. ,
la, 14 and 18.

The device shown in Figure 2 differs only in the clock circuit, which uses a stable oscillator 2 such as a crystal oscillator.
0, and the delay caused by the line frequency N-21 is equal to 64 μsec (the duration of the line). Delay counter 21 and write control circuit 1
The start of 8 is carried out by the line sync signal generated by the sync separator 14, and precisely at the end of the delay caused by the read control circuit 2.9 start G counter 21, the line sync signal starts the write control. This occurs 64 microseconds after being applied to circuit 18.

By configuring the video signal digital processing equipment in this way, any instability (or jitter) that may adversely affect the line sync signal will not have any adverse effect on the quality of the final television picture. It will no longer affect you. The reason for this is that, under any conditions, the video signal can be reproduced at the terminal S by continuously reading out data from the memory device 11 with a fixed delay time relative to the moment it was written to the memory device 11. Also, any phase deviation that may cause the starting instant of the counter 21 and the write control circuit 18 to be 0iis will also cause the starting instant of the successive control circuit to be exactly the same as the instant mentioned above, except for a certain delay time. , so that the effects of this shift are no longer visible on the display device.

It goes without saying that the present invention is not limited to the above-mentioned example and can be modified in various ways. For example, it is clear that the delay imposed by counter 1N is not limited to a value of 64 μsec, but can be any other value that is a multiple of this value. That is, this delay time can be made exactly equal to an integer multiple of the line period.

The present invention is suitable for use in an encoding or decoding device for encoded television. FIG. 3 shows an example of a decoding device using the device of the present invention, which, as in the video signal digital processing device described above, includes converters lO and 18, and a digital storage device t (this digital storage device is , consisting of two parallel memory devices 1181 and 82 which are controlled by an address switching circuit δ8 and alternately write and read depending on the position of the switch, during the occurrence of a line synchronization pulse preceding the video signal. (direct connection between converters IO and 18), synchronous separator 14, oscillator 20 and one write control circuit 1
8, a succession control circuit z2, and a delay counter z1, and the decoding device further includes a circuit 80 for adapting the receiver to encoded transmission, which circuit 80:
The present invention is composed of an input circuit 84 which is a personal input device for the user, a pseudo random number generator 85 that receives a line synchronization signal coming from the 1 synchronization separator 14, and a decoding circuit 86. The invention also relates to the aforementioned television receiver having a video signal digital processing device or to a decoding device which itself has a video signal digital processing device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a conventional video signal digital processing device, FIG. 2 is a block diagram showing an example of a video signal digital processing device according to the present invention, and FIG. 8 is a block diagram showing an example of a video signal digital processing device according to the present invention. FIG. 2 is a block diagram illustrating an example of a decoding device to which the device is applied. lO...Analog-digital converter 11...Storage device lz...Processing circuit 1B
03. Digital-analog converter 14... Synchronization separator 1b... Phase comparator 16... Oscillator 1
7... Frequency division and readout control circuit 18
...Write control circuit 19...Filter 20.
... Stable oscillator 31 ... Delay counter z2 ... Read control circuit 211, 8! ...Storage device δ8・
...Address switching circuit 84...
・Input circuit 85... Pseudo-random number generator '86... Encoding circuit patent applicant To La Radiotechnique curve Φ

Claims (1)

[Claims] 1. A synchronization separation circuit (14) that separates a line synchronization signal from an input video signal, a digital storage device for this input video signal, a write control circuit (18) that writes to this storage device, and a A video signal digital processing device comprising a processing circuit (12) for processing the output video signal, and a readout control circuit (22) for reading the output video signal from the storage device and reproducing the output video signal. The device comprises a clock circuit which does not depend on the line synchronization signal, and the i-c circuit has an oscillator (20), the output signal of which is sent to the write control circuit (18), the output control circuit (22) and the output control circuit (22). the delay counter (21) is configured to provide the line synchronization signal with a delay equal to an integral multiple of the television line period;
The output signal of the synchronization separation circuit (14) that separates the line synchronization signal is directly supplied to the write control circuit (18), and after passing through the delay counter (81), it is supplied to the continuation control circuit (22). A video signal digital processing device characterized in that: