JPH01220996A - High speed phase matching circuit - Google Patents

Abstract

PURPOSE:To suppress color disturbance of a picture by controlling the delay quantity of a video signal in response to error information obtained through the phase comparison of the reference signal and the phase of a burst signal. CONSTITUTION:A phase detector 67 detects an error between a burst phase of a video signal read from a memory 32 and a phase of a reference signal being the result of frequency division of an output from a reference oscillator 51. That is, the time base fluctuation of a readout data from the memory 32 is corrected but there is a case that the relation between the readout timing and the burst is not necessarily best. Thus, the reference signal in a frequency of fsc being the result of frequency-division of the oscillation signal (4fsc) representing the reference of the readout by a frequency divider 66 and the phase error of the burst signal extracted by a burst gate circuit 65 is detected to obtain the video signal in the best phase relation in a selector 64. Then the delay of the video signal is controlled in response to the error information. Thus, even with the special effect reproduction applied to the circuit, the color disturbance in the picture is minimized.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention provides a method for high-speed phase alignment that is effective when used in a device that reproduces a video signal recorded on a recording medium such as a disk or tape. Regarding circuits.

(Prior art) When reproducing and processing a video signal recorded on a video tape recorder or laser disc, the chroma signal (especially burst signal) of the video signal and the reference signal (3.58 MH2) generated inside the processing circuit are used. It is necessary to maintain a constant phase relationship with

Therefore, normally, a phase control means as shown in FIG. 5 is provided in the video signal path to match the phases of the video signal and the reference signal.

The video signal at the input terminal 11 is led out to the output terminal 12 and is also supplied to the sync separation circuit 13 .

The sync separation circuit 14 separates the horizontal sync signal from the input video signal, delays it, generates a burst gate pulse, and supplies it to the burst gate circuit 14 . The burst signal extracted by the burst gate circuit 14 is supplied to one side of the phase comparator 15. The other side of the phase comparator 16 has
A reference signal from a voltage controlled oscillator 16 using a crystal is supplied. The phase error information obtained by the phase detector 16 is then given to a control terminal of the voltage controlled oscillator 16 via a low-pass filter 17.

As a result, the oscillation frequency of the voltage controlled oscillator 16 is synchronized in phase with the color burst signal of the input video signal, and is output to the output terminal 18. In other words, the phases of the burst signal of the video signal at the output terminal 12 and the reference signal at the output terminal 18 are matched.

(Problem to be Solved by the Invention) However, since the above-mentioned phase matching circuit employs a feedback loop using a low-pass filter, as shown in FIG. ,
There is a problem in that it takes time for the control voltage of the voltage controlled oscillator 16 to stabilize. Also, even if the frequencies of the reference signal and burst signal match, if the phases do not match,
- It is necessary to shift the skin debris wave number and perform phase matching, which takes time.

Therefore, the present invention provides a high-speed phase matching circuit that can achieve phase matching between a color burst signal and a reference signal at high speed, and can minimize color disturbance in an image even when special reproduction is performed. The purpose is to provide

[Structure of the Invention] (Means for Solving the Problems) The present invention extracts a burst signal from a video signal sampled and quantized at n f sc (f sc: color subcarrier frequency), and on the other hand, The nfsc reference oscillation signal is frequency-divided to the fsc frequency, and the phases of this reference signal and the burst signal are compared to obtain error information. The delay amount of the video signal is controlled and derived in accordance with the error information from the phase comparison means.

(Function) With the above means, the phase of the video signal is controlled rather than the phase of the reference signal using a feedforward method, and phase matching can be obtained at high speed.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, in which a video signal at an input terminal 21 is delayed in a delay section 22 based on phase error information and is output to an output terminal 23.

Furthermore, the video signal is supplied to a sync separation circuit 24.

The synchronization separation circuit 24 separates and delays the horizontal synchronization signal to create a burst gate pulse and supplies it to the burst gate circuit 25 . The burst signal extracted by the burst gate circuit 25 is supplied to one side of a phase comparator 26.

The other side of the phase comparator 26 is supplied with a stable reference signal (3.58 MHz) from a reference signal generator 27 using a crystal. The phase error information obtained by the phase comparator 26 is supplied to the control terminal of the delay section 22 to control the amount of delay of the video signal. The delay unit 22 prepares, for example, a plurality of video signals with different phases, and selects and derives a video signal with an appropriate phase according to the content of the phase error information.

As a result, the video signal at the output terminal 23 is brought into alignment at a predetermined phase with respect to the reference signal at high speed. Therefore, even when the reference signal obtained at the terminal 28 is used in a subsequent signal processing circuit, the phase relationship with the chroma signal is stable.

FIG. 2 is a signal waveform diagram shown to explain the operation of the above circuit. When the video signal becomes discontinuous due to special playback or the like and starts again, phase error information is detected during the burst signal period T. be exposed. Based on this information, the delay unit 22 is controlled at high speed to set the delay amount τ. Thereby, the phases of the reference signal and the burst signal are always maintained in a predetermined relationship.

FIG. 3 is an example of a signal processing circuit to which the present invention is applied.

For example, an NTSC analog video signal is input to the input section 30 and guided to an analog-to-digital converter 31 . The analog-to-digital converter 31 uses the oscillation output from the voltage controlled oscillator 39 through the phase shift circuit 41 as its driving clock pulse. The analog-to-digital converted video signal is digitized to follow the input time-base fluctuation, and is stored in the memory 32. memory 32
The write address is controlled by a write address generation circuit 33 that generates a write address in accordance with the time axis variation of the input video signal. The read address of the memory 32 is generated by a read address generation circuit 3 which generates a read address by being driven by a stable oscillation output from a crystal oscillator.
4. The read digital video signal is converted into an analog video signal in a digital-to-analog converter, which is also driven by stable clock pulses from a crystal oscillator, and is led out to an output section.

As a result, a stable video signal with time axis correction can be obtained at the output section.

By the way, in this system, analog-to-digital converter 3
1, if there is a time axis variation in the analog video signal, the phase of the clock pulse is controlled to follow it.

As a result, the sample points for digitization are relatively the same as those with no time axis variation.

For this purpose, means are provided for controlling the drive clock pulses.

That is, the human video signal is supplied to the synchronization separation circuit 35. The synchronization separation circuit 35 separates the horizontal synchronization signal HD and supplies it to the phase comparator 36.

Phase comparator 36. The closed loop of the low pass filter 37, the adder 38, the voltage controlled oscillator 391 and the frequency divider 40 forms a phase locked loop. That is, the phase comparator 36
compares the phase of the horizontal synchronizing signal HD and the output (horizontal frequency) from the frequency divider 40, and filters the phase error to the low-pass filter 37.
The signal is smoothed by the adder 38 and supplied to the frequency control terminal of the voltage controlled oscillator 39. This causes the oscillation frequency of the voltage controlled oscillator 39 to be phase-locked to the horizontal synchronization signal of the input video signal. In other words, if jitter occurs in the horizontal synchronization signal due to time axis fluctuations in the input video signal,
The oscillation output of the voltage controlled oscillator 39 follows accordingly.

Next, the oscillation output of the voltage controlled oscillator 39 is used as a clock pulse for the analog-to-digital converter 31 via a phase shift circuit 41, and time axis fluctuation correction is performed with even finer precision.

That is, the digital burst signal output from the analog-to-digital converter 31 is extracted by the burst gate circuit 43. The gate timing of the burst gate circuit 43 is controlled by the burst flag from the synchronous separation circuit 42. The burst flag may be obtained from the synchronization separation circuit 35 described above.

The extracted burst signal is input to the burst phase error detection section 45. This burst phase error detection section 45
Of the burst phase error information detected in , the low-frequency component is supplied to the adder 38 via the low-pass filter 46 and added to the control voltage of the phase-locked loop. As a result, the phase-locked loop is phase-locked to the horizontal synchronizing signal and also follows the phase of the burst signal, resulting in a finely synchronized state. Furthermore, the burst phase error detection section 45
The high frequency component of the burst phase error information detected in
It is used to control the phase shift amount of the phase shift circuit 41. The phase shift circuit 41 prepares in advance a plurality of clock pulses with different phases, and selects and derives a clock pulse with an appropriate phase according to the output from the burst phase error detection section 45.

As a result, the sampling clock pulse for analog-to-digital conversion follows the input signal with high precision, and quantizes the input video signal with relatively no time axis fluctuation.

The analog-to-digital converted digital video signal is sent to the memory 33 based on the address generated by the write address generation circuit 33 driven by the output of the phase shift circuit 41.
2. The intervals between sample points change in accordance with time axis fluctuations, so they are not necessarily at equal intervals, but by reading out at accurate intervals when reading from the memory 33, it is possible to obtain an output video signal without time axis fluctuations. Can be done.

The output of memory 32 is input to high speed phase matching circuit 60.

The high-speed phase matching circuit 60 includes a plurality of shift registers RO1,
62 and 63 are connected in series, and the output of the memory 32 and the outputs of the registers 61 and 62 and 63 are supplied to the selector 64. The selector 64 selects and derives one of the outputs of the memory 32 and the outputs of the registers 61, 62, and 63, and its selection operation is controlled by the output of the phase detector 67.

The phase detector 67 detects an error between the burst phase of the video signal read from the memory 32 and the phase of the reference signal obtained by frequency-dividing the output from the reference oscillator 51. That is,
The read data from the memory 32 has been corrected for time axis fluctuations, but the relationship between the read timing and the burst phase may not necessarily be in the best condition. Therefore, the phase error between the fsc reference signal, which is obtained by frequency-dividing the oscillation signal (4fsc) indicating the reading reference by the frequency divider 66, and the burst signal extracted by the burst gate circuit 65 is detected, and the selector 64 selects the best one. The aim is to obtain video signals that are in phase relationship. For example, the phase of the burst signal with respect to the reference signal is as shown in FIG.
If it is ■ or ■, select the burst signal of ■.

The output of the selector 64 is also a digital-to-analog converter 52 which uses the output of the basic oscillator 51 as a driving clock pulse.
is converted into an analog video signal by

[Effects of the Invention] As explained above, according to the present invention, phase matching between a color burst signal and a reference signal can be obtained at high speed,
In particular, even when special reproduction or the like is performed, color disturbances in the image can be minimized.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a signal waveform diagram shown to explain the operation of the circuit in FIG. 1,
Fig. 3 is a circuit diagram showing an example of the use of this invention, and Fig. 4 is a circuit diagram showing an example of the use of this invention.
Signal waveform diagram shown to explain the circuit operation in the figure, No. 5
This figure shows a conventional phase matching circuit, and FIG. 6 is a signal waveform diagram shown to explain the circuit operation of FIG. 5. 22...Delay unit, 24...Synchronization separation circuit, 25...
・Burst gate circuit, 26... Phase comparator, 27・
...Reference signal generator, 22...Delay section, 51...Reference oscillator, 60...Phase matching section, 61, 62.63.
...Shift register, 64...Selector, 65...
Burst gate circuit, 67...phase detector. Applicant's agent Patent attorney Takehiko Suzue Figure 4

Claims (1)

[Claims] burst extraction means for extracting a burst signal from a video signal sampled and quantized at NFSC (color subcarrier frequency); It is characterized by comprising: a phase comparison means for obtaining error information by comparing the phase with the burst signal; and a delay means for controlling and deriving the delay amount of the video signal according to the error information from the phase comparison means. High-speed phase matching circuit.