JPH0666104B2 - Time axis correction device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a time axis correction apparatus, and more particularly, to a video signal recording / reproducing apparatus such as a VTR or a video disk, which uses a memory to remove the time axis fluctuation included in the reproduced image. The present invention relates to a time axis correction device.

[Prior art]

Conventional time base corrector (below, T
(Referred to as BC) include those shown in FIGS. 1 to 3. FIG. 1 shows the main configuration of the recording / reproducing apparatus and TBC. In the figure, reference numeral 1 is a recording / reproducing apparatus used in, for example, a well-known helical scan type two-head VTR, which is 1800 rpm.
Rotating cylinder 1b driven by motor 1a
Then, using two heads 1c which are mounted 180 degrees opposite to each other, a digital video signal previously recorded on the magnetic tape 1d is reproduced. The recording signal on the magnetic tape 1d is appropriately modulated, and the reproduced signal is demodulated by the demodulation circuit 2 into the original digital video signal.

3 is a write signal generation circuit as a writing means,
A clock and a horizontal synchronizing signal (hereinafter referred to as an HD signal) which are previously included in the reproduced digital video signal are detected and output to the memory 4. As will be described later, a reproduced digital video signal including a time axis fluctuation (hereinafter referred to as a jitter) component is written in the memory 4 and is temporarily stored while timing is detected by the detected write clock W and the write HD signal fW. To be done. Reference numeral 5 is a reference clock generation circuit composed of, for example, a crystal oscillator, and 6 is a memory read clock R of a constant frequency shaped from the reference clock.
And a read HD signal f _R and a vertical synchronizing signal VD, which is a read signal generating circuit as a read means.

This VD signal is input to the phase servo circuit 7 and is used to synchronize the rotational phase of the rotary cylinder 1b by controlling the rotary motor 1a of the recording / reproducing apparatus 1.

On the other hand, the read clock R and the read HD signal f _R are stored in the memory 4
Is used to read the written video data input to the.

FIG. 2 shows the details of the structure of the memory 4. 8a, 8b, 8c
Is a shift register having a predetermined capacity, and the case of three shift registers is illustrated. The digital video signal (uncorrected digital video signal) including the jitter component and input to the memory 4 is
Writing to and reading from the shift registers 8a, 8b, and 8c are performed simultaneously at a rate of 1H per 3 horizontal scanning lines (3H), and read within the remaining 2H section. To prevent 9 both clock W for writing and reading, switching the R, clock switching circuit supplied to the shift registers 8, 10 enter both HD signal fW, f _R of the writing and reading, the clock switching circuit 9, each shift A multiplexer 11 that sequentially switches the outputs of the registers 8a, 8b, and 8c, and a timing control circuit that outputs a control gate signal.

FIG. 3 shows the operation timing of the memory 4.

At the time of writing, burst-like writing clocks W ₁ , W ₂ , W ₃ are sequentially output from the clock switching circuit 9 to the respective shift registers 8a, 8b, 8c at a predetermined timing. The timing is controlled by the write HD signal fW input via the timing control circuit 10. For example, first, of the uncorrected digital video signals (shown as analog signal waveforms corresponding to video data for convenience) of 1H minute intervals shown by 1 in FIG. 3 among V _{0 to} V ₄ , the video signal V ₀ is , Is written in the shift register 8a by the write clock W ₁ which is completely synchronized with this. Then, the video signal V ₁ and then V ₂ are written to the write clocks W ₂ and W ₃ , respectively, in sequence with the shift register 8b.
It is written in 8c.

The write data is read out after a predetermined interval period D from the end of each of the write clocks W ₁ , W ₂ , W ₃ and then through the clock switching control circuit 9 to the shift registers for stable frequency reading. This is done while sequentially inputting the clocks R ₁ , R ₂ and R ₃ . The read video signal output is sequentially switched by the multiplexer 11 controlled by the read HD signal f _R input via the timing control circuit 10,
The video data is continuous in time series. Jitter is not included in this video data. That is, in the conventional TBC, an uncorrected digital video signal having a jitter component is written to the memory at a clock synchronized with this, and the reading is performed by using a reference clock in which the jitter component can be ignored to remove the jitter component. It is becoming like this.

However, in such a TBC, the allowable limit (collection window) of the uncorrected video data jitter is the third.
It is determined by the interval period shown by D in the figure. In other words, it is the range where the write clock W and the read clock R do not overlap. Interval period D is 0 for 3H memory
Because it is limited to the range of 1H, the collection window is
It becomes 1H. In order to keep the writing / reading timing within the range of the collection window 1H, it is necessary for the phase servo circuit 7 to keep the rotational phase error of the rotary cylinder 1b within 1H. However, it is difficult for a helical VTR or the like to obtain such accuracy including a jig, so that the collection window must be expanded accordingly. For that purpose, it is necessary to make the capacity of the memory 4 larger than 3H. The memory capacity for 1H is, for example, 4x of NTSC system.
When sampled at fsc (fsc: subcarrier frequency 3.58MHz) = approx. 14MHz, it becomes 910 bytes. Using a large amount of high-speed and large-capacity memory, which is several times more than this, is extremely disadvantageous in terms of cost and power consumption.

〔Purpose〕

The present invention has been made in order to eliminate such a conventional defect, and a read control signal for reading the video signal written in the memory from the memory is written to the video signal input to the memory. It is an object of the present invention to provide a time axis correction device capable of significantly reducing the storage capacity of a memory by performing phase control so as to follow the phase of a write control signal for blocking.

〔Example〕

4 and 5 are diagrams showing an embodiment of the present invention.
In the figure, the same reference numerals as those in FIG. 1 represent the same parts. 12
Is a voltage controlled oscillator (hereinafter referred to as VCO) that generates a reference clock to be output to the read signal generating circuit 6. 1
3 when the phase comparator for comparing the phase of the write HD signal fW and read HD signal f _R, the phase difference between the input signal fW and f _R is 180 °, configured so that the phase error output is zero Has been done. Reference numeral 14 is a loop filter for feeding back the output of the phase comparator 13 to the VCO 12. PLL which is control means by the above three parties
(Phase Locked Loop). Reference numeral 15 is a 30 Hz oscillation circuit for generating a reference signal for the phase servo circuit 7 of the recording / reproducing apparatus 1.

Next, the operation will be described.

In FIG. 4, the rotary cylinder 1b of the recording / reproducing apparatus 1 is
It rotates at a constant speed and a constant phase in synchronization with the reference signal generated by the 30 Hz oscillator circuit 15. The uncorrected digital video data reproduced by the recording / reproducing apparatus 1 is written in the memory 4 in the same procedure as the conventional one. The reading of written data differs from the conventional one in the following points.

A write HD signal fW and read HD signal f _R is supplied to a phase comparator 13 of the PLL, the phase is compared. The output phase error signal is fed back to the VCO 12 via the loop filter 14. In this case the phase comparator 13, a phase difference between the write HD signal fW and read HD signal f _R is a phase lock so as to be 180 °. As a result, the TBC can always operate near the center of the collection window, and writing and reading do not overlap. Since the read clock R also follows the jitter of the write HD signal fW, the jitter remains in the TBC output. However, the nature of the jitter contained in the uncorrected video data is usually as shown in FIG.
The distribution has mainly low frequency components. Therefore, TB
In order to keep the jitter component remaining in the C output within the collection window, the read clock R should follow only the very low frequency component of the residual jitter component.

Therefore, the response frequency of PLL is several Hz as shown in Fig. 5 (b).
It should be below. As a result, the residual jitter remaining in the TBC output is also only a very low frequency component, as shown in FIG. 5 (c). Such a low-frequency jitter can be sufficiently removed by the AFC circuit provided in the monitor TV, so that it does not cause a visual problem and can be used for home VTRs. That is, if the response frequency of the PLL is adjusted as described above, it is possible to substantially eliminate the jitter and the collection window of 1H is sufficient. Therefore, the storage capacity of the memory 4 can be greatly reduced.

Although the above-described embodiment takes the helical scan VTR as an example, the present invention is not limited to this. For example, it can be applied to various recording methods such as a video disk and a video sheet recorder. Although the recording signal is a digital video signal, it can be similarly applied to a method of writing and reading an analog signal to and from an analog line memory.

〔effect〕

As described above, according to the present invention, the read control signal for reading the video signal written in the memory from the memory is the phase of the write control signal for writing the video signal input to the memory. By performing the phase control so as to follow, it is possible to reduce the TBC correction window, and it is possible to greatly reduce the storage capacity of the high-speed writable / readable memory.

[Brief description of drawings]

FIG. 1 is a block diagram of a main part of a conventional time axis correction device of a video signal recording / reproducing device, FIG. 2 is a block diagram of a memory part shown in FIG. 1, and FIG. 3 is a block diagram of FIG. Timing charts for explaining the operation, FIGS. 4 to 5 show an embodiment according to the present invention, FIG. 4 is a main part configuration diagram corresponding to FIG. 1, and FIG. 5 (a) is an uncorrected video. FIG. 5B is a response characteristic diagram of the PLL, and FIG. 5C is a residual jitter spectrum diagram of the corrected video signal. 1 ... Recording / reproducing apparatus 3 ... Write signal generating circuit as writing means 4 ... Memory 6 ... Read signal generating means as reading means PLL ... Control means

Claims (2)

[Claims] 1. A memory for inputting a video signal including a synchronization signal, temporarily storing the input video signal, and outputting the stored video signal, and a memory included in the video signal input to the memory. A sync signal separating means for separating and outputting a sync signal existing therein, a write control signal generating means for generating a write control signal for writing a video signal inputted to the memory, and a sync signal separating means for outputting. A first phase for comparing the phase of a synchronization signal with the write control signal generated by the write control signal generating means and controlling the phase of the write control signal generated by the write control signal generating means in accordance with the phase difference. Control means, read control signal generation means for generating a read control signal for reading the video signal written in the memory from the memory, and the write control signal generation means. Comparing the phase of the write control signal generated by the means with the read control signal generated by the read control signal generating means, and the phase of the read control signal generated by the read control signal generating means in accordance with the phase difference. A time axis correction device having a second phase control means for controlling the. 2. The second phase control means has a low phase difference of about several Hz between the write control signal generated by the write control signal generating means and the read control signal generated by the read control signal generating means. The time axis correction device according to claim (1), which has a response characteristic such that the phase of the read control signal generated by the read control signal generating means can be controlled when the frequency is a frequency. .