JPS5833379A - Static picture recorder - Google Patents

Abstract

PURPOSE:To prevent the quality deterioration of a reproduced picture, by eliminating the level fluctuation component caused by the uneven revolution of a floppy disk device or the fluctuation component due to the header signal in the video signal which is written in a field memory in the slow writing mode. CONSTITUTION:The component differing between the reproduced video signal containing the level fluctuation due to the frequency variance caused by the uneven revolution of a floppy disk devide 20 and the uneven revolving signal of the device 20 which is obtained by feeding the clock signal recorded on a disket along with the FM signal into an FM demodulating circuit 21 is extracted through a luminance compensating circuit 102. Then the recording of the FM signal onto the disket is delayed by a recording delaying circuit 101 for a period during which the effect of the spurious fluctuation component emerging to the uneven revolution by the header signal in the recording mode is eliminated. Thus the writing is inhibited for the demodulated video signal into a field memory 5 until the spurious fluctuation component of the uneven revolution is eliminated in the reproduction mode. As a result, the change of luminance can be completely eliminated for a reproduced image.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a still image recording device that records video signals as still image information on a diskette of a floppy disk device. The present invention relates to a still image recording device.

Generally, the original purpose of a floppy disk device is to record and reproduce digital data, and digital data and clock signals are written simultaneously.

By the way, one field of video information is stored in a field memory, and the low frequency converted video signal obtained by slowly reading out the video information stored in the field memory is FM-modulated. When trying to record and play back still images using a floppy disk device, the following problems occur.

In other words, the rotation system of a floppy disk drive does not have any servo or other controls to keep the rotation of the diskette constant, so it always has uneven rotation. When an FM signal is recorded and reproduced, the frequency of the FM signal changes due to the time axis fluctuation due to the rotational unevenness described above.

The frequency fluctuations caused by the rotational unevenness described above are converted into voltage fluctuations when FM demodulated, resulting in level fluctuations in the video signal obtained by FM demodulation, and the brightness on the television screen changes according to the rotational unevenness described above. The image quality will deteriorate.

The present invention has been made in view of the above-mentioned circumstances when still images are recorded and played back using a conventional floppy disk device, and the present invention is directed to playback that includes level fluctuations due to uneven rotation of the rotation system of the floppy disk device. video signal,
A brightness correction circuit is provided that extracts the difference component between the clock signal and the rotational unevenness signal of the floppy disk device obtained by inputting the clock signal to the FM demodulation circuit. A recording delay circuit is provided that delays recording of the FM signal until the influence of the pseudo fluctuation component appearing in the rotational unevenness signal is eliminated by a header signal inserted into the signal indicating the starting position of the FM signal, and FM demodulation during playback is performed. By sufficiently delaying the timing of writing signals to the field memory from the header signal, uneven rotation of the rotation system of the floppy disk device and brightness changes caused by the header signal are eliminated, thereby preventing deterioration in the quality of the reproduced image. The purpose of the present invention is to provide a still image recording device.

Hereinafter, the present invention will be specifically described with reference to the accompanying drawings.

FIG. 1 shows a block diagram of a still image recording device using a floppy disk device.

The still image recording device has two operation modes, one for recording and one for reproduction.

That is, during recording, there is a fast write mode in which the video signal of one field is written to the field memory in real time, and a fast write mode in which the contents of the written field memory are written in one field memory.
There is a slow read mode in which the signal is read out at a speed of /33, converted into an analog signal, then FM modulated and recorded on three tracks of a diskette of a floppy disk device along with the clock used for reading one field memory.

On the other hand, during playback, the FM signal played by the floppy disk device is demodulated, and the playback clock
There is a slow write mode in which the data is sampled again and written to the field memory, and a fast read mode in which the contents of the field memory are read out at the scan rate of the television scan line and converted to an analog signal to obtain a reproduced video signal.

The configuration of the still image recording apparatus shown in FIG. 1 will be explained below according to the above four operation modes.

[Fast write mode operation part]

The video signal input to the taste image signal input terminal 11 is as follows.

1/2 of the sampling frequency when converting to a digital signal
In order to remove higher frequency components, the signal is input to a pre-filter 1, which is a low-pass filter (I, , P, F,), and then input to a pedestal clamp circuit 2 for processing, and for recording and playback. Contact R of switch S1 of selection circuit 8 to select
1 through the movable contact C1, the quantization number 6 bits A/
Input to D converter 4.

It is converted into a 6-bit digital signal.

On the other hand, the video signal is also input to the synchronization separation circuit 7, and based on the horizontal synchronization signal separated by the synchronization separation circuit 7, a fast-ride clock generation circuit 8 generates a fast write clock that serves as a reference for the write operation. ing.

The clock for writing the output of the A/D converter 4 into the field memory 5 is the fast write clock described above or the slow write clock described later.The write clock selection circuit 9, in the fast write mode, Select Fastlight Clock.

The fast write clock is input to the A/D converter 4 as a sampling pulse for sampling the video signal, and is also input to the write address control circuit 10 as a write clock pulse.

The write address control circuit 10 creates a write address for writing the digital signal sampled by the A/D converter 4 and quantized into 6 bits into the field memory 5 constituted by a semiconductor memory.

The field memory 5 has a configuration as shown in FIG.

In the field memory 5 shown in FIG. 2, an input digital signal is converted into parallel data by a 10-bit serial-to-parallel conversion circuit 35, temporarily stored by an input latch 36, and 60 data are output at a period of 1/10 of the sampling frequency. The data is written to a semiconductor memory section 37 consisting of a memory.

The field memory 5 is configured as described above.

The reason is that when writing the 6-bit digital signal from the A/D converter 4 to the semiconductor memory section 37, the sampling frequency is approximately 12 MHz (period, approximately 82μ), as will be described later.
This is because a signal sampled at a frequency of 12 MHz cannot be directly written into the semiconductor memory section 37 due to the cycle time of the semiconductor memory section 37.

On the other hand, when reading a signal, the field memory 5 temporarily stores the signal from the semiconductor memory section 37 in the output latch 38, and converts the signal from the semiconductor memory section 37 into serial data using the parallel-to-serial conversion circuit 39. ing.

The RAM controller 40 creates control signals such as an address signal, a write signal, an input/katch signal, an output latch signal, a serial-to-parallel conversion clock, and a parallel-to-serial conversion clock from the write address signal and the read address signal. It is a circuit.

Next, the fast write clock generation circuit 8 generates a well-known PLL (PhaseLocke) as shown in FIG.
d Loop) consists of a voltage controlled oscillator 43 which generates a signal with a frequency of fs according to an input voltage, and a 1 which divides the frequency fs of the signal output from the voltage controlled oscillator 43 into l/N. /N frequency dividing circuit 44.

The reference signal input to the phase comparator 41 is a horizontal synchronizing signal, and the division ratio N of the frequency dividing circuit 44 determines how much of the capacity of the field memory 5 and one horizontal opening period is sampled. In this example, N-7
72 is adopted.

Therefore, the fast write clock frequency (output signal frequency of the voltage controlled oscillator 43) fs by the fast write clock generation circuit 8 is fs = 772X15.734.
= 12.147 MHz, and this 12.147 MH
The video signal is sampled and written into the field memory 5 using the z clock.

Note that in this embodiment, the video signal is a black and white signal, and the sampling frequency is 12.147 MHz as described above, but in the case of a color signal, if the force is the frequency fsc of the rasp carrier, the sampling frequency is 12.147 MHz. X f
sc= 10.7 MHz or 4 X'f SC
= 14.8 MHz sampling frequency is used.

Further, in this embodiment, when writing a video signal for one field period to the field memory 5, the semiconductor single body memory section 37
In order to minimize the capacity of , and to store as much information as possible within that capacity, only the period during which video information exists is stored.

For this reason, the horizontal blanking period is not sampled for the horizontal component of the video signal, and the vertical synchronization period is not sampled for the vertical component. Write gates for clocks (85% of one horizontal open period) and for 249H are created in the vertical write processing circuit 26, and these write gates are input to the write clock selection circuit 9, and the write gates are inputted to the write clock selection circuit 9. The video signal is sampled and written into the field memory 5 only during the output period.

[Slow read mode operation part]

When the fast write mode ends and writing of the digitized video signal to the field memory 5 is completed,
A slow mode signal is input to the slow clock generating circuit 15 of FIG. 1 from the slow mode signal input terminal 2.

The slow clock generation circuit 15 is a circuit that creates a slow read clock, and when the K slow mode signal is input as described above, the slow clock generation circuit 15
outputs a slow read clock to the recording delay circuit 101.

The recording delay circuit 101 prohibits reading from the field memory 5 for a certain period of time, and transmits the FM to the deskerato.
This circuit delays the recording of a signal, and its structure and operation will be described in detail later.

The recording delay circuit 101 reads the slow read clock after the above-mentioned fixed period and outputs it to the clock selection circuit 12.
Output to.

The read clock selection circuit 12 is a circuit that selects between a slow read clock and a fast read clock output from a fast read clock generation circuit 13 (to be described later). In the slow read mode, the read clock selection circuit 12 selects between a slow read clock is selected and output as a read clock pulse and a D/A pulse to the read address control circuit 11 and the 6-bit D/A converter 6, respectively.

The read address control circuit 11 creates a read address for reading the field memory 5 based on a slow read clock input as a read clock pulse.

Further, the D/A converter 6 receives the slow read clock input as a D/A pulse and a digital signal from the field memory 5, and converts it into an analog signal at the cycle of the D/A pulse.

The output of the D/A converter 6 is input to a low-pass interpolation filter 18 for smoothing.

The interpolation filter 18 outputs a video signal that is time-base converted from the video signal input to the video signal input terminal 11 .

2. The frequency fck of the slow read clock is determined by the number of diskette tracks used per field and the maximum frequency of the time-axis converted video signal. In this embodiment, The frequency fck of the slow read clock is 1/33 of the sampling frequency during fast write, and fCk=12.147H/FB=868KHz.

On the other hand, the highest frequency f+Bax of the video signal input from the video signal input terminal ■1 is f max = 4.67
Assuming MHz, the highest frequency fsmax of the time-axis converted (low frequency) video signal is fs max =
4.57/83=141.5KHz.

The time-base converted video signal output from the interpolation filter 18 is input to the FM modulation circuit 19 .

The FM modulation circuit 19 is a circuit that modulates the time-base converted video signal into an FM signal of 180 KHz to 220 KHz, and its output is input to the recording amplifier 30 in the floppy disk device 20. .

The recording amplifier 30 records the FM signal of the time-base converted video signal on a track on one side of the diskette.

As described above, the FM signal of the time-axis converted video signal is recorded on one side of the diskette of the floppy disk device 20, but in order to reproduce this FM signal and store it again in the field memory 5, it is necessary to A clock is required to obtain the programming pulse and the write address, and this clock, like the FM signal, must be a signal that is subject to fluctuations due to rotational irregularities occurring in the rotation system of the floppy disk device main body 32.

Therefore, in order to correct fluctuations in the FM reproduction signal due to rotational irregularities occurring in the rotation system of the floppy disk device main body 320, it is necessary to write a clock on the other side of the diskette.

Therefore, in this embodiment, the read clock output from the slow clock generation circuit 15 is input to the header signal addition circuit 22, and the header signal addition circuit 22 detects the beginning of the FM signal recorded on one side of the diskette. A header signal for detecting the reference position is added to the slow read clock, and its output is input to the recording amplifier 31, which adds the header signal and outputs the slow read clock signal. I am trying to record it on a diskette at the same time as the FM signal.

Note that when recording an FM signal on a diskette, the horizontal write processing circuit 25 generates 650 clock pulses of read clock pulses, while the vertical write processing circuit 26 generates 650 clock pulses.
Create a read gate for 88H, first read 83H from field memory 5, and
Record on the second track.

When the recording of the first track is completed, the mode control circuit 2.8 detects the index signal from the floppy disk device main body 32 and outputs a head access signal.
The track control circuit 29 moves the head and records 88H of information on the second track.

Similarly to the above, information for 83H is recorded on the third track, and recording for 1 field, that is, 249H, is completed in three tracks.

[Slow light mode operation part]

The reproduction amplifier 33 of the floppy disk device 20 reproduces the FM signal written on the diskette, outputs the output to the FM demodulation circuit 21, inputs the output of the FM demodulation circuit 21 to the integration circuit 47, Restores to a video signal that has undergone time axis conversion (low frequency conversion).

On the other hand, the reproduction amplifier 34 of the floppy disk device 20 reproduces the clock signal written on the surface opposite to the recording surface of the FM signal at the same time as the FM signal, thereby generating a write clock signal.

The write clock signal is input to the header signal detection circuit 23, gate 24, and brightness correction circuit 102.

The brightness correction circuit 102 detects the frequency (period) fluctuation of the read clock obtained by reproducing the slow read clock having a constant period except for the period of the header signal, and detects the rotation of the floppy disk device main body 32. A circuit that detects a rotational unevenness signal of the rotational system, and performs brightness correction by canceling a level fluctuation component of a video signal inputted from the integration circuit 47, which includes a level fluctuation component due to the rotational unevenness of the rotational system, with the rotational unevenness signal. , its structure is explained in detail in Japanese Patent Application No. 55-99143 filed by the present applicant.

The output of the brightness correction circuit 102 is transmitted from the contact P1 of the switch S1 of the selection circuit 3 through the movable contact C1 to the A/D
It is input to converter 4.

On the other hand, the header signal added to the write crotter signal output from the reproduction amplifier 34 of the floppy disk device 20 is detected by the header signal detection circuit 23.

The timing immediately after the detection of the header signal is the reference for the start of the FM signal, and the gate circuit 24 takes out the write clock signal of the header signal and uses it as a slow write clock.

The header signal detection circuit 23 is described in detail in the specification of the application filed by the present applicant on August 21, 1980 (title of the invention "Still Image Recording Apparatus").

The slow write clock is input to the write clock selection circuit 9 together with the fast write clock.

In the slow write mode, the write clock selection circuit 9 selects a slow write clock and inputs the slow write clock as a sampling pulse to the A/D converter 4, and also as a write clock pulse to the write address control circuit 10. Output to.

The A/D converter 4 uses the slow write clock as a sampling pulse to sample the low frequency conversion video signal output from the FM demodulation circuit 21 and convert it into a digital signal, and generates a write address output from the write address control circuit 10. The data is written to the address of the field memory 5 specified by.

As already mentioned, the video signal of one field is
The data is recorded on three tracks of the diskette, and the horizontal write processing circuit 25 operates similarly to the slow read mode.
creates a gate for 650 write clock pulses, and the vertical write processing circuit 26 creates a write gate for 88H, respectively, and writes 88H worth of video information obtained from the first track of the diskette to the field memory 5. When this writing operation is completed, the head of the diskette moves and the video information recorded on the second and third tracks of the diskette is transferred to the field memory 5.
I try to write to .

[Fast read mode operation part]

When the slow write mode ends and writing of the low frequency converted video signal to the field memory 5 is completed, the mode control circuit 28 outputs a fast read mode signal.

The synchronization signal generation circuit 14 includes a 4×fsc crystal oscillator 14.
', and is output to the horizontal synchronous signal 20x generation circuit 13, which serves as a reference for the reproduced signal.

The fast read clock generation circuit 13 is constituted by a PLL circuit shown in FIG.
A fast read clock, which serves as a reference for the read operation, is created using the above-mentioned horizontal synchronization signal inputted from the controller as a reference signal.

The frequency of the fast read clock mentioned above is the same as the frequency of the fast write clock, fS=t2, 147 M
It is Hz.

The fast read clock is input from the read clock selection circuit 12 to the read address control circuit 11 as a read clock pulse, and is also input to the D/A converter 6 as a D/A pulse.

The read address control circuit 11 creates a read address signal for reading out the information stored in the field memory 5 from the read clock pulse.

The D/A converter 6 converts the digital signal read out from the field memory 5 according to the read address signal into an analog signal using a D/A pulse, and the output of the D/A converter 6 is as follows. The signal is input to an interpolation filter 16 and restored to a video signal with the same scan rate as the television.

On the other hand, the horizontal write processing circuit 25 creates read gates for 650 clock pulses, and the vertical write processing circuit 26 creates read gates for 249H. No signal is read out during the non-open period, ie, the horizontal blanking period and the vertical synchronization period.

A video signal without a horizontal blanking signal and a vertical synchronizing signal outputted from the interpolation filter 16 is inputted to a mixing circuit 17 together with a composite synchronizing signal and a composite blanking signal outputted from the synchronizing signal generating circuit 14, and the mixing circuit 16 performs the above-mentioned processing. A composite video signal is created by adding a composite synchronization signal and a composite blanking signal to the video signal, and the composite video signal is passed from the playback side contact P2 of the switch S2 of the selection circuit 3 to the common contact C2. I am trying to output it.

In the fast read mode described above, by continuously and repeatedly reading out the field memory 5, a continuous composite video signal is output from the common contact C2 of the switch S2 of the selection circuit 3, and the composite video signal is input it into the television receiver.

A still image is obtained.

The mode control circuit 28 shown in FIG. 1 controls the operating portions of the four modes described above in response to input signals from the operation keys 27, and supplies necessary signals for each mode.

Next, the operation of the still single-image recording apparatus shown in FIG. 1 will be explained, focusing on the operations of the recording delay circuit 101 and the brightness correction circuit 102.

During slow write mode operation, as shown in FIG. 4, the FM signal from the floppy disk device main body 32 is processed by the reproduction amplifier 33 and input to the FM demodulation circuit 21.

The FM demodulation circuit 21 is a pulse count type demodulator, and operates a monostable circuit at the rising and falling edges of the rectangular wave of the FM signal to generate a pulse train signal. When this pulse train signal passes through the integrating circuit 47, the repetition period changes from time to time.

A video signal that changes depending on the period of the pulse train signal is obtained.

Meanwhile, along with the FM signal, the floppy disk device main body 3
The light clock reproduced in step 2 is processed by the regenerative amplifier 34 and then input to the brightness correction circuit 102.

As shown in FIG. 4, the brightness correction circuit 102
An FM demodulation circuit 45 composed of a pulse count circuit similar to the demodulation circuit 21, an integration circuit 46 that integrates the output of the FM demodulation circuit 45, and an amplifier 48 that amplifies the rotational unevenness signal output from the integration circuit 46. , a differential amplifier 49 that amplifies the difference between the video signal output from the integrating circuit 47 and the output of the amplifier 48.

When the write clock input to the FM demodulation circuit 45 undergoes frequency fluctuations due to rotational irregularities in the rotation system of the floppy disk device main body 32, the integrator circuit 46 outputs a frequency proportional to the cycle and amount of fluctuation of the rotational irregularities. A rotational unevenness signal having an amplitude as shown in FIG. 5 is output.

The rotational unevenness signal is amplified by an amplifier 48 and then input to a differential amplifier 49.

The differential amplifier 49 amplifies the difference between the output of the amplifier 48 and the video signal containing a level fluctuation component due to uneven rotation of the rotation system of the floppy disk device main body 32, which is manually input from the integrating circuit 47. If the amplifier 48 is set so that the output of the amplifier 48 is equal to the level fluctuation component, the level fluctuation component in the video signal will be canceled out by the output of the amplifier 48. From the differential amplifier 49, a video signal free of level fluctuation components due to uneven rotation of the rotation system of the floppy disk device main body 32 is obtained.

As described above, it is possible to remove the level fluctuation component of the video signal due to rotational unevenness of the rotation system of the floppy disk device main body 32, and to correct the brightness change of the video.

In order to detect rotational irregularity signals of the rotation system of the floppy disk device main body 32, the read clock signal must have a constant frequency, as can be seen from the above explanation. , as shown in FIG. 5, the header signal addition circuit 22 adds F to the clock pulse during the output period of the clock prohibition signal to the read clock signal.
'A header signal is added to identify the starting position of the M signal.

The above header signal period is the clock pulse period (2,7μ
s), it is set to 10 μs.

When the write clock signal obtained by reproducing the read clock signal including the header signal as described above is input to the FM demodulation circuit 45, the integration circuit 46 detects the rotational unevenness of the rotation system of the floppy disk device main body 32 and the header signal. Due to the periodic fluctuation caused by the signal, a rotational unevenness signal that changes as shown in FIG. 5 is output.

In the above-mentioned rotational unevenness signal, the period τ indicates the original rotational unevenness signal of the rotation system of the floppy disk device main body 32, and the period τ8 has a large DC output due to a large change in the repetition period of the pulse train due to the header signal. It also shows that the period τ has changed. indicates that the DC output is changing due to the influence of the large fluctuation that occurred during the period τ8, and the above period τ. The larger the time constant of the integrating circuit 46, the longer the fluctuation in .

A video signal obtained by inputting the rotational unevenness signal as described above to the differential amplifier 49 and performing brightness correction is stored in the field memory 5 by a slow light cropper that is created at the same time as the header signal is detected. and the period τ. The video signal outputted from the differential amplifier 49 includes a pseudo fluctuation component due to the influence of the header signal, and the fluctuation level is also large, so the brightness may appear at the joint of the image reproduced on the television screen. Change occurs.

In order to eliminate the above-mentioned brightness changes, recording of the FM signal on the diskette is delayed until the influence of the above-mentioned pseudo-fluctuation component appearing in the uneven rotation signal due to the influence of the header signal is eliminated. Of the video signal obtained by demodulating the FM signal reproduced by the main body 32, a period in which the amplitude fluctuates due to the above-mentioned pseudo fluctuation component may be prevented from being written to the field memory 5.

Therefore, in the embodiment shown in FIG. 1, a recording delay circuit 101 as shown in FIG. 6 is inserted between the slow clock generation circuit 15 and the read clock selection circuit 12.

The recording delay circuit 101 generates a 9FM prohibition gate signal that prohibits reading from the field memory 5 by the N count circuit 50 that counts the slow clock from the slow clock generation circuit 15, and outputs the 9FM prohibition gate signal. During the signal period, the gate 51 is closed to prohibit passage of the slow clock input from the slow clock generation circuit 15 to the read clock selection circuit 12, thereby delaying generation of the slow read clock.

During the above FM prohibition gate signal period, the slow clock is set to N.
Due to the influence of the header signal, the period until the influence of the pseudo fluctuation component appearing in the rotational unevenness signal of the floppy disk drive main body 320 rotation system disappears (period τ in Fig. 5) is longer. It is set so that

In the above manner, as shown in FIG. 7, the slow read clock is set at the timing t of the end of the FM inhibit gate signal. starting from the timing t. Reading of the field memory 5 is started from the above timing [. The period before τ.

A signal with a constant frequency is recorded, and the above timing [.

In the subsequent period, the FM signal of the D/A converted video signal read from the field memory 5 is recorded.

If the FM-modulated video signal is recorded on the diskette with a sufficient delay from the header signal, when the field memory 5 is in the slow write mode, there will be no pseudo fluctuation component due to the header signal in the video signal output from the brightness correction circuit 102. After that, the video signal is written to the field memory 5, so that the field memory 5 has the following information:
A normal video signal that does not contain the above-mentioned pseudo fluctuation components will be written.

Therefore, in the first read mode, no change in brightness occurs at the joint of the image obtained by reading the contents of the field memory 5.

In the above manner, it is possible to completely eliminate rotational irregularities in the rotation system of the floppy disk device main body 32 and brightness changes that occur in reproduced images due to header signals.

In the above explanation, basic embodiments of the present invention have been described, but the present invention is not limited to the above embodiments, and various configurations can be made within the scope of the gist of the present invention.

As is clear from the detailed explanation above, the present invention provides a method for converting the level fluctuation component caused by rotational unevenness of the rotation system of a floppy disk device included in a reproduced video signal into the rotation obtained by FM demodulating a clock pulse. This is because the system's rotational unevenness signal is used to cancel this out, and the timing at which the FM demodulated signal is written into the field memory during playback is sufficiently delayed from the output timing of the header signal to prevent pseudo fluctuation components caused by the header signal from being written into the field memory. , level fluctuation components due to uneven rotation of the floppy disk device body and pseudo fluctuation components due to header signals are removed from the video signal written to the field memory during slow write mode, and brightness changes in the reproduced image due to these level fluctuation components in the video signal are removed. can be completely eliminated, and low F of the image quality of the reproduced image can be prevented.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a still image recording device according to the present invention, FIG. 2 is a block diagram showing the configuration of a field memory, and FIG.
FIG. 4 is a block diagram of the PLL circuit, FIG. 4 is a block diagram of the brightness correction circuit, and FIG. 5 is a time chart 1 for explaining the generation of rotational unevenness signals. FIG. 6 is a block diagram of the recording delay circuit, and FIG. 7 is a time chart for explaining the operation of the recording delay circuit. 4... A/D converter, 5... Field memory, 6... D/A converter, 8... Fast write clock generation circuit, 9... Write clock selection circuit, 1
0...Write address control circuit, 11...Read address control circuit, 12...Read clock selection circuit,
13...Fast read clock generation circuit, 15...
・Slow clock generation circuit, 19...FM modulation circuit,
20... Floppy disk device, 21... FM demodulation circuit. 22... Header signal addition circuit, 23... Header signal addition circuit, 101... Recording delay circuit, 102... Brightness correction circuit. Patent applicant: Sanyo Electric Co., Ltd. Agent: Patent attorney Seihaku Ho and two others

Claims (1)

[Claims] (1) A device for recording one field of video signal stored in a field memory in the form of an FM signal on multiple tracks of a diskette of a floppy disk device, which
having a pulse width larger than that of a clock signal recorded in synchronization with the FM signal on a surface opposite to the recording surface of the M signal;
A header signal adding circuit adds a header signal representing the start position of the FM signal to the clock signal, and detects the header signal based on the difference in pulse width between the header signal and the clock signal to detect the start position of the FM signal. The header signal detection circuit is equipped with a header signal detection circuit that performs FM demodulation of the reproduced video signal containing level fluctuations due to frequency fluctuations caused by rotational irregularities in the rotation system of the floppy and disk device, and the clock signal recorded on the diskette together with the FM signal. A brightness correction circuit extracts the difference component from the rotational unevenness signal of the floppy disk device obtained by inputting it into the circuit, and a brightness correction circuit that extracts the difference component from the rotational unevenness signal of the floppy disk device obtained by inputting it to the circuit, and the field is used only for a period of time until the influence of the pseudo fluctuation component that appears in the rotational unevenness signal due to the error signal during recording disappears. A recording delay circuit for inhibiting reading from the memory and delaying recording of the FM signal onto the diskette is provided, and the demodulated video signal is written into the field memory until the above-mentioned pseudo fluctuation component 75 of the rotation unevenness signal disappears during playback. A still image recording device characterized by not performing.