JPH0822088B2 - Time axis correction device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time axis correction apparatus for writing an input video signal in a memory, removing a time axis error from the memory, and reading the video signal. It is applied to video tape editing equipment.

[Outline of Invention]

The present invention relates to a time axis correction apparatus which writes an input video signal in a memory, reads out the video signal by removing the time axis error from the memory, and a burst signal and a horizontal synchronization signal from the input video signal written in the memory. To detect the discontinuous portion of the sub-carrier signal, detect the inverted portion of the color framing, and control the write start signal to the memory by this detection output and the video signal read from the memory. By subjecting the chroma signal to the phase inversion process, it is possible to normally perform the highly accurate time axis correction process even for a video signal including a portion in which the color frame is inverted by the editing process.

[Conventional technology]

Generally, in a signal recording / reproducing apparatus such as a VTR that records / reproduces a signal using a rotary head device, time axis fluctuations due to eccentricity of the rotary head, uneven rotation, fluctuations in running speed of a recording medium, etc. are involved. It is necessary to correct the fluctuation of the time axis contained in the reproduction signal in order to perform a high reproduction operation. Especially, in a so-called direct FM recording type video tape recorder that directly modulates and records the video signal,
Since residual jitter causes color irregularity, it is necessary to perform highly accurate time axis correction processing.

Conventionally, to correct the time base error of the VTR playback video signal, the input video signal containing the time base error is digitized and written to the memory by the write clock signal, and the time base error is removed from this memory. For example, a time axis correction device configured as shown in FIG. 2 for reading out is used.

In the conventional time axis correction device shown in FIG. 2, the reproduced video signal including the time axis fluctuation is supplied to the analog / digital (A / D) converter 41 through the signal input terminal 40 and synchronized. It is supplied to the separation circuit 51 and the burst gate circuit 52.

The sync separation circuit 51 separates the sync signal contained in the reproduced video signal and supplies the horizontal sync signal to the AFC circuit 53. Further, the burst gate circuit 52 is
The burst signal included in the input reproduction video signal is separated and supplied to the APC circuit 54.

In the case of the NTSC system time axis correction device, the AFC circuit circuit 53 has a frequency (910 times) that is 910 times the horizontal synchronization frequency (fh) based on the horizontal synchronization signal supplied from the synchronization separation circuit 51.
fh) or sub-carrier frequency (frequency four times f _SC (4
f _SC ), and supplies the reproduced clock pulse to the APC circuit 54.
By dividing the frequency by 910, a write start signal (Ws) for each horizontal scanning period (1H) is formed and supplied to the write address generation circuit 55. Also, the APC circuit 54 performs phase control to match the phase of the reproduction clock pulse with the phase of the burst signal supplied from the burst gate circuit 52, and changes the phase according to the time axis error of the input reproduction video signal. Form a write clock signal (W _CK ) having a frequency of 910 fh, and supply this write clock signal (W _CK ) to the write address generation circuit 55 and the A / D converter 41.

Further, the reference clock generation circuit 61 has a frequency of 910fh.
The reference read clock signal (R _CK ) of the read address generation circuit 62 and digital-analog (D / A) converter 43
To be supplied.

Then, by using the write clock signal (W _CK ) accompanied by the phase fluctuation according to the time axis error of the input reproduction video signal formed by the APC circuit 54, the input reproduction video signal is converted by the A / D converter 41. The digitized video data is written to the memory 42, and the video data is read from the memory 42 by using the reference read clock signal (R _CK ) having no time axis error given by the reference clock generation circuit 61 and D / A By converting to analog with the converter 43,
Playback video signal with time axis error corrected signal output terminal 44
Output from

[Problems to be solved by the invention]

By the way, in the NTSC system, a video signal is configured with four fields as one color frame, and color reproduction can be performed from the chroma signal with reference to the phase of the color burst signal superimposed on the video signal. There is. When the time axis correction processing is performed on the playback video signal of the video tape that has been edited, ignoring the above color frame, with the conventional time axis correction device, ± 140 ns (1/2 f _SC ) causes the image to shift, and normal time axis correction processing cannot be performed. In particular, in a direct FM recording type video tape recorder, residual jitter causes color unevenness and the like, so it is necessary to perform highly accurate time axis correction processing.

Therefore, in view of the above conventional problems, the present invention is
An object of the present invention is to provide a time-axis correction device having a novel configuration that can normally perform high-precision time-axis correction processing even for a playback video signal of a video tape that has been edited with the color frame ignored. And

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention writes an input video signal in a memory, and writes it in the memory in a time axis correction device which reads out a video signal from which a time axis error has been removed. Extracting means for extracting a burst signal and a horizontal synchronizing signal from the input video signal, and a write start signal forming means for forming a write start signal to the memory from the burst signal and the horizontal synchronizing signal extracted by the extracting means, Detecting means for detecting a discontinuous portion of the subcarrier signal from the burst signal and SCH of the horizontal synchronizing signal, control means for controlling the phase of the write start signal based on the detection result of the detecting means, and the burst signal And a write address of the input video signal to the memory based on the write start signal. Write address signal generating means for generating a signal, read address signal generating means for generating a read address signal for reading the video signal stored in the memory based on a reference clock, and read from the memory Separation means for separating the video signal thus generated into a luminance signal and a chroma signal, and inversion processing means for selectively inverting the phase of the chroma signal separated by the separation means based on the detection result of the detection means, A synthesizing unit for synthesizing the chroma signal output from the inversion processing unit and the luminance signal output from the separating unit is provided.

[Action]

In the time axis correction device according to the present invention, the burst signal and the horizontal synchronizing signal are extracted from the input video signal by the extracting means, and the discontinuous portion of the subcarrier signal is detected by the detecting means from the burst signal and the SCH of the horizontal synchronizing signal. By detecting and controlling the phase of the write start signal to the memory formed by the write start signal forming means based on the burst signal and the horizontal synchronizing signal by the control means based on the detection result of the detecting means, Correct image shifts in unframed areas. The video signal is read from the memory by the read address signal generated based on the reference clock, the video signal is separated into the luminance signal and the chroma signal by the separating means, and the phase of the chroma signal is detected by the detecting means. A video signal without chroma inversion is formed by selectively inverting based on the result and synthesizing with the luminance signal by the synthesizing means.

〔Example〕

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

The time-axis correction device shown in the block diagram of FIG. 1 performs time-axis correction processing of an NTSC system reproduced video signal including a time-axis variation reproduced by a direct recording system video tape recorder (not shown). The input reproduction video signal supplied to the signal input terminal 10 is digitized by the analog / digital (A / D) converter 11, and this video data is stored in the memory 13 according to the write address data formed by the write address generation circuit 12. , The video data is read from the memory 13 in accordance with the read address data formed by the read address generation circuit 14, and the video data is analogized by the digital / analog (D / A) converter 15 to output the signal. The playback video signal that has undergone time-axis correction processing is output from 16.

In this time axis correction device, the input reproduction video signal is supplied from the signal input terminal 10 to the A / D converter 11, and is also supplied to the sync separation circuit 17 and the burst gate circuit 18, The horizontal separation signal (PBH) and the vertical synchronization signal (PBV) are taken out by the sync separation circuit 17,
Further, the burst signal is taken out by the burst gate circuit 18.

Horizontal sync signal (PB
H) is AFC circuit 19, N / I detection circuit 20 and SCH detection circuit 21
Is also supplied to the write start signal generating circuit 23 via the phase shifter 22. Also,
Vertical sync signal (PBV) obtained by the sync separation circuit 17
Are supplied to the inversion detection circuit 24.

The burst signal obtained by the burst gate circuit 13 is supplied to the APC circuit 20. Further, the burst signal is sent to the SCH through the exclusive OR circuit 26.
It is supplied to the detection circuit 21 and is also supplied to the write start signal generation circuit 23 via the exclusive OR circuit 27.

The AFC circuit 19 has a horizontal sync signal (fh) based on the horizontal sync signal (PBH) supplied from the sync separation circuit 12.
Supplied to the APC circuit 25 for 910 times the frequency (910fH) that is to form the reproduction clock pulses having a frequency of four times the sub-carrier frequency _{(f SC) (4f SC)} . And
The APC circuit 19 uses the phase of the burst signal supplied from the burst gate circuit 13 as a reference, and the AFC circuit 1
A write clock signal (W _CK ) with a phase variation according to the time base error of the above-mentioned reproduced video signal is formed based on the reproduction clock supplied from 4, and this write clock signal (W _CK ) is _subjected to the A / D conversion And the write address generating circuit 12.

Further, the N / I detection circuit 20 is supplied with a frame pulse corresponding to a color frame, and based on this frame pulse and the horizontal synchronization signal (PBH) supplied from the synchronization separation circuit 12, the frame pulse is As a signal showing the inverted state of the phase of the burst signal of each line in the color framing state with respect to the color frame shown in FIG. Form an N / I signal. The N / I signal obtained by the N / I detection circuit 20 is supplied to the exclusive OR circuit 26, and also the memory 13 and the exclusive OR circuit via the exclusive OR circuit 28. Is being supplied to 26.

The exclusive-OR circuit 26 inverts the phase of the burst signal of the opposite phase line by taking the exclusive-OR of the N / I signal and the burst signal. That is, the exclusive OR circuit 26 aligns the burst signal of the color framing portion of the input reproduction video signal in the positive phase, and the burst signal of the non-color framing portion in the opposite phase. , Above SCH detection circuit 2
Supply to 1. Then, the SCH detection circuit 21 performs a phase comparison between the burst signal supplied via the exclusive OR circuit 26 and the horizontal synchronization signal (PBH) supplied from the synchronization separation circuit 17 to obtain the opposite phase. The burst signal is detected and its detection output is supplied to the inversion detection circuit 24.

The inversion detection circuit 24 determines from the detection output of the SCH detection circuit 21 and the vertical synchronization signal (PBV) that the burst signal has an opposite phase, that is, a field in which the color framing of the input reproduction video signal is not logically "1". The inversion detection output shown is supplied to the exclusive OR circuit 28.
The exclusive OR circuit 28 inverts the polarity of the N / I signal formed by the N / I detection circuit 20 by the detection output of the inversion detection circuit 24, and puts it in the color framing state of the input reproduction video signal. Form the corresponding N / I signal. The N / I signal obtained by the exclusive OR circuit 28 is the memory 13
It is supplied to the decoder 29 via.

Further, the exclusive OR circuit 27, to which the N / I signal obtained by the exclusive OR circuit 28 is supplied, applies the burst signal supplied from the burst gate circuit 18 only to the fields where color framing is not taken. The phase is inverted by the N / I signal. Then, the write start signal generation circuit 23 supplies the horizontal synchronization signal (PBH) supplied from the synchronization separation circuit 17 via the phase shifter 22 from the burst gate circuit 18 via the exclusive OR circuit 27. A write start signal is formed by synchronizing with the supplied burst signal, and the write start signal is supplied to the write address generation circuit 12. The write start signal generated by the write start signal generation circuit 23 is N / N only in the field where the burst signal supplied from the burst gate circuit 18 through the exclusive OR circuit 27 is not color framing. The phase is inverted by the I signal so that it is shifted by 140 ns, and the image shift is corrected by this.

The write address generation circuit 12 forms write address data from the write start signal (W _S ) and the write clock signal (W _CK ) supplied from the APC circuit 25, and the A / D converter 11 outputs the write address data. The video data obtained by digitizing the input reproduction video signal is written in the memory 13 according to the write address data.

Further, the read address generating circuit 14, the reference of the read clock signal from the reference clock generating circuit 30 is supplied with (R _CK) and the read start signal (R _S), the read clock signal (R _CK) and a read start signal Read address data is formed based on (R _S ), and the video data is sequentially read from the memory 13. The video data read from the memory 13 is supplied to the Y / C separation circuit 31 and also to the digital / analog (D / A) converter 15 via the signal switching circuit 32. ing.

The Y / C separation circuit 31 separates the video data read from the memory 13 into luminance signal data and chroma signal data, and drops the luminance signal data into a dropout compensation circuit.
33 and the chroma signal data to the decoder 29. The dropout compensation circuit 33 performs dropout compensation on the luminance signal data, and supplies the luminance signal data that has undergone dropout compensation to the data synthesis circuit 34. Further, the decoder 29 outputs the N / I signal corresponding to the color framing state of the input reproduction video signal to the memory 1
It is supplied via 3 and performs a decoding process for inverting the phase of the chroma signal in accordance with this N / I signal. The chroma signal data decoded by the decoder 29 is supplied to the encoder 36 via the dropout compensation circuit 35. This encoder 36 is the above reference clock generation circuit.
Color framing is performed by performing an encoding process that inverts the phase of the chroma signal in accordance with the reference decoded signal supplied from 30. The chroma signal data encoded by the encoder 36 is supplied to the data synthesizing circuit 34.

Then, the data synthesizing circuit 34 synthesizes the video data subjected to the chroma inversion processing from the luminance signal data and the chroma signal data, and supplies it to the D / A converter 15 via the signal switching circuit 32.

In the time axis correction device having such a configuration, when the reproduced video signal from the video tape which has been subjected to the editing process ignoring the color framing is supplied to the signal input terminal 10, the data synthesizing circuit 34 synthesizes it. Chroma inversion processed video data is selected by the signal switching circuit 32 and analogized by the D / A converter 15, so that image shift and chroma inversion do not occur in a portion where color framing is not taken. A reproduced video signal that has been correctly time-axis corrected is obtained at the signal output terminal 16.

〔The invention's effect〕

In the time axis correction device according to the present invention, the burst signal and the horizontal synchronizing signal are extracted from the input video signal by the extracting means, and the discontinuous portion of the subcarrier signal is detected by the detecting means from the burst signal and the SCH of the horizontal synchronizing signal. By detecting and controlling the phase of the write start signal to the memory formed by the write start signal forming means based on the burst signal and the horizontal synchronizing signal by the control means based on the detection result of the detecting means, It is possible to correct the shift of the image in the unframed part. Further, the video signal is read from the memory by the read address signal generated based on the reference clock, the video signal is separated into the luminance signal and the chroma signal by the separating means, and the phase of the chroma signal is detected by the detecting means. A video signal without chroma inversion can be formed by selectively inverting based on the result and synthesizing with the luminance signal by the synthesizing means.

That is, in the time axis correction device according to the present invention, the detecting means detects the discontinuous portion of the subcarrier signal from the burst signal extracted from the input video signal by the extracting means and the SCH of the horizontal synchronizing signal, and based on the detection result. Control the phase of the write start signal to the memory and selectively invert the phase of the chroma signal of the video signal read from the memory, so that the video signal formed by the editing work ignoring the color frame Even if input, it is possible to prevent image shift and form a video signal without chroma inversion, and highly accurate time-axis correction for the playback video signal of a video tape that has been edited with color frames ignored. Processing can be performed normally.

[Brief description of drawings]

FIG. 1 is a block diagram of a time axis correction device showing the configuration of an embodiment of the present invention. FIG. 2 is a block diagram of a time axis correction device showing a configuration of a conventional example. 10 …… Signal input terminal 11 …… A / D converter 12 …… Write address generation circuit 13 …… Memory 14 …… Read address generation circuit 15 …… D / A converter 16 …… Signal output terminal 17 …… Synchronization Separation circuit 18 …… Burst gate circuit 19 …… AFC circuit 20 …… N / I detection circuit 21 …… SCH detection circuit 23 …… Write start signal generation circuit 24 …… Inversion detection circuit 25 …… APC circuit 26,27, 28 …… Exclusive OR circuit 29 …… Decoder 30 …… Reference clock generation circuit 31 …… Y / C separation circuit 34 …… Data synthesis circuit 36 …… Decoder

Claims (1)

[Claims] 1. A time axis correction apparatus for writing an input video signal to a memory and reading a video signal from which a time axis error has been removed, wherein a horizontal synchronization with a burst signal is made from the input video signal written to the memory. Extracting means for extracting a signal; write start signal forming means for forming a write start signal to the memory from the burst signal and the horizontal synchronizing signal extracted by the extracting means; and the SCH of the burst signal and the horizontal synchronizing signal. Detecting means for detecting a discontinuous portion of the subcarrier signal from the above, control means for controlling the phase of the write start signal based on the detection result of the detecting means, and the input based on the burst signal and the write start signal. A write address that generates a write address signal for writing the video signal to the memory. Response signal generating means, a read address signal generating means for generating a read address signal for reading the video signal stored in the memory based on a reference clock, and a brightness of the video signal read from the memory. A separation means for separating the signal and the chroma signal; an inversion processing means for selectively inverting the phase of the chroma signal separated by the separation means based on the detection result of the detection means; and an output from the inversion processing means. A time axis correction device comprising a synthesizing means for synthesizing the chroma signal and the luminance signal output from the separating means.