JPH0636613B2 - Color synchronization circuit - Google Patents

Description

The present invention relates to a color synchronizing circuit, and more particularly to a video signal recording / reproducing apparatus using a PAL television signal, for example, a time axis correcting apparatus for a video tape recorder (VTR). It is suitable for application.

[Conventional technology]

90 ° to each other in PAL television signals
Two color difference signals having the phase difference of U signal and V signal
The signal has a signal, and the carrier phase of the V signal is 180 ° phase-inverted with respect to the U signal for each horizontal synchronization section. In addition to this, the carrier phase of the U and V signals has a frequency such that the phase is rotated by 90 ° at the time of the horizontal sync signal, and the phase of the color burst is inverted to conform to this. Has been done.

However, the VTR has an operation mode such as a dynamic tracking reproduction mode in which recording tracks are reproduced intermittently as needed. In this operation mode, U and V included in the reproduction input signal picked up from the magnetic tape are used. There is a possibility that the order around the phase of the signal, the phase inversion order of the V signal, and the phase inversion order of the burst signal become discontinuous. When such a signal discontinuity occurs,
Correct color information cannot be transmitted to the video signal processing circuit in the subsequent stage.

In order to solve such a problem, the time axis correction device 1 having the configuration shown in FIG. 6 has been conventionally used. In FIG. 6, the reproduced video input signal VD _IN picked up from the magnetic tape is input to the analog-digital conversion circuit 4 of the time axis correction circuit 3 through the delay circuit 2. Sampling clock signal SAM for analog-to-digital conversion circuit 4
(Having a frequency of 4 _SC with respect to the subcarrier frequency _SC ) is generated in the sampling clock generation circuit 5.

Here, the sampling clock generation circuit 5 generates a sampling pulse SAM synchronized with the burst signal included in the reproduced video input signal VD _IN .

The delay circuit 2 has a delay time corresponding to the time required to generate the sampling pulse SAM in the sampling clock generation circuit 5, and thus the sampling clock generation circuit 5 converts the sampling pulse SAM into analog-digital based on the burst signal. A burst signal is supplied to the analog-digital conversion circuit 4 via the delay circuit 2 at a timing after the analog signal is supplied to the conversion circuit 4 and the analog-digital conversion circuit 4 starts operating.
Thus, the burst signal can be taken into the time-axis correction circuit 3 together with the video signal.

In the analog-to-digital conversion circuit 4, the reproduced video input signal VD _IN converted into a digital signal is taken into the memory 6 by a write clock pulse (not shown) synchronized with the sampling pulse SAM. The data in the memory 6 is read at a predetermined reference cycle by a read clock (not shown), converted into an analog video signal S1 in the digital-analog conversion circuit 7, and then supplied to the YC separation circuit 8.

Thus, the video signal S1 input to the YC separation circuit 8 is time-axis corrected to the predetermined reference period, and the luminance signal Y separated in the YC separation circuit 8 is directly output to the addition circuit 9. Then, the separated color signal C is supplied to the color synchronizing circuit 10 to be color-synchronized and then supplied to the adding circuit 9.

The color synchronizing circuit 10 receives the color signal C in the UV separation circuit 15, and inputs the separated V signal and U signal to the decoding circuits 16 and 17, respectively. Additionally give connexion decode wire carrier rear generator 19 sampling the burst signal B _U burst sampling circuit 18 included in the U signal.

The decode carrier generation circuit 19 generates V-axis and U-axis carrier signals SV1 and SU1 and inputs them to the decode circuits 16 and 17, respectively, and thus, in the decode circuits 16 and 17, the baseband (before conversion to the PAL format format). V signals V0 and U signals U0 (which are the same as the original signals similar to the color signals) are generated and supplied to the encoding circuits 20 and 21, respectively.

The baseband V signal V0 is applied to the V detection circuit 22, and the direction of the V signal of the line (scanning line in the horizontal direction) is detected. As a result, the detection signal S2 indicating the V direction of the line currently being processed is supplied to the match / mismatch detection circuit 23 and compared with the reference V-axis signal REFV. When the direction of the V signal of the line currently being processed does not match the direction of the reference V-axis signal REFV, the match / mismatch detection circuit 23 obtains a detection signal S3 of logic "1" and switches it to the switching circuit 24. It is given as a control signal.

On the other hand, the switching circuit 24 supplies the + V-axis and -V-axis carrier signals SV supplied from the V-axis encode carrier generating circuit 25.
P and SVM are provided. The V-axis encode carrier generation circuit 25 receives the reference subcarrier R via the phase shift circuit 26.
EFSC is supplied, which allows the reference subcarrier RE
It changes in synchronism with the phase shift of FSC, and is in the opposite phase of +
V-axis and -V-axis encode carrier signals SVP and SV
Generate M.

Thus, when the match / mismatch detection circuit 23 detects that the direction of the V signal of the line currently being processed matches the direction of the reference V-axis signal REFV, it outputs the encoded carrier signal SVP or SVM of the matched direction. It is selected by the switching circuit 24 and supplied to the encoding circuit 20 as a V-axis encode carrier signal VEN0. On the other hand, the V direction of the line currently being processed is the reference V
When the direction does not match the direction of the axis signal REFV, an encoding carrier having a direction opposite to the direction of V represented by the detection signal S2 is selected by the switching circuit 24 as SVP or SVM to be used as the V-axis encoding carrier signal VEN0 for the encoding circuit 20. Supply. Thus the encoding circuit 2
0 is always supplied with the V-axis encode carrier signal VEN0 having the same direction as that of the reference V-axis signal REFV.

On the other hand, the reference subcarrier signal REFSC obtained through the phase shift circuit 26 is applied to the encoder circuit 21 by U
It is provided as the axis encode carrier signal UEN0.

In this way, the V signal and the U signal V1 synchronized with the reference signal are output to the output terminals of the encoding circuits 20 and 21, respectively.
And U1 are obtained, which are combined in the adder circuit 27 and supplied to the adder circuit 9 as a color signal C0 which is color-synchronized with the reference signal. As a result, at the output end of the adder circuit 9,
In the color synchronizing circuit 10, a composite video output signal VD _{OUT including} a color signal that is color-synchronized with the reference signal is obtained.

Here, as the reference signal, for example, a station reference signal of a broadcasting station is used. According to the conventional time axis correction device 1 of FIG. 6, the reproduced video input signal V is supplied to the memory 6 of the time axis correction circuit 3.
In order to obtain the baseband V signal V0 and U signal U0 by taking in the D _IN burst signal and the video signal, and generating the decode carrier signals SV1 and SU1 in the color synchronization circuit 10 based on the burst signal. The baseband V signal V0 and U signal U0
Is encoded by using the V-axis and U-axis encoding carrier signals VEN0 and UEN0 synchronized with the reference subcarrier REFSC, thereby including a V signal that changes in synchronization with the change in synchronization of the V signal of the reference synchronization signal. The video output signal VD _OUT can be obtained.

[Problems to be solved by the invention]

When configured as the conventional time axis correction apparatus 1 of FIG. 6,
Since the burst signal is taken into the time axis correction circuit 3 together with the video data, there is a problem in that the reproduced video input signal VD _IN must be input to the time axis correction circuit 3 via the delay circuit 2.

That is, since the frequency band of the reproduced video input signal VD _IN is extremely wide, it is necessary to prepare a high-performance delay circuit 2 for allowing the wideband video signal to pass without deteriorating the characteristics. However, such a wideband and high performance delay circuit inevitably increases in size and shape, and even if such a large delay circuit is used, the phase of the color signal actually changes due to the temperature characteristics of the delay time and the like. This is unavoidable, and there is a problem that a loop for correcting this change is separately required.

AP Further, in the color synchronization circuit 10, in order to obtain a decoded wire carrier rear SV1 and SU1 burst signal _{B U} is
A C circuit is required, but as the APC circuit, a circuit that instantly follows a discontinuous carrier must be used.
Therefore, conventionally, a gate oscillator has been used. However, this gate oscillator has a drawback that it is apt to malfunction due to noise caused by jumping in from other circuit elements.

The present invention has been made in consideration of the above points, and eliminates the above-mentioned problem by eliminating the need to capture a burst signal when capturing the reproduced video input signal VD _IN into the time base correction circuit 3. The idea is to solve all the points at once.

[Means for solving problems]

In order to solve such a problem, in the present invention, the color matching control circuit 35 compares the color information PBC0 of the reproduction video input signal VD _{IN and} the color information REFC0 of the reference signal to obtain the color matching control signal CCTL corresponding to the difference. Occurs,
By controlling the phase of the subcarrier REFSC of the reference signal on the basis of the color matching control signal CCTL in the decoding carrier generation circuit 40, the V-axis and U-axis decoding carriers that match the color information PBC0 of the reproduced video input signal VD _IN can be obtained. V-axis and U-axis encoding carrier signals VEN and UEN that generate signals VCR and UCR and that match the color information REFC0 of the reference signal based on the sub-carrier REFSC of the reference signal are generated in the encoding carrier generation circuit 49, and the V-axis is generated. And U-axis encoding Carriers VCR and UCR are used to decode the V and U signals separated from the reproduced video input signal VD _IN to obtain a baseband color signal, and the baseband color signal is used for the V-axis and U-axis. Encoding carrier VEN and U
By encoding with EN, a color signal C0 synchronized with the color information REFC0 of the reference signal is obtained.

[Action]

The color matching control circuit 35 detects how the reproduced color information PBC0 of the reproduced video input signal VD _IN differs from the color information REFC0 of the reference signal and detects the corresponding color matching control signal C.
Get the CTL. The decode carrier generation circuit 40 receiving the color matching control signal CCTL is a reference sub carrier REF.
By switching control of the phase of SC by the color matching control signal CCTL, V-axis and U-axis decoding carriers VCR and UCR that match the reproduction color information PBC0 are generated from the reference sub-carrier REFSC, and reproduction is performed by this decoding carrier. The V and U signals separated from the video input signal VD _IN are decoded into baseband color signals.

Thus, the baseband color signals V0 and U0 have carriers corresponding to the reference subcarrier REFSC and include the V signal of the reproduced video input signal VD _IN and the video signal of the U signal.

On the other hand, V generated by the encode carrier generating circuit 49
Axis and U-axis encoding carriers VEN and UEN are used to encode the baseband color signals V0 and U0, and thus the baseband color signals V0 and U0 have color information that matches the reference color information that the reference signal has. Converted into color signals V1 and U1. Thus, the color signal C0 color-synchronized with the reference signal can be obtained.

〔Example〕

An embodiment of the present invention will be described in detail below with reference to the drawings. In FIG. 1 in which parts corresponding to those in FIG.
The reproduced video input signal VD _IN is directly input to the analog-digital conversion circuit 4 of the time axis correction circuit 3, and the sampling clock generation circuit 5 reproduces the video input signal VD _IN.
The reproduced video input data sampled by the sampling pulse SAM made from the burst contained in _IN is written in the memory 6.

Here, only the video signal (that is, the luminance signal Y and the color signal C) of the reproduced video input signal VD _IN is written in the memory 6. On the other hand, the color information of the reproduced video input signal VD _IN is input through the reproduced color information input circuit 31, and the burst signal is not written in the memory 6.

The reproduction color information input circuit 31 receives the reproduction video input signal VD _IN and generates the V signal V11 as the first color information of the reproduction color information PBC0. Here, the V signal V11 is a signal indicating whether or not to invert the baseband V signal for each line. As shown in FIG. 2, when it is not inverted, a logic "1" (represents a + V state), Logic "0" when inverted
(Represents the state of -V). Here, FIG. 2 shows P
The format of the AL type television signal is shown, and the phase of the V signal at the time point t ₀ of the first horizontal synchronizing signal of the first field is used as a reference (this is the + V direction), and thereafter one horizontal synchronizing section (that is, 1H). It means that the phase of the V signal V11 is alternately inverted (that is, in the order of −V, + V, 0V ... Thus, the V signal V11 is represented by a 1-bit digital signal.

The reproduction color information input circuit 31 uses the NI signal NI indicating the direction of the color bust as the second color information of the reproduction color information PBC0.
11 is sent out. Here, the NI signal NI11 is, as shown in FIG. 2, a logical "1" (this state is represented by symbol I) indicating the direction of the color burst at the time t ₀ when the first horizontal synchronizing signal of the first field is generated. , The logic "0" (this is referred to as the sign N
Represents).

In FIG. 2, the format of the PAL television signal is expressed under the following conditions. That is, with respect to the V signal of the first horizontal synchronizing signal of the first field as a reference, the phase of the V signal at the time point of the succeeding horizontal synchronizing signals is sequentially represented as a vector. Although the vector of the V signal is inverted every 1H, the vector of the V signal is shown in FIG. 2 in a non-inverted representation format, which is represented as the V axis as shown in FIG. Expressed in this way, the U signal is a signal whose phase is delayed by 90 ° with respect to the + V signal, and as shown in FIG.
It is represented by a vector that is advanced by 90 ° from the V-axis vector as the U-axis signal. When expressed in this manner, the burst signal B _U noninverting time, as shown in FIG. 3, so that can be represented by 45 ° advanced vector to the vector of the V axis.

Drawing the format of a PAL television signal under these conditions, the first field is as follows:
As shown in FIGS. 2 (A1) to (A4), there is a relationship in which the vector on the V-axis is rotated by 90 ° and delayed while passing 1H each with respect to the phase at time t ₀ as a reference. Correspondingly, the phase of the −U axis (and hence the U axis) is also rotated by 90 °. This burst signal B _U respect can be expressed as a phase every time the 2H elapses from the time t ₀ is successively reversed. The vector representing this burst signal B _U is at time t ₀
The NI signal (Fig. 2 (A
3)).

Here, the frequency of the subcarrier is practically selected to be a value that is not divisible by the frequency of the horizontal synchronizing signal, and has an offset of 180 ° with respect to the horizontal synchronizing signal during one field section. On the other hand, since the NI signal inverts every 2H, the definition between the logical level of the NI signal NI11 and the direction of the burst signal BU is reversed between the odd field and the even field. That is, for the odd field, when the burst signal _BU is at the angle of FIG. 3 in the first 1H section, the NI signal NI
11 is defined as "N", while for even fields it is defined as a logical "N" for a phase rotated 180 °.

On the other hand, in FIG. 2 (A1), the phase around the non-inverted V-axis is shown, but the phase of the V signal is actually inverted every 1H. Therefore, it is determined whether or not the V signal is inverted with respect to the direction of the vector at the time point t ₀ by the V signal V11 (see FIG.
4)).

In this way, it is possible to specify the color information at the time when the first synchronization signal is generated for each field that successively follows, but the phase of the V axis and the -U axis at the start time t ₀ of the first field, to reach a field that matches the burst signal B _U phase, the third view (B1)
~ (B4), (C1) ~ (C4) ... (H1) ~ (H
As shown in 4), it is impossible to return to the same phase relationship without going through the phase rotation of 8 fields. This means that at the start of the first to eighth fields, the color synchronization of the standard television format format cannot be achieved unless specific color information is designated.

Further, as is apparent from FIG. 2, in the successive horizontal synchronization sections, the method of inverting the phase of the V signal and the inversion of the burst signal are as follows: 1st and 6th fields, 3rd and 8th fields, 5th and 5th fields. Comparing the 2 field, the 7th field and the 4th field, they are almost the same except that the timing is shifted by H / 2. Therefore, if the color signals of the pair of fields are processed as the same data and then the difference between odd and even is discriminated and the output timing is distinguished, the color signals of each field can be output without error. This difference in field can be distinguished by a so-called field OE signal attached to the video signal for each field.

Therefore, the reproduction color information input circuit 31 determines the phase of the V axis, the phase of the burst signal, and the odd / even of the field, for each field, based on the reproduction video input signal VD _IN. Determine which one of the 1st to 8th fields and set this to 3
Bit signal, that is, V signal V11, NI signal NI1
1, output as a field OE signal OE11.

Thus, in the memory 6, 1 of the reproduced video input signal VD _IN
A video signal for a field is written by adding 2-bit reproduction color information PBC0 consisting of a V signal V11 and an NI signal I11 for each field.

The video data read from the memory 6 is digital-
After being converted into an analog signal in the analog conversion circuit 7, when being sent to the YC separation circuit 8, the V signal and the NI signal attached to the video signal for one field are read out and the color matching control circuit 35 is read. V signal V12 and NI
It is supplied as signal NI12.

The color matching control circuit 35 sets the content of the reproduction color signal PBC0 extracted from the reproduction video input signal VD _IN to the reference color information R.
When the reproduced color information PBC0 does not match the reference color signal REFC0 as compared with EFC0, a control signal CCTL for matching the reproduced color information PBC0 is output, and the first and second color information comparison circuits 36 and 37 are provided. And an inversion control circuit 38.

As shown in FIG. 4, the first color information comparison circuit 36 compares the V signal V12 coming from the memory 6 with the reference V signal REFV in the exclusive OR circuit EX1, and when they match, it becomes a logic "0". , And a color control signal CCTL1 having a logic "1" is generated when they do not match.

Further, the color information comparison circuit 36 receives the NI data coming from the memory 6.
The signal NI12 is fed to the second exclusive OR circuit EX2.
The reference output NI13 is compared with the reference NI signal REFNI and the comparison output NI13 is supplied to the D input terminal of the flip-flop circuit FF1. The reference V signal REFV is inverted by the inverter IN and supplied to the clock input terminal of the flip-flop circuit FF1.
The exclusive OR circuit EX2 by the fall of FV
Is read into the flip-flop circuit FF1.

Here, as described above with reference to FIG. 2, one cycle of the reproduced NI signal NI12 corresponds to two cycles of the V signal V12,
Therefore, at the time when the V signal V12 shifts from + V to -V, the level of the NI signal NI12 is at a stable state of logic "1" or "0". Thus the NI signals NI12 and RE
The determination result of the exclusive OR circuit EX2 can be read into the flip-flop circuit FF1 while the FNI comparison is stable. Thus, the Q output of the flip-flop circuit FF1 is used as the comparison result output NI14 of the color information comparison circuit 36, and the third exclusive OR circuit E is output.
It is supplied to the inversion control circuit 38 constituted by X3.

On the other hand, the field odd / even signal OE11 coming from the reproduction color information input circuit 31 is the fourth exclusive OR circuit EX.
The second color information comparison circuit 37 composed of 4 compares it with the reference OE signal REFOE and outputs its comparison output OE12.
Is a comparison output N in the exclusive OR circuit EX3.
Compared with I4. Thus, if the reproduced color information PBC0 and the reference color signal REFC0 match for both the NI signal and the OE signal from the exclusive OR circuit EX3, the logic "0" is set, and if one of them does not match, the logic "1" is set. Then, the second color control signal CCTL2 is obtained.

The color control signals CCTL1 and CCTL2 represent the difference between the reference color information REFC0 and the reproduction color information PBC0 as the field number difference, and the V-axis decoding carrier phase switching circuit 4 of the decoding carrier generating circuit 40 respectively.
It is supplied to the 1- and U-axis decoding carrier phase switching circuits 42 as a switching control signal.

V-axis and U-axis decoding carrier phase switching circuits 41 and 4
Reference numeral 2 generates a V-axis decoding carrier VCR and a U-axis decoding carrier UCR having a phase corresponding to the reproduction color information PBC0 based on the reference sub-carrier signal REFSC. The phase carrier signal generated in the carrier generating circuit 43 is received. The phase shift carrier generating circuit 43 is composed of a shift register, and generates a phase carrier signal having a phase of 0 °, 90 °, 180 °, 270 ° from the reference subcarrier signal REFSC via the phase shifting circuit 44, and this is used as the V axis. And U-axis decoding carrier phase switching circuits 41 and 42 are applied to the switching input terminals.

V-axis and U-axis decoding carrier phase switching circuits 41 and 4
2 operates in conjunction with each other to select phase carrier signals having a phase difference of 90 ° and send them to the decoding circuits 16 and 17 as a V-axis decoding carrier VCR and a U-axis decoding carrier UCR, respectively.

Here, by the color control signals CCTL1 and CCTL2,
V-axis and U-axis decoding carrier phase shift switching circuits 41 and 4
2 is a color control signal CCTL1, CC as shown in FIG.
V axis and U axis decoding carrier V depending on the contents of TL2
The amount of phase rotation of CR and UCR is selected.

Thus, in the decoding circuits 16 and 17, the V signal and the U signal separated in the UV separation circuit 15 are once decoded to the base band by the V axis and U axis decoding carriers VCR and UCR, respectively, and then in the encoding circuits 20 and 21. Encoded.

The V-axis and U-axis decoding carriers VEN and UEN obtained based on the reference sub-carrier signal REFSC are supplied to the encoding circuits 20 and 21. That is, after the reference sub-carrier signal REFSC is phase-shifted by the phase-shift circuit 50 of the encode carrier generation circuit 49, it is directly converted into U
Encoding circuit 21 as axis encoding carrier UEN
Is supplied to. The output of the phase shift circuit 50 is phase-shifted by 90 ° in the + 90 ° phase shift circuit 51 and then supplied to the encoder circuit 20 as a V-axis encode carrier VEN.

Thus, at the output terminals of the encoding circuits 20 and 21, the V signal V1 and the U signal U1 synchronized with the reference subcarrier signal REFSC are encoded, which are combined in the adding circuit 27 and then combined with the luminance signal Y in the adding circuit 9. Thus, the video output signal VD _OUT color-synchronized with the reference color signal is obtained.

According to the configuration of FIG. 1, the output terminals of the decoding circuits 16 and 17 are provided with the reference color information RE in the color matching control circuit 35.
The difference in field number is detected based on the reproduction color information PBC0 with respect to FC0, and the decode carrier generation circuit 40 detects the reference subcarrier signal REFS based on the detection result.
Since the C is phase-rotated by an amount corresponding to the difference between the field numbers, the V-axis and U-axis decoding carriers VCR and UCR are obtained.
The baseband color signals V0 and U0 which are color-synchronized with the reference subcarrier signal REFSC can be decoded at the output terminal of the.

Then, the base band color signals V0 and U0 are encoded in the encoding circuits 20 and 21 based on the reference sub-carrier signal REFSC.
By encoding with the V-axis and U-axis decoding carriers VEN and UEN obtained in FIG. 9, a continuous video output signal corresponding to the line-sequential inversion operation of the V-axis of the reference sub-carrier signal REFSC. VD
_OUT can be easily obtained.

Therefore, in a VTR, for example, by reproducing the same field continuously by DT reproduction, or by reproducing by skipping the field, reproduction having discontinuous color information that is not in color synchronization with the reference color information. Video input signal VD _IN
When it arrives, it can be converted into a color signal that is in color synchronization with the reference color information, and thus the video output signal VD _OUT having the standard format of the PAL system can be easily obtained correctly.

〔The invention's effect〕

As described above, according to the present invention, the reproduced video input signal VD
Even if a playback signal that does not have standard format color information arrives as _IN , it is easy to realize a color synchronization circuit that can reliably convert this to a video output signal that is color synchronized with the reference signal. You can

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a color synchronizing circuit according to the present invention, FIG. 2 is a signal waveform diagram showing the format of a PAL television signal, and FIG. 3 is a vector diagram showing its color information. FIG. 4 is a connection diagram showing a detailed configuration of the color matching control circuit 35 of FIG. 1, FIG. 5 is a table showing its control mode, and FIG. 6 is a block diagram showing a conventional color synchronizing circuit. 1 ... Time axis correction device, 3 ... Time axis correction circuit, 10 ...
... Color synchronization circuit, 31 ... Reproduction color information input circuit, 35 ...
Color matching control circuit, 40 ... Decoding carrier generation circuit,
41, 42 ... V-axis, U-axis carrier phase switching circuit, 43
...... Phase shift carrier generation circuit, 44, 50 …… Phase shift circuit,
49 ... Encoding carrier generation circuit.

Claims (1)

[Claims] 1. A video signal recording / reproducing apparatus for recording / reproducing a PAL television signal, compares color information of a reproduced video input signal and color information of a reference signal, and generates a color matching control signal corresponding to the difference. And a V-axis and U-axis matching the color information of the reproduced video input signal by controlling the switching of the phase of the sub-carrier of the reference signal based on the color-matching control circuit of the color-matching control circuit. A decode carrier generating circuit for generating an axis decode carrier signal; and an encode carrier generating circuit for generating a V-axis and U-axis encode carrier signal matching the color information of the reference signal based on the sub-carrier of the reference signal. The color matching control circuit compares the first determination signal indicating whether to invert the baseband V signal of the reproduction video input signal. First comparing means for comparing with a corresponding first reference judgment signal, and second comparing means for comparing the second judgment signal representing the direction of the color burst of the reproduced video input signal with the corresponding second reference judgment signal. Comparing means and third comparing means for comparing a third judgment signal representing the odd-even of the field of the reproduced video input signal with a corresponding third reference judgment signal.
Generating the color matching control signal representing the difference between the color information of the reproduced video signal and the color information of the reference signal based on the comparison outputs of the first, second and third comparing means, and decoding the color matching control signal. The carrier generation circuit includes a phase shift subcarrier generating means for generating a plurality of phase shift subcarrier signals by shifting the reference subcarrier signal by a predetermined phase shift amount, and the color matching control signal generated in the color matching control circuit. Phase-shifting subcarrier selecting means for generating the V-axis and U-axis encoding carrier signals having color information matching the color information of the reference signal by selecting one of the plurality of phase-shifting subcarrier signals based on By decoding the V-axis and U-axis signals separated from the playback video input signal by the V-axis and U-axis decoding carrier A baseband color signal is obtained, and the baseband color signal is encoded by the V-axis and U-axis encoding carriers to obtain a color signal synchronized with the color information of the reference signal. Color synchronization circuit.