KR100236134B1 - Timebase corrector with drop-out compensation - Google Patents

Abstract

The input video signal is written to the time base error correction memory based on the clock pulse synchronized with the synchronization signal of the input video signal, and the signal written to the time axis error correction memory based on the read clock pulse synchronized with the existing synchronization signal. There is provided a time base correction device for reading and correcting the time base error. In such a time base correcting device, when the drop out of the first vertical synchronizing signal in the input video signal occurs, in the time base correcting device, when the drop out of the first vertical synchronizing signal in the input video signal occurs, input from the time base error correction memory. Writing of the video signal is prohibited, and the time axis error is corrected by the input video signal already written in the memory until the second vertical synchronization signal is detected.

Description

Time base compensation device

1 is a block diagram showing an embodiment of a conventional time base corrector.

2 is a waveform diagram illustrating a waveform of a vertical synchronization pulse.

3 is a block diagram showing a first embodiment of a time base corrector according to the present invention;

4 (a) to 4 (h) are timing charts referred to for explaining the operation of the first embodiment of the time base corrector according to the present invention.

5 is a block diagram showing a specific embodiment of the read clock generation circuit used in the present invention.

FIG. 6 (shown in two views of FIGS. 6 (a) and 6 (b) to enlarge the scale) is a video tape to which the second embodiment of the present invention and the time base corrector according to the present invention can be applied. Block diagram showing a recorder.

7 (a) to 7 (g) are timing charts for reference in explaining the operation of the video tape recorder shown in FIG.

* Explanation of symbols for main parts of the drawings

2: A / D conversion circuit 5: D / A conversion circuit

6: read clock generation circuit 12: horizontal sync pulse detection circuit

16: counter 17: ROM for WE generation

BACKGROUND OF THE INVENTION 1. Field of the Invention [0002] The present invention generally relates to a time base error compensator (ie, a time base compensator), and more particularly to a time base compensator suitable for use in a home video tape recorder (VTR) or the like and having a speed error correction function.

Most home video tape recorders currently on the market use a color signal low-conversion system, where the color signal is low-converted and the low-converted signal is reconverted to the original band signal by the heterodyne system in playback mode. . Since the time-base variation component of the chromaticity signal is removed by the double heterodyne method using a crystal oscillator, and the time-base variation component of the luminance signal is corrected by the automatic frequency control (AFC) circuit in the horizontal scanning circuit of the television receiver, the time-base compensator is generally used. It is not necessary. On the other hand, in a direct color processing business video tape recorder (that is, a 1-inch helical scan type video tape recorder, a 4-head video tape recorder, etc.), the luminance signal and the chromaticity signal should not be separated and an interleaved relationship should be maintained between them. Therefore, the time base corrector is frequently used.

An example of a conventional time base corrector will be described with reference to the block diagram of FIG.

Referring to FIG. 1, a video signal to be subjected to time axis correction is applied to the input terminal 1 and supplied to the analog-digital (A / D) conversion circuit 2 and the write clock generation circuit 3. The write clock generation circuit 3 generates a write clock coinciding with the variation of the time axis included in the video signal. The luminance signal component with the variation of the time axis is sampled by the write clock, and the analog video signal is converted into the digital video signal by the A / D conversion circuit 2. Namely, the analog video signal is pulse code modulated (PCM modulation), and the PCM video signal is written into the digital memory 4. The digital video signal written to the digital memory 4 is read by the read clock from the read clock generation circuit 6 supplied with the existing synchronization frequency, and the read video signal is supplied with the digital-analog (D / A) to which the read clock is supplied. A video signal, which is converted into an analog signal by the conversion circuit 5 and stabilized in time axis variation, is obtained at the output terminal 7.

On the other hand, in a video tape recorder, the clamping and switching of the video head are performed using the blanking period (vertical blanking period) of the video signal. In the case of an NTSC composite video signal, as shown in FIG. 2, the vertical sync pulse 8 exists before and after the equalization pulse 3H, which is used as the reference time axis in the vertical direction of the screen.

As described in the prior art, in contrast to a commercial video tape recorder, a time base compensator is generally not used in a home video tape recorder. Even if a time base compensator is used in a home video tape recorder, if the residual error containing the vertical sync pulse is the largest when the color burst signal is taken as the reference point of the time base correction, waveform distortion, skew distortion (unlike business VTRs) It is very difficult to reliably detect the vertical synchronizing signal from the reproduced signal where distortion, drop-out, etc. occur frequently. In addition, the possibility that the reference time axis in the vertical direction of the screen is dropped out increases. In particular, when the drop out noise 9 or the like enters near the vertical synchronizing pulse 8 during the blanking period as shown in FIG. 2, the detection of the vertical synchronizing pulse 8 becomes difficult, and the surface is disturbed in the vertical direction, Substantial degradation of image quality occurs.

Japanese Patent Laid-Open No. 63-194494 describes a method of recording a color video signal. In the color video signal recording method, the first and second color signals of the color video signal consisting of the luminance signal and the first and second color signals are converted in a line sequence manner, time-base compressed to 1/4, and then multiplexed in the luminance signal. . About twice the time base extension to split the multiplexed signal, that is, the color line sequence TCI (time compressed intergration) signal into two channel signals, and scan one or two time periods of one field of two channel signals By doing so, the color video signal is recorded simultaneously on two inclined tracks.

Japanese Patent Application No. 2-51248, which was not yet disclosed at the time the assignee of the present application filed the present invention, discloses the above-described recording method and a time axis error correction device (TBC) provided to the recording device, playback device, and playback device. Doing.

An example of a conventional video tape recorder and a time base corrector for recording a color video signal on a magnetic tape by the above-described recording method and reproducing a signal recorded from the gyro tape will be described.

First, the first and second color signals of the color video signal consisting of the luminance signal first and second color signals (other signals of red and blue) are converted in a line sequence manner, time-base compressed by 1/4, and in the luminance signal The multiplexed, multiplexed signal (i.e., TCI signal) is time-scaled by about twice, while the two-channel signal obtained by the mixing process is fed to the FM modulator circuit and FM modulated.

Incidentally, two sets or four rotating magnetic heads are mounted closely on the rotating drum of the tape guide device, and the head gaps of the rotating magnetic heads mounted closely to each other have different azimuth angles. In addition, the azimuth angles of the four rotating magnetic heads are sequentially recorded such that the recording azimuth angles of the four inclined tracks formed on the magnetic tape when the four rotating magnetic heads rotate one turn are + θ, -θ, + θ, -θ. Is selected to fluctuate.

A time-field extended TCI signal of one field is recorded so that two sets of FM-modulated signals are sequentially supplied to two sets of rotating magnetic heads so that two sets of two inclined tracks per rotation are formed on the magnetic tape. Thus, a time-base extended TCI signal of one frame is recorded such that four sets of inclined tracks of two channels per two revolutions are formed.

In the magnetic tape on which signals are recorded as described above, the two-channel signals on the paper tape are reproduced by two sets of different rotating magnetic heads having the same head arrangement and gap azimuth angle as the rotating magnetic head in the recording mode. The reproduced signals of the two channels are supplied to the FM demodulator circuit, respectively, and demodulated, and the demodulated signals are converted into analog signals in an analog form, written into respective time axis error correction memories, and read from thereto to correct the time axis errors.

A write clock signal containing jitter, generated on the basis of a horizontal synchronizing signal and a buster signal separated from the FM demodulated time base extended TCI signal, is supplied to two memories at the time of writing, while a read obtained from a fixed oscillator The clock signal is supplied to two memories at the time of reading.

Two channel signals from each memory are supplied and decoded to the common luminance signal decoder and the common chromaticity signal decoder. That is, a luminance signal and a line sequence chroma signal are respectively extracted from the two channel signals, the luminance signal and the line sequence chroma signal are time-base compressed by about half, and the line sequence chroma signal is extended by about 4 times the time axis, and a simultaneous chroma signal is obtained. The digital luminance signal and the digital red and blue difference signals thus produced are converted into analog signals in digital form, so that the original luminance signal, red and blue difference signals are obtained.

Based on the horizontal synchronizing signal and the burst signal respectively separated from the two channels of FM demodulated and time-base extended TCI signals, speed error signals are generated, respectively, and these speed error signals are read out from the time-base error correction memory. The clock signal obtained from the fixed oscillator is phase modulated by the speed error signal read out from the memory to generate a read clock signal, which is stored in a memory dedicated to matching the TCI signal, which reads the time base correcting memory and the D / A converter is supplied.

In the above-described time axis error correcting apparatus for a video tape recorder, the time axis of a pair of reproduced video signals generated by simultaneously reproducing video signals recorded respectively on a pair of inclined tracks on a magnetic tape by a pair of rotating magnetic heads. Two sets of circuits are needed to compensate for errors and speed errors. Therefore, the circuit arrangement of the time-base compensator of the prior art is complicated and the power consumption is quite large.

It is therefore an object of the present invention to provide an improved time base compensator that can address the above mentioned disadvantages and drawbacks encountered in the prior art.

In particular, it is an object of the present invention to provide a time axis corrector which can be prevented from disturbing the vertical synchronization on the screen even when the vertical synchronization pulse cannot be detected for reasons such as drop out.

Another object of the present invention is to provide a time axis corrector having a speed error correction function of a simple device,

Another object is to provide a time base corrector with speed error correction which can reduce power consumption.

According to an aspect of the present invention, an input video signal is written to the time base error correction memory based on a clock pulse synchronized with the synchronization signal of the input video signal, and the signal written to the time axis error correction memory is read synchronized with the reference synchronization signal. The time axis corrector, which reads on the basis of the clock pulses and corrects the time axis, includes a write circuit for writing a video signal, a memory in which the video signal is written, a circuit for reading a time axis corrected video signal from the memory, and a video signal. A first synchronous separation circuit for extracting the first synchronous signal, a second synchronous separation circuit for extracting the second synchronous signal from the video signal, and a write in which the memory is placed in a writable state based on the first synchronous signal A write-enabled signaling circuit for generating a possible signal and a drop out of the second synchronous signal; When the dropout detection circuit, and a dropout detection circuit for detecting a drop-out of the second sync signal comprises a circuit for generating a signal to disable the writing of the memory.

The above objects and other features, advantages, and the like of the present invention will become more apparent from the detailed description of the illustrated embodiments with reference to the accompanying drawings. Similar reference numerals are used for the same or similar parts in the drawings.

A first embodiment of a time base corrector according to the present invention will now be described with reference to FIGS. 3 and 4 (a) to 4 (h). FIG. 3 is a block diagram showing the time-base compensator of the present invention applied to a video tape recorder, and FIGS. 4 (a) to 4 (h) each illustrate the operation of the video tape recorder shown in FIG. Timing waveform diagram. In Fig. 3, the same reference numerals have been given the same parts corresponding to those of Fig. 1 and need not be described in detail.

Referring to FIG. 3, a reproduced video signal generated by reproducing a video signal recorded on a tape track of a video tape recorder by a rotating playhead is supplied to the input terminal 1. The reproduced video signal applied to the input terminal 1 is supplied to the demodulator 10 and demodulated. This demodulated video signal is fed to a low pass filter (hereafter simply referred to as LPF) 11 through which a signal of, for example, a sub-6 MHz band is passed, or the band is followed by a subsequent A / D. Limited for the transducer 2. The processed signal is supplied to the A / D converter 2 so that an analog reproduced video signal is converted into a digital video signal, and the reproduced digital video signal is supplied to, for example, a digital memory, and the digital video signal is supplied to a TBC memory. Is written in (4).

The video signal reproduced as the output of the demodulator 10 is supplied to the horizontal sync pulse detection circuit 12 and the vertical sync pulse detection circuit 15 as well as the low pass filter 11. In the horizontal synchronizing pulse detection circuit 12, a horizontal synchronizing pulse and a burst signal included in the reproduced video signal are detected, and the detected reproducing horizontal synchronizing pulses are WCK-PLL (phase locked loop) 13 and the counter 16. And a delay circuit 18. In the horizontal synchronizing pulse detection circuit 12, the reproduced horizontal synchronizing pulse is detected from the horizontal synchronizing pulse and the burst signal, and then supplied to the WCK-PLL 13 constituting the write clock generation circuit 3.

The WCK-PLL 13 compares the output of the reproduced horizontal sync pulse with a signal generated by frequency division of the output of the voltage controlled oscillator VCO, and controls the oscillation frequency of the VCO by the generated error voltage. It is arranged to obtain a write clock pulse 21 in accordance with the frequency of the applied reproduction video signal. The write clock pulse 21 is supplied to the clock terminals of the A / D converter 2 and the TBC memory 4. The PLL 13 includes a counter that counts the clock generated in the PLL 13 when the reproduced horizontal sync pulse cannot be detected. Since the count output from the counter in the PLL 13 is output to the adder circuit 14 as automatic H (AUTO-H), the output of the horizontal sync pulse detection circuit 12 does not lose the reproduced horizontal sync pulse. do. The regenerated horizontal sync pulse is supplied to the counter 16 and the delay circuit 18, and the counter 16 counts the regenerated horizontal sync pulses.

On the other hand, as shown in FIG. 4 (a), the reproduced video signal includes the vertical sync pulse 8 during the vertical blanking period VB of the vertical flyback blanking period.

This vertical sync pulse 8 is detected by the vertical sync pulse generating circuit 15 shown in FIG. 3 every field (in every frame or track) as shown in FIG. 4 (b). 4 (b) shows a state in which the vertical synchronizing pulse 8 'of the second field cannot be detected due to drop out or the like. As described above, in order to clear the counter by the regenerated vertical sync pulse 24 detected by the vertical sync pulse generation circuit 15, the vertical sync pulse 24 is applied to the erase terminal CLR of the counter 16. It is also supplied to the delay circuit 18. The counter 16 counts the regenerated horizontal sync pulses from the adder circuit 14, for example, counts 262 horizontal sync signals as shown in FIG. 4 (d), and if the write start signal 25 Is detected, the counter 16 is cleared or starts counting from the beginning.

The count output of the counter 16 is supplied to the ROM (lead only memory) 17 for the TBC memory 4, and the ROM 17 uses the output of the counter 16 as an address. If the vertical sync pulse 8 is continuously detected, the ROM 17 generates a low signal 26 as shown in FIG. 4 (e), while the vertical sync pulse is perpendicular to the fourth (e) degree. Once dropped as shown by the sync pulse 8 ', the address output of the counter 16 exceeds one vertical blanking period VB so that the output of the ROM 17 becomes a high level signal 27. When the output is supplied to the writable terminal EN of the counter 16, the counter 16 stops the counting operation as shown in FIG. 4 (d). At the same time, the output of ROM 17 remains a high level signal 27, which continues until the next second vertical sync pulse 8 is detected or the counter 16 is cleared.

The low level signal 26 and the high level signal 27 of the WE signal from the WE generation ROM 17 are applied to the writable terminal EN of the TBC memory 4, and the vertical sync pulse 8 can be detected. And only during one field (frame or track) period during which the high level signal 27 is output, the writing in the TBC memory 4 is prohibited. As a result, writing is prohibited in the TBC memory 4 during the second field period in which the vertical synchronizing pulse 8 'is not detected, but the write data 27 is stored.

Next, the read start signal 28 for the TBC memory 4 is correctly synchronized with the reference synchronization signal and supplied to the RST terminal of the TBC memory 4 as shown in FIG. 4 (f), and the read clock pulse ( 22 is supplied to the TBC memory 4, and the digital video signal from the TBC memory 4 is converted by the D / A converter 5 into an analog video signal and then output to the output terminal 7. The read data 30 from the TBC memory 4 at this time is shown in FIG. 4 (h). In this figure, the enhanced read data 30 'of the first field portion stored in the TBC memory 4 is output as data of the second field portion, and a vertical sync pulse 8' is generated from this second field portion. do.

According to this embodiment, it is possible to obtain a TBC capable of outputting the previous data stored in the TBC memory 4 at an accurate timing even when no vertical synchronizing pulse is detected.

Further, in the embodiment of the present invention, the read clock generation circuit 6 is arranged as shown in Fig. 5 when one field signal is divided into several tracks and recorded on a so-called high-vision video tape recorder or the like. do.

In particular, when signals recorded on two tracks in separate form are reproduced, the synchronization signals included in the reproduction signals from the two tracks are used as reference synchronization signals. Referring to Fig. 5, these reproduction synchronization signals are provided to the speed error detection circuits 31 and 32, respectively, in which the speed error signals V1 and V2 are derived, respectively.

These speed error signals V1 and V2 are added by the adder 33 and the level converting circuit 34 and converted into average values.

Assuming that the speed error signals V1 and V2 of the reproduction synchronization signal of each track are actually the same waveforms because magnetic heads (not shown) are arranged very closely, the speed error signals V1 and V2 are added and averaged. These signals are hardly affected by noise. Moreover, the read clock generation circuit 6 can be used by each track in common.

The output of the level conversion circuit 34 is supplied to the frequency control terminal of the VCO (not shown) of the PLL circuit 35. The oscillation output of the VCO and the output of the reference oscillator 36 are phase compared to obtain a read clock pulse 22 or the like of a predetermined phase. The PLL circuit 35 is currently commercially available on the market.

As described above, the field memory is used as the TBC memory 4 to perform pre-interpolation, while the pre-interpolation may be similarly executed by using a frame memory.

Moreover, when recording a signal of one field in a so-called separate recording method so that a signal of one field is recorded in several separated tracks, pre-segment interpolation is executed if one segment of memory is used, and one field of memory is used. Is used, pre-field interpolation is performed, and when one frame of memory is used, pre-frame interpolation is performed.

According to the above embodiment of the present invention, even when the vertical sync pulse is not detected due to drop-out or the like, it is possible to obtain a time axis corrector which can avoid the disturbance of the vertical sync with respect to the image.

A second embodiment of the time base corrector according to the present invention is described in detail below with reference to FIGS. 6 and 6 (a) to 7 (g).

In a second embodiment, the time base corrector of the present invention is provided in a video tape recorder.

First, the recording circuit of the video tape recorder will be briefly described, and then the playback circuit will be described. FIG. 6 is divided into FIG. 6 (a) and FIG. 6 (b) in order to be able to see the drawings of a moderately large scale.

The recording circuit of the video tape recorder will be described below. The first and second color signals of the color video signal consisting of the luminance signal and the first and second color signals (red and blue color difference signals) are converted in a line sequence manner, time-base compressed by a quarter-time compression ratio, and then luminance Multiplexed onto the signal. This multiplexed signal (the aforementioned TCI signal) is about twice the time-base extension, and the two channel signals provided by the shuffling process are provided to the FM modulator circuit and FM modulated.

In two or four sets of rotating magnetic heads mounted on the rotating drum of the tape guide device, the head gaps of the two closely arranged rotating magnetic heads are arranged to have different azimuth angles. Moreover, the head gap azimuth angles of the four rotating magnetic heads are in the order of + θ, -θ, + θ, -θ of the recording azimuth angles of the four inclined tracks formed on the magnetic tape each time the four rotating magnetic heads rotate once. It is determined to be different by + θ, -θ, + θ, -θ.

The two channel FM modulated signals are sequentially fed to two sets of rotating magnetic heads. Thus, one field of time-base extension TCI signal is recorded such that two sets of inclined tracks of two channels are formed on the magnetic tape for each rotation of the two sets of rotating magnetic heads. Thus, one frame of the time base-expansion TCI signal is recorded such that four sets of slope tracks of two channels are formed every two revolutions of the rotating magnetic head.

Hereinafter, the regeneration circuit will be described with reference to FIG. The magnetic tape on which signals are recorded by the above-described recording circuit is reproduced by the other two sets of rotating magnetic heads Ha and Hb. The two sets of rotating magnetic heads Ha and Hb are arranged with the same azimuth angle as the rotating magnetic heads of the recording circuit, so that two channel signals recorded on the magnetic tape are reproduced simultaneously.

In FIGS. 6 (a) and 6 (b), reference characters AK and BK denote circuits of channels A and B that are identically configured, respectively, and the read clock generation circuit 142 is each independent circuit AK and BK. Are jointly connected to

The reproduction signals of the two channels, that is, the reproduction signals of the four rotating magnetic heads Ha and Hb, are supplied to the FM demodulator circuits 41 and 121, respectively, and are FM-modulated to provide time-base extension TCI signals, respectively. These time base-extended TIC signals are supplied to low pass filters 42 and 122, band pass filters 45 and 125, and synchronous separation circuits 46 and 126, respectively. The outputs of band pass filters 45 and 125 are fed to burst signal separation circuits 47 and 127, respectively. The time-base extension signals from the low pass filters 42 and 122 are applied to the A / D converters 43 and 123, respectively, and converted into digital signals, and then supplied to the time-axis error correction memories 40 and 124, respectively, to write clocks. It is written based on the signal, which will be described later.

The PLL circuits 48 and 128 constitute a write clock signal generation circuit. In this circuit, the phase comparison outputs of the phase comparator circuits 49 and 129 are supplied to the voltage controlled oscillators 111 and 131 through the low pass filters 110 and 130.

Thus their oscillation frequencies are controlled. Oscillation signals from the voltage controlled oscillators 111 and 131 (the oscillation frequencies are six times larger than the color subcarrier frequency, for example six times greater) are fed to the N-division frequency dividers 112 and 132 (divide-by-Nfreq. Dividers). The frequency divider is then supplied to the phase comparators 49 and 129 for phase comparison with the burst signal from the burst signal separation circuits 47 and 127. Thereafter, the oscillation signals from the voltage controlled oscillators 111 and 131, i.e., the clock signals containing jitter components, are supplied to the A / D converters 43 and 123 and are respectively read as a read clock signal and the memory 40 as a read clock signal. And 124).

The phase comparator circuits 113 and 133 are reset by horizontal synchronization signals from the sync separation circuits 46 and 126, respectively. In the phase comparator circuits 113 and 133, the phase signals are compared with the burst signals from the frequency dividers 112 and 132, and these compared outputs, i.e., the speed error signals, are supplied to the A / D converters 114 and 134. Each is converted into a digital speed error signal. At this time, the digital speed error signals are supplied to the memory 115 and 135, respectively, and are written and read so as to be delayed by the same delay time provided by the writing and reading of the time base-extension TCI signal in the memory 40 and 142. .

The read clock signal generation circuit 142 common to each of the independent circuits AK and BK of the channels A and B is described below. First, the arrangement of the read clock signal generation circuit 142 will be described.

The clock signal from the clock oscillator 143 (this oscillator is a crystal oscillator and its oscillation frequency is six times N times the color subcarrier frequency, for example) is an S-division frequency divider (144). Is applied to the frequency divider, and the divided output from the divider is supplied to the phase comparator 146. The compared output from the phase comparator 146 is supplied to the mixing circuit 150 through the low pass filter 147.

On the other hand, the digital speed error signals read out from the memories 115 and 135 are supplied to the adder 140 and summed.

The added output from the adder 140 is supplied to the quarter count multiplier 141, where the level of the output is reduced in half and then converted by the D / A converter 148 into an analog signal. The analog speed error signal thus converted is supplied to the integrator 149 and integrated. An integrated output, that is, a ramp waveform signal whose cycle is equal to one horizontal cycle period, is supplied to the mixer circuit 150 and combined with the output of the low pass filter 147.

At this time, the oscillation frequency of the voltage controlled oscillator 151 is controlled by the output of the mixing circuit 150. The oscillation signal from the oscillator 151 is fed to an M-division frequency divider 152 (in this case M = S) and frequency divided into M. The frequency divided output from frequency divider 152 is supplied to phase comparator 146 and phase compared with the frequency divided output by frequency divider 144.

Therefore, the oscillation signal from the voltage controlled oscillator 151 is clock oscillator 143 by the signal integrated by the integrator 149 (integrates the analog speed error signal from this integrator D / A converter 148). The reference clock signal is equal to the signal resulting from the phase modulation of the signal. The oscillation signal from the oscillator 151 is supplied to the D / A converters 116 and 136 and also to the memories 40 and 124 as read clock signals, respectively.

Since the signals reproduced from the rotating magnetic heads Ha and Hb are reproduction signals from inclined tracks which are in close proximity to each other on the magnetic tape, the correlation between their speed errors (signals) is large. For this reason, the read clock signals supplied to the time base error correction memories 40 and 124 for correcting the speed error of the reproduction signals of the rotating magnetic heads Ha and Hb can be made common.

Decoded by two channels of time base-compression TCI decoders (not shown) read from memory 40 and 124 by read clock signals, i.e., each luminance signal of the two channels of TCI signals is time-compressed in half. Digital luminance signals are obtained. In addition, each line-sequence color signal is also time-base compressed, which is expanded by four times as a time axis and converted into a color signal. At this time, the first and second digital color signals are obtained and supplied to the digital luminance signals of the two channels and the D / A converters 116 and 136, respectively, by the common clock signal from the read clock signal generation circuit 142. Converted into analog signals. Thus, two channel analog luminance signals and first and second analog color signals are supplied to output terminals 118 and 138 through low pass filter 117, respectively.

The adder 140 is used to sum digital speed error signals from the memories 115 and 135, but can add the speed error signals in the form of analog speed error signals.

Further, by effectively using the memory 40 and 124 instead of the memory 115 and 135, the velocity error signals are inserted into the horizontal blanking period of the time base-extended TCI signals and written to and read from the memory 115 and 135. can do.

7 (a) to 7 (g) are signal timing charts in each section of the reproduction circuit shown in FIG. 7 (a) and 7 (b) show the reproduction video signals of the A and B channels when the time base-extended TCI signals are recorded directly on the magnetic tape, respectively. As shown in Figs. 7 (a) and 7 (b), because of the space between the head gaps of adjacent rotating magnetic heads, the playback video signal of the A channel is as high as 5H (H is one horizontal cycle period). Is played before the playback video signal. Thus, in the reproducing circuit of the second embodiment, the time base-extended TCI signal of the B channel is recorded on the magnetic tape before the time base-extended TCI signal of the A channel by 5H. Thus, the output video signals of the A and B channels from the time base correction memories 40 and 124 become signals having no delay time difference as shown in Figs. 7 (c) and 7 (d). This makes the use of magnetic tape more efficient.

7 (e), 7 (f) and 7 (g) show average values of the speed error signals of the A and B channels and the speed error signals of the A and B channels.

Although two rotating magnetic heads arranged closely to each other as described above can be used, three rotating magnetic heads or more heads can be used.

Other suitable systems may be used without being limited to color video signal recording and playback systems.

As described above, according to the second embodiment of the present invention, the time axis corrector has N (= 2, 3, 4, ...) time axis error correction memory (these are N playback video signals written therein.) Signals are obtained by simultaneously playing the video signals recorded on the N inclined tracks at the same time by a closely mounted N rotating magnetic head), and the N burst signals and the N horizontal sync signals separated from the N playback video signals. The N write clock signal generation circuit for generating the N write clock signals and supplying the N write clock signals to the N time axis error correction memory, and a speed error signal obtained based on the N burst signal and the N horizontal synchronization signal separated from the N playback video signals. It consists of a read clock signal generation circuit that generates a read clock signal resulting from the phase modulation of the signal and supplies it to the N time axis error correction memories. There. Therefore, the second embodiment of the time base corrector according to the present invention has the advantage that the power is reduced and the clocks do not overlap between channels.

Although preferred embodiments of the present invention have been described with reference to the drawings, the present invention is not limited to these embodiments, and those skilled in the art will appreciate that the present invention may be made without departing from the spirit and scope of the appended claims. May be modified and modified.

Claims (3)

The input video signal is written to the time base error correction memory based on the clock pulse synchronized with the synchronization signal of the input video signal, and the signal written to the time axis error correction memory receives the read clock pulse synchronized with the reference synchronization signal. A time base correction apparatus for reading on a basis of time axis correction, comprising: a) writing means for writing a video signal, b) a memory into which the video signal is written, and c) for reading a time axis corrected video signal from the memory. Means and d) first synchronous separation means for extracting a first synchronous signal from the video signal, e) second synchronous separation means for extracting a second synchronous signal from the video signal, and f) the first synchronous signal. A write-enabled signal for generating a write-enabled signal that makes the memory writable based on the signal Generating means, g) dropout detecting means for detecting a dropout of the second synchronous signal, and h) writing in the memory when the dropout detecting means detects a dropout of the second synchronous signal. And a means for generating a signal that makes it impossible. 2. The apparatus of claim 1, wherein the write-enabled signal generating means comprises a counter for counting the number of the first synchronous signals, and a read-only memory (ROM) for generating a predetermined pattern signal in response to the output of the counter. Time base compensation device. 2. The time axis correction apparatus according to claim 1, wherein an output signal of the drop out detection means is supplied to an erase terminal of the counter to clear the counter in response to the second synchronous signal.

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