JP2805097B2 - Time axis error correction device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a time axis error correction device (hereinafter referred to as TBC) suitable for use in a home VTR or the like.

[Summary of the Invention]

The first invention of the present invention is a T
For BC, based on the clock pulse synchronized with the horizontal synchronization signal in the input video signal, write the input video signal to the memory for time axis error correction, read the write signal with the read clock pulse that matches the reference signal, and In a time axis error correction device configured to correct an error, when a first vertical synchronization signal in an input video signal is lost, writing of the input video signal to a time axis error correction memory is prohibited. The time axis error is corrected with the input video signal already written until the detection of the vertical synchronization signal No. 2.

According to a second aspect of the present invention, based on a write clock pulse synchronized with a horizontal synchronizing signal in an input video signal, an input video signal is written to a memory for time axis error correction, and a read clock in which the write signal matches a reference signal. A TBC which reads out pulses and corrects a time axis error, a vertical sync pulse generating means for detecting a vertical sync pulse from an input video signal and generating a read vertical sync pulse, and a write clock pulse and a read vertical sync. A pulse is supplied, a delay means for generating a write start signal to the TBC memory, a write clock pulse and a reproduction vertical synchronizing pulse are supplied, and a count means is counted by the write clock pulse, and a count value of the count means is inputted. Output a write inhibit signal that inhibits writing to the TBC memory using the count value as an address. And a write inhibit signal generating means that, the writing start signal and write inhibit signal
A time axis error correction device for supplying to a memory for TBC and interpolating a preceding value of a vertical synchronization signal of write data output of a write inhibit signal based on a read start signal obtained from a read clock pulse. Thus, in the first and second aspects of the present invention, even when a vertical synchronization signal cannot be detected due to dropout or the like, an image without vertical synchronization disturbance can be displayed.

[Conventional technology]

Conventional VTRs for household use, which are commonly used in the past, convert the signal to a low-frequency range and return it to the original high-frequency range by the heterodyne method during reproduction.The chroma signal is a double heterodyne using a crystal oscillator. Method, the time-based fluctuation is removed, and the luminance signal is corrected for the time-axis fluctuation by the AFC of the horizontal scanning circuit of the receiver, so the TBC is not generally used. On the other hand, the direct color process method (1 inch helical In a commercial VTR with a 4-head VTR, etc., the TBC is often used because the luminance signal and the chroma signal are not separated and the interleave relationship is maintained.

An example of such a TBC will be described with reference to FIG. 3. A video signal to be subjected to time axis correction is input to an input terminal (1) in FIG. 3, and this video signal is converted into an analog-to-digital converter (hereinafter A / D converter). D) and (2) and the write clock generation circuit (3). The write clock generation circuit (3) generates a write clock corresponding to the time axis fluctuation included in the video signal, samples the luminance signal having the time axis fluctuation with the above write clock, and analogizes the signal by the A / D (2). The video signal is digitized, that is, converted into PCM, written in the digital memory (4), and the video signal written in the memory (4) is read by the read clock of the read clock generation circuit (6) supplied with the reference synchronization frequency. The digital signal is read out and returned to the video signal by the digital-analog conversion circuit (5) to which the read clock is supplied, so that the output terminal (7) obtains a video signal whose time base fluctuation is stabilized.

On the other hand, the VTR uses a blanking period (vertical blanking period) of a video signal to switch between a clamp and a video head. During this blanking period, for example,
In the television composite video signal of the NTSC system, there is a vertical synchronization pulse (8) before and after the equalization pulse 3H as shown in FIG. 4, and the TBC uses this as a reference time axis in the vertical direction of the screen.

[Problems to be solved by the invention]

As explained in the previous example, unlike commercial VTRs, TBCs are not commonly used in home VTRs.However, even when TBCs are used in home VTRs, the reference point for time axis correction is a color burst. If the residual error including the vertical sync pulse is large, it is difficult to reliably detect the vertical sync signal from the reproduced signal with many waveform distortions, skew distortions, dropouts, etc. unlike commercial VTRs For example, the possibility that the reference time axis in the vertical direction of the screen is lost is high. That is, as shown in FIG. 4, if a dropout or noise (9) is mixed in the vicinity of the vertical synchronization pulse (8) during the blanking period, the detection of the vertical synchronization pulse (8) becomes difficult, and the screen is vertically displaced. Disturbance causes a problem that image quality is greatly deteriorated.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and an object of the present invention is to generate a vertical synchronization disturbance on a screen even when a vertical synchronization pulse (8) cannot be detected due to dropout or the like. Not to try to provide TBC.

[Means for solving the problem]

As shown in FIGS. 1 and 2, the TBC of the first invention is based on a clock pulse (21) synchronized with a horizontal synchronization signal in an input video signal (20). TBC (19) which writes an input video signal (20) to a memory for time axis error correction (4) and reads a write signal with a read clock pulse (22) that matches the reference signal to correct the time axis error When the first vertical synchronizing signal (8 ') in the input video signal (20) is lost, writing of the input video signal (20) to the time-time error correction memory (4) is prohibited, The time axis error is corrected with the input video signal already written until the detection of the second vertical synchronizing signal (8).

The second invention is based on a write clock pulse (21) synchronized with a horizontal synchronization signal in an input video signal (20).
A TBC (19) in which an input video signal (20) is written to a TBC memory (4), and a write signal is read out with a read clock pulse (22) that matches a reference signal to correct a time error. , Vertical sync pulse (24) detected by detecting vertical sync pulse (8) from input video signal (20)
And a delay means for receiving a write clock pulse (21) and a reproduced vertical sync pulse (24) to generate a write start signal (25) for the TBC memory (4). (18), a writing clock pulse (21) and a reproducing vertical synchronizing pulse (24) are supplied, and counting means (16) counted by the writing clock pulse (21); and a count value of the counting means (16) are input. A write inhibit signal generating means (17) for outputting a write inhibit signal (27) for inhibiting writing to the TBC memory (4) using the counted value as an address; a write start signal (25) and a write inhibit signal (27). ) Is supplied to the TBC memory (4) and the write data in which the write inhibit signal (27) is output based on the read start signal (28) obtained from the read clock pulse (22). It is obtained by a time base error correcting apparatus characterized by comprising pre-value interpolation to the vertical synchronizing signal of the motor.

[Action]

According to the TBC (19) of the present invention, even if the vertical synchronization pulse cannot be detected during the blanking period and the vertical synchronization pulse cannot be detected, the video signal track is stored in the memory ( Since the previous value interpolation is performed by prohibiting writing to 4),
It is possible to eliminate such an adverse effect that vertical synchronism is disturbed on the screen, the screen flows, and the screen becomes completely invisible.

〔Example〕

An embodiment of the TBC of the present invention will be described below with reference to FIGS. FIG. 1 is a system diagram when the TBC of the present invention is arranged in a DTR, and FIG. 2 is a timing waveform diagram for explaining its operation.

In FIG. 1, a reproduced video signal obtained by reproducing a video signal recorded on a VTR tape track by a rotary reproducing head is supplied to an input terminal (1), supplied to a demodulator (10), and demodulated. The demodulated video signal is supplied to a low-pass filter (hereinafter, referred to as LPF) (11), for example, to pass a band of 6 MHz or less, and to limit the band for A / D (2) at the subsequent stage, and / D (2). In the A / D (2), the analog reproduced video signal is converted into a digital reproduced video signal.
A video signal is written to the memory (4).

The reproduced video signal, which is the output signal of the demodulator (10), is supplied to a horizontal synchronization pulse detection circuit (12) and a vertical synchronization pulse generation circuit (15) in addition to the LPF (11). ) Detects the horizontal synchronizing pulse and the burst signal included in the reproduced video signal, and supplies the reproduced horizontal synchronizing pulse (hereinafter referred to as H) to the WCK-PLL (13), the counter circuit (16), and the delay circuit (18). I do. The horizontal synchronizing pulse generator (12) detects H from the horizontal synchronizing pulse and the burst signal, and supplies H to the WCK-PLL constituting the write clock generating circuit (3). WCK-PLL (13) is H and VC
A phase comparison is performed between the output of the O (Voltage Controlled Oscillator) and the divided signal, and the error voltage controls the oscillation frequency of the VCO to generate a write clock pulse (21) that tracks the frequency of the input reproduced video signal. Get, A / D (2)
And the clock terminal of the TBC memory (4). PLL
(13) When H cannot be detected in PL
It has a counter that counts the clock generated in L, and outputs the counter output as H (AUTO H) to the adder circuit (14), so that the horizontal synchronization pulse detection circuit (12)
Is configured so that H does not escape from the output. Such H is supplied to the counter (16) and the delay circuit (18).
The counter (16) counts the above H.

On the other hand, as shown in FIG. 2A, the reproduced video signal includes a vertical synchronizing pulse (8) in the vertical blanking period VB of the vertical blanking period. Such vertical sync pulse (8)
Is detected for each field (frame or track) as shown in FIG. 2B by the vertical synchronization pulse generation circuit (15) shown in FIG. FIG. 2B shows a case where the vertical synchronization pulse (8 ') of the second field cannot be detected due to dropout or the like. In this way, in order to clear the counter (16) with the reproduced vertical sync pulse (24) detected by the vertical sync pulse generating circuit (15), the reproduced vertical sync pulse (24) is cleared by the clear terminal CLR of the counter (16). And to the delay circuit (18). The write start signal (25) from the delay circuit (18) to the memory (4) is
It is obtained as shown in FIG. In the counter (16), the addition circuit (1
H from step 4) is counted, for example, 262H is counted as shown in FIG. 2D. When a write start signal (25) is detected, the counter (16) is cleared and starts counting from the beginning. The count output of the counter (16) is TBC
The memory (4) is supplied to a ROM (17) for generating a write enable (hereinafter referred to as WE), and the ROM (17) is provided with a counter (16)
When the vertical synchronizing pulse (8) is continuously detected, the outputs of the ROM (17) all output a low signal (26) as shown in FIG. If it exits without being detected like the pulse (8 '), the counter (1
The address output of (6) exceeds one vertical blanking period VB, and the output of the ROM (17) becomes a high signal (27). When this output is supplied to the EN terminal of the counter, the counter (1
6) Stops the counter operation as shown in FIG. 2D. R at the same time
The output of OM (17) remains at the high signal (27) and continues until the next second vertical sync pulse (8) is detected or the counter (16) is cleared.

The low and high signals (26) and (27) of the WE signal obtained from the ROM (17) for generating WE are supplied to the WE terminal of the TBC memory (4), and the vertical synchronization pulse (8) cannot be detected. Writing to the TBC memory (4) is prohibited for only one field (frame or track) period during which the high signal (27) is output. As a result, as shown in FIG. 2G, the TBC memory (4) is not written in the second field period in which the vertical synchronizing pulse (8 ') cannot be detected. Stored in the memory (4). here,
In this example, the read start signal (28) of the TBC (4) correctly synchronized with the reference synchronization signal is supplied to the RST terminal of the TBC memory (4) and the read clock pulse (22) as shown in FIG. 2F. , D / A (5), and converts the video signal to an output terminal (7). At this time, the read data (30) from the TBC memory (4) has the second field portion where the vertical synchronization pulse (8 ') is missing as shown in FIG. This means that the interpolation read data (30 ') of one field portion is output.

That is, according to the present example, a TBC that can output the previous data already stored in the TBC memory (4) at a correct timing when a vertical synchronization pulse cannot be detected is obtained.

In the above case, the previous value interpolation is performed using the field memory as the TBC memory (4), but the interpolation can be similarly performed using the frame memory. HDTV VT
Even when segment recording for dividing and recording one field signal into several tracks as used in R and the like is performed, when a memory for one segment is used, interpolation of the previous segment is performed, and memory for one field is used. If this is the case, it is clear that the preceding field interpolation is performed, and in the case of a memory for one frame, the preceding frame interpolation is apparent, and it is apparent that various changes can be made without departing from the gist of the present invention.

〔The invention's effect〕

According to the present invention, even if a vertical synchronization pulse cannot be detected due to dropout or the like, a TBC that does not cause vertical synchronization disturbance on a screen can be obtained. In particular, a still image can be completely interpolated by performing frame interpolation.

[Brief description of the drawings]

1 is a system diagram showing one embodiment of the TBC of the present invention, FIG. 2 is a waveform diagram showing the timing of the TBC in FIG. 1, FIG. 3 is a system diagram of a conventional TBC, and FIG. FIG. 4 is an explanatory diagram of a pulse waveform. (2) A / D, (4) TBC memory, (5) D / A,
(6) is a read clock generation circuit, (12) is a horizontal synchronization pulse detection circuit, (13) is a PLL, (15) is a vertical synchronization pulse generation circuit, (16) is a counter, and (17) is a WE generation ROM. is there.

Claims (2)

(57) [Claims] An input video signal is written to a memory for correcting a time axis error based on a clock pulse synchronized with a horizontal synchronizing signal in the input video signal, and the write signal is read by a read clock pulse that matches a reference signal. A time axis error correction device for correcting a time axis error by inputting the input video signal to the time axis error correction memory when the first vertical synchronization signal in the input video signal is lost. A time axis error correction device wherein writing is prohibited and a time axis error is corrected with an input video signal already written until a second vertical synchronization signal is detected. 2. An input video signal is written to a memory for correcting a time base error based on a write clock pulse synchronized with a horizontal synchronizing signal in the input video signal, and a write signal is read by a read clock pulse that matches a reference signal. A vertical synchronization pulse generating means for detecting a vertical synchronization pulse from the input video signal to generate a reproduced vertical synchronization pulse; and Delay means for supplying the reproduced vertical synchronizing pulse and generating a write start signal to the memory for time axis error correction; and supplying the write clock pulse and the reproduced vertical synchronizing pulse and counting by the write clock pulse. Means, and the count value of the counting means is inputted, and the count value is used as an address, Write-inhibition signal generating means for outputting a write-inhibit signal for inhibiting the writing to the inter-axis correction memory; supplying the write start signal and the write-inhibition signal to the time-axis correction memory; A time axis error correction apparatus comprising a vertical synchronization signal of a write data output from the write inhibit signal and a preceding value interpolation based on the obtained read start signal.