JPH05316468A - Noise reducer - Google Patents

Abstract

PURPOSE:To control a noise reduction quantity in accordance with the movement of an image by a simple constitution. CONSTITUTION:A subtracter 64 detects the difference between the video signals of before/after by one field. The piece of difference data is provided for integrators 67 and 68, and the integrator 67 integrates difference data corresponding to a lump signal. On the other hand, the integrator 68 integrates difference data corresponding to a luminance signal. A data correcting circuit 69 corrects the output of the integrator 68 into a value corresponding to the integration time of the integrator 67. A comparator 70 compares the output of the integrator 67 and the data correcting circuit 69 and outputs a signal corresponding to the result of comparing to a control signal generator 72, which generates a control signal corresponding to the output of the comparator 70 and controls the limit characteristic of a limiter 66.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a noise reducer suitable for use in an analog video tape recorder for high definition, for example.

[0002]

2. Description of the Related Art In a video tape recorder, a video signal is recorded on or reproduced from a magnetic tape by a magnetic head. In a high-definition video tape recorder, a pair of magnetic heads for A channel and one for B channel are provided as the magnetic heads. By rotating this magnetic head at double speed, the video signal of one field is recorded on the video track of two segments and the video signal of one frame is recorded on the video track of four segments. ..

If the characteristics of the magnetic head vary, or if a magnetic tape of poor quality is used, the image reproduced from the magnetic tape deteriorates. To improve this, a noise reducer is inserted in the reproduction system.

[0004]

When this noise reduce process is performed, the afterimage becomes noticeable especially in the image. Therefore, it has been proposed to detect the movement of an image and change the noise reduction amount between a still image and a moving image.

However, the conventional device has a problem that the accuracy of detecting a still image and a moving image is poor, and it is difficult to control the noise reduction amount correctly. Further, there has been a problem that an attempt to improve the detection accuracy results in a large scale, a large apparatus, and a high cost.

The present invention has been made in view of such a situation, and it is possible to accurately control the noise reduce amount with a simple structure and to reduce the cost.

[0007]

A noise reducer according to the present invention comprises a subtracter 64 as a difference detecting means for detecting a difference between video signals of one field or one frame before and after,
A limiter 66 and a subtractor 62 as a synthesizing means for synthesizing the difference detected by the subtractor 64 with the video signal, and a component corresponding to a ramp signal as a predetermined reference signal among the differences detected by the subtractor 64. , A comparator 70 as a comparing means for comparing the component corresponding to the luminance signal,
A control signal generator 72 is provided as a control means for controlling the limiter 66 corresponding to the comparison result of the comparator 70.

[0008]

In the noise reducer having the above structure, the limit amount in the limiter 66 is controlled according to the result of comparison between the component corresponding to the ramp signal and the component corresponding to the luminance signal. Therefore, with a simple configuration, the noise reduction amount can be accurately controlled in accordance with a still image or a moving image.

[0009]

1 and 2 are block diagrams showing the structures of a recording system and a reproducing system of a high-definition analog video tape recorder to which the noise reducer of the present invention is applied. In FIG. 1 showing the configuration of the recording system, the luminance signal (Y) is limited to a predetermined band by the low pass filter 1 and then A /
A / D conversion is performed by the D converter 2. The luminance signal converted into a digital signal by the A / D converter 2 is emphasized by the vertical non-linear emphasis circuit 3 and then TD
It is supplied to the M circuit 10.

Similarly, the color difference signal (BY) is supplied to the TDM circuit 10 via the low-pass filter 4, the A / D converter 5, and the vertical non-linear emphasis circuit 6. Further, the color difference signal (RY) is also supplied to the TDM circuit 10 via the low pass filter 7, the A / D converter 8 and the vertical non-linear emphasis circuit 9.

The TDM circuit 10 includes color difference signals BY, R-.
Y is compressed on the time axis and time-division multiplexed with the luminance signal Y. At this time, the color difference signals are line-sequentially multiplexed. Then, in this TDM circuit 10, data for every 1H is shuffled to generate a signal for A channel and a signal for B channel.

The recording clock generating circuit 26 outputs a luminance signal Y
Generates a clock signal that is synchronized with the synchronization signal included in
Output to each part.

The signal for the A channel generated by the TDM circuit 10 is a horizontal nonlinear emphasis circuit 11
After being emphasized by, the D / A converter 12 performs D / A conversion. The analog signal output from the D / A converter 12 is band-limited by the low-pass filter 13 and then emphasized by the emphasis circuit 14. Then, after further FM modulation by the FM modulation circuit 15, it is amplified by the recording amplifier 16 and supplied to the rotary magnetic head Ha or Hc for A channel.

At this time, the synchronizing signal and the color burst signal output from the generating circuit 25 are superimposed on the signal output from the horizontal non-linear emphasis circuit 11 and supplied to the rotary magnetic heads Ha and Hc.

Similarly, B output from the TDM circuit 10
The signal for the channel includes a horizontal non-linear emphasis circuit 18, a D / A converter 19, a low pass filter 20, an emphasis circuit 21, an FM modulator 22, and a recording amplifier 23.
Is supplied to the head Hb or Hd for the B channel via.

As shown in FIG. 3, the A-channel heads Ha and Hc are mounted on the rotary drum 27 at a distance of 180 degrees. Similarly, head Hb for B channel
And Hd are also mounted 180 degrees apart. Also,
The heads Ha and Hb are arranged close to each other, and similarly, the magnetic heads Hc and Hd are also arranged close to each other. The rotary heads Ha and Hb simultaneously record signals for one segment of A channel and B channel. Similarly, the rotary heads Hc and Hd simultaneously record the signals of the A and B channels of one segment.

FIG. 4 shows a track pattern formed by the rotary heads Ha to Hd. As shown in the figure, the rotary heads Ha and Hb allow the tracks 17a and 1
7b is formed. Tracks 17c and 17d are formed by the rotary heads Hc and Hd. A video signal for one field is recorded on these four tracks (2 segments). Therefore, the video signal for one frame is recorded in four segments.

FIG. 5 shows the shuffling state of the video signal for each line in each segment. As shown in the figure, the CW signal (CW), the segment synchronization signal (VL) and the ramp signal (R) are sequentially recorded in each segment in the preamble section of 3H. Then, in the subsequent 136H section, a superimposed signal of the shuffled luminance signal and color difference signal is recorded every 1H.

Next, the reproducing system shown in FIG. 2 will be described. Rotating head Ha or Hc for A channel
The reproduced signal is amplified by the head amplifier 31, then input to the FM demodulator 32, and FM demodulated.
The signal output from the FM demodulator 32 is de-emphasized by the de-emphasis circuit 33 and is limited to a predetermined band by the low-pass filter 34. The signal output from the low-pass filter 34 is the A / D converter 35.
After being A / D converted by, the signal is de-emphasized by the horizontal non-linear de-emphasis circuit 36 and supplied to the noise reducer 46 of the TDM circuit 37.

The reproduced clock generating circuit 44 separates the synchronizing signal from the signal output from the low pass filter 34, generates a clock synchronized with this synchronizing signal, and outputs it to each section.

Similarly, the magnetic head Hb for the B channel is used.
Alternatively, the signal reproduced by Hd is the head amplifier 3
8, the FM demodulator 39, the de-emphasis circuit 40, the low-pass filter 41, the A / D converter 42, and the horizontal non-linear de-emphasis circuit 43 are supplied to the noise reducer 47 for the B channel of the TDM circuit 37. The output of the low-pass filter 41 is supplied to the reproduction clock generation circuit 45, and the reproduction clock is generated.

In the noise reducers 46 and 47,
As described below, the noise reduce process and the time axis correction process are performed. The signals output from the noise reducers 46 and 47 are supplied to a decoder 48, where they are subjected to processing such as deshuffling and time-axis expansion, and are processed by a luminance signal Y, a color difference signal BY, and a color difference signal RY. Are separated into

The luminance signal Y is de-emphasized by the vertical non-linear de-emphasis circuit 49, and then D /
The signal is D / A converted by the A converter 50, band-limited by the low-pass filter 51, and then output to a circuit (not shown). Similarly, the color difference signal BY is output to a circuit (not shown) via the vertical non-linear de-emphasis circuit 52, the D / A converter 53, and the low-pass filter 54, and the color difference signal R-Y is outputted by the vertical non-linear de-emphasis circuit. Circuit 5
5, through the D / A converter 56 and the low pass filter 57 to be output to a circuit (not shown).

FIG. 6 shows a configuration example of the noise reducers 46 and 47. In the noise reducer 46,
The signal input from the horizontal non-linear de-emphasis circuit 36 is input to the subtractor 64 and the delay circuit 6
After being delayed by 1 for n clocks, it is supplied to the subtractor 62. The subtractor 62 subtracts the signal supplied from the limiter 66 from the signal supplied from the delay circuit 61 and supplies the subtracted signal to the 1-field memory 63. Memory 6
3 is the delay circuit 61 based on the number of clocks for one field.
Then, the signal is delayed by the clock obtained by subtracting n clocks from the above signal and output. That is, the combined delay amount of the delay circuit 61 and the memory 63 is one field of the adjustment.

In this embodiment, one field is used as a unit for processing, but it goes without saying that one frame can be used as a unit for processing.

The data read from the memory 63 is supplied to the subtractor 64. The subtractor 64 subtracts the signal of one field before read from the memory 63 from the signal of the current field, delays the difference by n clocks by the delay circuit 65, and then outputs the difference to the limiter 66. Further, the difference data output by the subtractor 64 is supplied to the integrators 67 and 68. The integrator 67 integrates the difference data corresponding to a preset predetermined reference signal.
As the reference signal, the CW signal, segment sync signal, ramp signal, etc. shown in FIG. 5 can be used.
Alternatively, it is also possible to insert a special reference signal. In the embodiment, the ramp signal is used as the reference signal.

The integrator 68 integrates the difference data substantially corresponding to the luminance signal. The data correction circuit 69 corrects the output of the integrator 68 to be data corresponding to the integrator 67. For example, the integration time in the integrator 67 is t ₁
When the integration time in the integrator 68 is t ₂ , the data correction circuit 69 outputs t ₁ / t ₂ to the output of the integrator 68.
Is multiplied by. The comparator 70 compares the output of the integrator 67 with the output of the data correction circuit 69, and outputs a signal corresponding to the comparison result to the adder 71.

The configuration of the processing circuit for the A channel has been described above. The delay circuit 8 as the processing circuit for the B channel corresponds to each circuit of the delay circuit 61 to the comparator 70 described above.
1 to the comparator 90 are provided. And the comparator 90
Is supplied to the adder 71 and is added to the output of the comparator 70. The output of the adder 71 is supplied to the control signal generator 72, and the output of the control signal generator 72 is supplied to the limiters 66 and 86, respectively.

Next, the operation will be described. The input signal is delayed by one field in total by passing through the paths of the delay circuit 61, the subtractor 62, and the memory 63. The subtracter 64 subtracts the data one field before output from the memory 63 from the data currently input. Since the video signal has a strong correlation for each field, the difference data becomes a signal substantially proportional to the noise included in the reproduced video signal. The difference data is delayed by n clocks by the delay circuit 65 and then supplied to the subtractor 62 via the limiter 66. Subtractor 62
The noise component supplied from the limiter 66 is subtracted from the video signal supplied from the delay circuit 61, and the video signal from which the noise component has been removed is output to the memory 63. In this way, the noise component is removed from the signal written in and read from the memory 63.

On the other hand, the integrator 67 integrates the difference data corresponding to the ramp signal component among the difference data output by the subtractor 64. As shown in FIG. 7, the ramp signal is inserted after the burst signal and the ID signal in the 1H signal. As shown in FIG. 5, this ramp signal is generated only in the period of 1H in one segment. The integrator 67 executes the integration operation in the section of 1H in which the signal shown as the synchronization signal in FIG. 7 is logic H.

On the other hand, the integrator 68 substantially integrates the noise component corresponding to the period in which the luminance signal is inserted.
Then, the integrated value is converted by the data correction circuit 69 into a value corresponding to the integration time by the integrator 67 as described above. Output of integrator 67 and data correction circuit 6
The outputs of 9 are almost equal when the still image is being reproduced. On the other hand, when a moving image is being reproduced, the outputs of the two are significantly different. The comparator 70 generates a first signal when the outputs of the integrator 67 and the data correction circuit 69 are substantially equal to each other, and outputs a second signal when the output of the integrator 67 is smaller than the output of the data correction circuit 69. When the output of the integrator 67 is considerably smaller than the output of the data correction circuit 69,
The third signal is output.

Similar processing is performed in the B-channel circuit including the delay circuit 81 to the comparator 90, and the comparator 90 outputs the first signal, the second signal, or the third signal. The adder 71 adds the outputs of the comparator 70 and the comparator 90 and outputs the result to the control signal generator 72. The control signal generator 72 sets the limit amount in the limiter 66 to be large when both the outputs of the comparators 70 and 90 are the first signals. For the second signal, the limit level is set to a medium level, and for the third signal, the limit level is set to the smallest value.

FIG. 8 shows limit characteristics of the limiters 66 and 86. When the signal supplied from the adder 71 is small (when it is a still image), the control signal generator 72 controls so that the limit characteristic becomes large as shown in FIGS. 8A and 8B. As a result, many of the signals input from the delay circuit 65 or 85 are output to the subtractor 62 or 82. That is, the noise reduction amount becomes large. On the other hand, when the signal supplied from the adder 71 is large (when it is a moving image), the limit level is controlled to be small. As a result, the noise reduce amount supplied to the subtractor 62 or 82 is reduced. Therefore, it is possible to improve the S / N without making the afterimage conspicuous regardless of the still image and the moving image.

The delay circuit 65 has a delay time corresponding to the delay time by the signal processing of the integrator 67 to the control signal generator 72, and the data input from the delay circuit 65 and the control signal generator 72 are input. The timing of the data is matched. The delay circuit 61 also adjusts the timing of the two data input to the subtractor 62.

FIG. 9 shows a second embodiment. In this embodiment, a circuit for distinguishing a still image from a moving image is
The A channel is composed of the integrator 101 to the hold circuit 107, and the B channel is composed of the integrator 111 to the hold circuit 117.
In the A channel, the output of the subtractor 64 is the integrator 1
After being integrated by 01, it is supplied to the hold circuit 102. Then, the hold circuit 102
Is supplied to the memory 104 and the subtractor 105 of the circuit 103. The subtractor 105 subtracts the output of the memory 104 from the output of the hold circuit 102 and outputs it to the integrator 106. The output of the integrator 106 is
It is supplied to the adder 71 via the hold circuit 107.

The B-channel integrator 111 to the hold circuit 117 are also constructed similarly to the A-channel integrator 101 to the hold circuit 107.

Furthermore, in this embodiment, the A channel memory 104 and the B channel memory 114 are used.
The output of is supplied to the adder 109, added, and then output to the control signal generator 110.
Then, one of the outputs of the control signal generators 72 and 110 is selected by the selector 108, and the limiter 6
6,86. Other configurations are similar to those in FIG.

Next, the operation will be described with reference to the timing charts of FIGS. The difference data (noise component) output from the A-channel subtractor 64 is supplied to the integrator 101. This integrator 10
1 integrates this noise component while the sync signal (FIG. 10B) is logic H. As described above with reference to FIG. 7, the section in which the synchronization signal is logic H corresponds to the section in which the ramp signal is inserted. In addition, the integrator 101
Resets the integrated value every time reset pulse 1 (ARPLS1) (FIG. 10C) is input. As shown in FIG. 10, the synchronization signal (FIG. 10B) and the reset pulse 1 (FIG. 10C) are generated every 1H of the reproduction signal (FIG. 10A) reproduced by the head Ha or Hc.

As described with reference to FIG. 5, the ramp signal is inserted only in the 1H section of the preamble of one track, and the normal luminance signal is inserted in the following 136H section. Therefore, the integrator 101
Will integrate and output the signal in the section where the synchronization signal for each H is H. The hold circuit 102 holds the output of the integrator 101 every time the hold pulse 1 (AHPLS1) (FIG. 10D) is input. Since this hold pulse 1 is also generated every 1H, the hold circuit 102 holds the integrated value output from the integrator 101 every 1H and outputs it to the memory 104 and the subtractor 103.

The memory 104 is a memory pulse (AMPL).
S) (FIG. 10E) is supplied every time the hold circuit 102 is supplied.
Memorize the output of. As shown in FIG. 10, this memory pulse is generated once in one track (one segment) immediately after the generation of the ramp signal. That is, the hold circuit 102
Each time the outputs a noise component corresponding to the ramp signal, the noise component is stored in the memory 104. Then, this stored value is held until the noise component corresponding to the next ramp signal is supplied. Therefore, the subtractor 105
The noise component corresponding to the ramp signal stored in the memory 104 is subtracted from the noise component corresponding to each H luminance signal output from the hold circuit 102.

The output of the subtractor 105 is supplied to the integrator 106. The integrator 106 integrates the data output from the subtractor 105 and outputs the integrated output from the hold circuit 107.
Output to. The reset pulse 2 (ARPLS2) (see FIG.
0F) and hold pulse 2 (AHPLS2) (FIG. 10)
G) is supplied, the integrator 106 resets the integrated output each time the reset pulse 2 is supplied, and the hold circuit 1
07 is an integrator 10 every time the hold pulse 2 is input.
Hold the output of 6. As shown in FIG. 10, the reset pulse 2 and the hold pulse 2 are output once per field. Therefore, the hold circuit 107 outputs data obtained by integrating the difference between the noise component corresponding to the luminance signal and the noise component corresponding to the ramp signal over the period of one field.

The integrator 111 to the hold circuit 117 in the B channel are also the integrators 10 in the A channel.
1 to the hold circuit 107, the hold circuit 117 outputs data obtained by integrating the noise component corresponding to the ramp signal from the noise component corresponding to the B channel luminance signal for one field. Incidentally, B
A timing chart of the operation of the integrator 111 to the hold circuit 117 of the channel is as shown in FIG. Since this FIG. 11 is substantially the same as FIG. 10, its description is omitted. The adder 71 adds the outputs of the hold circuits 107 and 117 and outputs the control signal generator 7
Output to 2. The control signal generator 72 outputs data as shown in FIG. 12, for example. That is, when the data input from the adder 71 is larger than I ₁ , 0 is output, and as the size decreases, the output is increased by 1 step by step. Output. Therefore, the data output by the control signal generator 72 is
It can be represented by 3-bit data.

On the other hand, the adder 109 adds the noise components corresponding to the ramp signals respectively stored in the A-channel memory 104 and the B-channel memory 114, and outputs them to the control signal generator 110. The output of the adder 109 is inversely proportional to S / N. Control signal generator 110
Have input / output characteristics as shown in FIG. That is, when the input data from the adder 109 is larger than I ₂ , 7 is output, and as the input becomes smaller, the output decreases by 1 step by step, and when the input is below a predetermined value, 0 is output. ..

The selector 108 selects one of the outputs of the control signal generators 72 and 110, which has a smaller level, and outputs it to the limiters 66 and 86. As shown in FIG. 8, the limiters 66 and 86 increase the limit level (increase the noise reduce amount) when the control signal (0 to 7) supplied from the selector 108 is large, and set the limit level when it is small. Decrease (decrease noise reduce amount).

The output of the control signal generator 72 controls the noise reduce amount in accordance with the movement of the video signal. On the other hand, the output of the control signal generator 110 is
The noise reduction amount is controlled according to the S / N ratio of the video signal. In order to reduce the adverse effect of noise reduction as much as possible, the selector 108 selects one with a smaller noise reduction amount.

FIG. 14 shows the integrator 101 (or 1 of FIG. 9).
11 shows an example of the configuration of 11). In this example,
The output of the subtractor 64 is input to the absolute value circuit 131, and the absolute value is calculated. That is, the absolute value circuit 131 has an input / output characteristic as shown in FIG. 15, for example. The output of the absolute value circuit 131 is input to the adder 132 and added to the output of the delay circuit 135. Then, the output of the adder 132 is input to the limiter 133, for example, as shown in FIG.
It is limited to a predetermined level according to the characteristics shown in. The output of the limiter 133 is supplied to the reset circuit 134. The output of the reset circuit 134 is delayed by one clock by the delay circuit 135 and supplied to the adder 132.

That is, when the synchronizing signal becomes logic H, the absolute value circuit 131 is enabled, and its output is reset circuit 13 via adder 132 and limiter 133.
4 is supplied. When the reset pulse 1 is not input, the reset circuit 134 outputs the input from the limiter 133 as it is. The data output from the reset circuit 134 is delayed by one clock by the delay circuit 135 and output to the adder 132. The adder 132 adds the data synchronized with the next clock supplied from the absolute value circuit 131 and the data supplied from the delay circuit 135.

By repeating the above operation, the data in the section where the synchronization signal is logic H is cumulatively added. Then, this data is output as the output of the integrator 101 to the hold circuit 102 in the subsequent stage. When the reset pulse 1 is input, the reset circuit 134 resets the data from the limiter 133 to 0 and outputs it.

FIG. 17 shows the integrator 106 (or 1) of FIG.
16) shows an example configuration. In this example,
The data output from the subtractor 105 is the hold circuit 14
1 is supplied to the adder 142, and the hold circuit 14
The output of 5 is added. The output of the adder 142 is supplied to the reset circuit 144 via the limiter 143. Then, the reset circuit 144
Is supplied to the hold circuit 145.

The hold circuit 141 holds the data from the subtractor 105 each time the hold pulse 1 is input 1H1 times. The data held in the hold circuit 141 is input to the hold circuit 145 via the adder 142, the limiter 143, and the reset circuit 144. The reset pulse 1 is also input to the hold circuit 145, and the hold circuit 145 holds the input data every time the hold pulse 1 is input. The data held by the hold circuit 145 is supplied to the adder 142 and added with the data from the hold circuit 141. By repeating the above operation, the data for one field is cumulatively added (integrated). The reset circuit 144 is
When the reset pulse 2 is input for each field, the input data is reset to 0 and output, and the reset pulse 2
When is not input, the input data is output as it is.

FIG. 18 shows the input / output characteristics of the limiter 143. As shown in the figure, the limiter 143 outputs the data corresponding to the input data as it is until the data from the adder 142 reaches a predetermined positive value from 0, but the value becomes equal to or more than the predetermined value. At that time, a constant value is output. When the input is negative, it outputs a substantially constant value.

FIG. 19 shows a third embodiment. In this embodiment, the output of the subtractor 105 of the A channel in the embodiment of FIG. 9 is supplied to the control signal generator 151, and the output of the memory 104 is supplied to the control signal generator 152. Then, the control signal generators 151 and 152
One of the outputs of the above is selected by the selector 153 and supplied to the limiter 66.

Similarly for the B channel, the subtracter 1
The output of 15 is supplied to the control signal generator 161, and the output of the memory 114 is supplied to the control signal generator 162. Then, the selector 163 controls the control signal generator 16
One of the outputs 1 or 162 is selected and the limiter 86
It is designed to be supplied to.

The delay times of the circuit 154 composed of the A channel integrator 101 to the control signal generator 152 and the circuit 164 composed of the B channel integrator 111 to the control signal generator 162 are shown in FIG. As in the case of the ninth embodiment, the delay circuits 61, 65, 81, 8
Similar to 5, the number of clocks is n. Other configurations are similar to those in FIG.

In this embodiment, the integrator 106 and the hold circuit 107 in the embodiment of FIG. 9 are omitted. Therefore, the control signal generator 151 generates a control signal corresponding to the noise component corresponding to the luminance signal component output by the subtractor 105 every 1H. Similarly, the control signal generator 152 outputs the control signal corresponding to the noise component corresponding to the ramp signal output from the memory 104. The selector 153 selects the smaller one of the signals output by the control signal generators 151 and 152 and outputs it to the limiter 66. That is, in this embodiment, the noise reduction amount is controlled for each line according to the movement of the video signal or the S / N amount.

Since the same processing is performed in the B channel circuit, the noise reduce amount is controlled independently for each channel in this embodiment.

[0057]

As described above, according to the noise reducer of the present invention, the noise component corresponding to the predetermined signal and the noise component corresponding to the luminance signal are compared, and the noise reduce amount is controlled according to the comparison result. Since this is done, it is possible to accurately adjust the noise reduction amount with a simple configuration in accordance with the movement of the image. As a result, a low cost device can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a recording system of a high-definition analog video tape recorder to which a noise reducer of the present invention is applied.

FIG. 2 is a block diagram showing a configuration of a reproduction system of a high-definition analog video tape recorder to which the noise reducer of the present invention is applied.

FIG. 3 is a perspective view of the rotary magnetic heads Ha to Hd of FIGS. 1 and 2.
It is a figure explaining the arrangement state of.

4 is a diagram illustrating a pattern of tracks formed by the video tape recorder of FIG.

5 is a diagram illustrating a signal pattern recorded in the track pattern shown in FIG.

FIG. 6 is a block diagram showing the configuration of an embodiment of the noise reducer of the present invention.

FIG. 7 is a waveform diagram illustrating a ramp signal.

FIG. 8 is a diagram illustrating characteristics of limiters 66 and 86 in FIG.

FIG. 9 is a block diagram showing a configuration of a second embodiment of the noise reducer of the present invention.

10 is a timing chart illustrating the operation of the noise reducer 46 of FIG.

11 is a timing chart explaining the operation of the noise reducer 47 of FIG.

12 is a diagram illustrating characteristics of the control signal generator 72 of FIG.

13 is a diagram illustrating characteristics of the control signal generator 110 of FIG.

14 is a block diagram showing a configuration example of an integrator 101 in FIG.

15 is a diagram illustrating input / output characteristics of the absolute value circuit 131 of FIG.

16 is a diagram illustrating input / output characteristics of the limiter 133 of FIG.

17 is a block diagram showing a configuration example of an integrator 106 in FIG.

18 is a diagram illustrating input / output characteristics of the limiter 143 of FIG.

FIG. 19 is a block diagram showing the configuration of a third embodiment of the noise reducer of the present invention.

[Explanation of symbols]

 46, 47 Noise reducer 61 Delay circuit 63 Memory 64 Subtractor 65 Delay circuit 66 Limiter 67, 68 Integrator 69 Data correction circuit 70 Comparator 72 Control signal generator

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H04N 9/87 Z 7916-5C

Claims (3)

[Claims] 1. A difference detecting means for detecting a difference between video signals of preceding and following one field or one frame, a combining means for combining the difference detected by the difference detecting means with the video signal, and a difference detecting means. Of the detected differences, a comparing unit that compares a component corresponding to a predetermined reference signal with a component corresponding to a luminance signal, and a control unit that controls the synthesizing unit in accordance with the comparison result of the comparing unit. A noise reducer comprising: 2. The difference detecting means and the synthesizing means are provided for at least two channels, and the control means controls the synthesizing means of both channels in accordance with a comparison result of at least one channel. The noise reducer according to claim 1, wherein the noise reducer is a noise reducer. 3. The noise reducer according to claim 2, wherein the control means controls the synthesizing means of both channels in accordance with a comparison result of both channels.