JPS61174886A - Time base correcting device - Google Patents

Abstract

PURPOSE:To prevent the occurrence of the phase change at the writing clock to correct the time base by prohibiting the phase lock of the writing clock due to a horizontal synchronizing signal during the equalizing pulse period when an omission occurs at the equalizing pulse. CONSTITUTION:Since a vertical gate signal is inputted into the set input of a DEF to constitute a discriminating circuit 45, an output D of the discriminating circuit 45 is changed to ''0'' or ''1'' only during the vertical synchronizing period in accordance with the condition of a data input (H rate signal (h)) and a clock input (reference H rate signal h0). At the time of excepting the vertical synchronizing period, having no relation to the condition of an data input and a clock input, ''1'' is always outputted, a gate circuit 48 is controlled and functions as a prohibiting gate for an H rate signal (h). During the time except the vertical synchronizing period, a vertical synchronizing period gate signal VG is ''0'', and therefore, a D output of the discriminating circuit 45 is ''1'', and as the result, an H rate signal H' is outputted from the gate circuit 48. Thus, an AFC circuit 42 generates a writing clock ck in which the phase is locked to a horizontal shynchronizing signal H, and the time base correcting action is correctly executed.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a time axis correction device using a digital memory, and particularly to a clock signal for writing a video signal necessary for time axis correction using such a digital memory. Regarding the generation method.

[Prior art and its problems]

Video signals reproduced from devices such as VTRs (video tape recorders) that record and reproduce signals through relative interlocking between a recording medium and a recording head are generally accompanied by fluctuations in the time axis. In recent years, time axis correction devices have come to be used not only for broadcasting purposes, but also for consumer VTRs. A clock signal that is phase-locked to the synchronization signal of the video signal is created, the reproduced video signal is digitized using this clock signal, and sequentially written to the memory, and in parallel with this, the clock signal that is phase-locked to the reference synchronization signal is used to sequentially output data from the memory. A so-called digital time axis correction device is now commonly used, which converts the read signal into an analog signal to obtain a time axis corrected video signal. A general configuration is shown in FIG.

In this figure 2, 1 is an A/D (analog-digital converter), 2 is a memory, 3 is a D/A (digital-to-analog converter), 4 is a write clock generator, 5 is a memory address controller, and 6 is a memory address controller. is a continuous clock generator, V4 represents a reproduced video signal, VO represents a time axis corrected video signal, and S represents a reference synchronization signal.

As the write clock generator 4 in such a time axis correction device, a structure shown in FIG. 3 has conventionally been used. That is, in this Figure 3,
40 is a synchronous separation circuit, 41 is an H rate circuit, and 42 is an AF
After separating the synchronization signal component S from the reproduced video signal V in the synchronization m circuit 40, the E rate circuit 41 extracts a signal h (which is converted into This H rate signal is input to the AFC circuit 42 to generate a write clock ck.
We are trying to generate this.

Here, to explain the reason why the rate circuit 41 is provided, this H rate circuit 41 is made up of, for example, a monostable multivibrator, and its time constant is shorter than one horizontal opening period, and 1/2 horizontal synchronization is used. By setting it to a value longer than the period, for example 43 μs, even when the vertical synchronization signal appears in the synchronization signal component S, the horizontal synchronization signal HK is removed by excluding the influence of the equalization pulse present therein.
This is provided to ensure that the corresponding H rate signal h+ is always obtained without interruption even during the vertical synchronization period.
This makes it possible to obtain a write P hook Ck whose phase is locked to the horizontal synchronizing signal H.

Next, the reason why the write clock CL which is reliably phase-locked to the horizontal synchronizing signal H without interruption during the vertical synchronizing signal period is generated in this manner will be explained with reference to FIG.

This figure 4 shows the memory address controller 5 in figure 2.
Only the write side of is shown together with memory 4, 50 is an address counter, C8 is a write H clear pulse,
is a reproduction vertical synchronization signal, and AD is a write address signal.

In such a time axis correction device, the storage capacity required for the memory 4 is determined by the amount of time axis correction, and if the memory 4 has a storage capacity for 10 horizontal scanning lines, the time axis fluctuation within the range of ±5 lines can be corrected. can be corrected.

Therefore, suppose that the memory 5 has a storage capacity equivalent to M10 horizontal scans, and the write address counter 5
0 is based on the phase of the reproduced vertical synchronization signal V, and from there, a write address signal AD is cyclically generated using the write clock cl (in units of 10 addresses), thereby regenerating the data into the memory 5. Video signal v4tf: @Next, it will be written.

Therefore, write clock cl (vertical synchronization signal V
Even during the period when
If the phase is not synchronized with the horizontal synchronization signal in i, the starting point in the vertical direction for time axis correction will fluctuate, making it impossible to obtain sufficient time axis correction.

This is the reason why the write clock Ck phase-locked to the horizontal synchronization signal is generated without interruption even during the vertical synchronization signal period.

Note that this write clock cl ((the read clock is also the same)
Since the sampling rate of the video signal is determined by this frequency, it is necessary to set it sufficiently higher than the band of the video signal. For example, when the band of the video signal is 4 MHz, the frequency is 1OMHz or more. In addition, in the case of color signals, it is necessary to phase-lock to the burst component, so a circuit called a human PC circuit is used.
This generates a write clock.

By the way, in such conventional time axis correction devices, if an equalization pulse is missing during the period in which the vertical synchronization signal appears in the reproduced video signal, a vertical phase fluctuation occurs in the corrected video signal. There is a problem with this. In other words, in such a time axis correction device, as shown in FIG. 3, the H rate circuit 4 using a monostable multivibrator is
1 is provided, thereby obtaining a rate signal representing the phase of the horizontal synchronization signal even during the period when the equalization pulse is present. As a result, when the synchronization signal component S in which the equalized pulse does not have any omissions is input as shown in FIG. ■It is possible to obtain a rate signal, but when a synchronization signal component S with missing equalization pulses as shown in Figure 5(C) is input, as shown in Figure 5(1), this During the period from when the equalization pulse is lost until the end of the vertical synchronization signal period at that time, the horizontal synchronization position shifts by 1/2H, which causes a shift in the start point of writing to the memory 5 described above, and the video signal changes. This results in phase fluctuations.In addition, (α) and (
C) includes the vertical synchronizing signal of the synchronizing signal, and shows only the portion before and after the vertical synchronizing signal, and time to indicates the position l of the equalization pulse dropout.

Incidentally, such loss of equalization pulses also occurs due to dropouts associated with VTR signal reproduction, but T
/TR has the problem that this problem is particularly likely to occur because the switching position of the head is often set during the vertical blanking period.

For example, in a so-called 2-head helical scan VTR, the tape is wound diagonally around a drum with two heads installed 180 degrees apart, and the tape is run to record and play back the tape. The signal from the head is generally switched during the vertical blanking period and treated as a continuous signal, and at this time, the video signal for one field including vertical synchronization signal information is continuously For those that record and play back as one track,
The switching positions of the two heads are set during the equalization pulse period before the vertical synchronization signal (generally 2 to 3H before the vertical synchronization signal).

However, even in this case, high-end machines for broadcasting etc. have a control function that always makes this switching position coincide with the blanking period between the horizontal synchronization signal and equalization pulse, so this is a particular problem. However, in consumer 2-head helical scan type VTRs that do not have such a control function, the switching position always fluctuates, albeit slightly, and as a result, the switching position is not equalized. When the pulse overlaps with the pulse, the above-mentioned dropout will occur.

Therefore, when the conventional time axis correction device is applied to a two-head helical scan type consumer VTR, sufficient correction cannot be obtained, and a deterioration in image quality is unavoidable. .

[Purpose of the invention]

An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art and to prevent phase fluctuations from occurring in the write clock for time axis correction even if a signal dropout occurs during the equalization pulse period, thereby ensuring sufficient correction. An object of the present invention is to provide a time axis correction device that can be obtained.

[Summary of the invention]

To achieve this objective, the present invention monitors the equalization pulse, and when a dropout occurs in the equalization pulse, prohibits phase locking of the write clock by the horizontal synchronization signal during the period of the equalization pulse. Characterized by points.

[Embodiments of the invention]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The time axis correction device according to the present invention will be described in detail below with reference to illustrated embodiments.

FIG. 1 shows an embodiment of the present invention, in which 43 is a vertical synchronization signal separation circuit, 44 is a vertical synchronization period gate signal generation circuit, 45 is a discrimination circuit, 46 is a counter, 47 is a monostable multivibrator, 48 is a gate circuit, and the other components are the same as those of the conventional example shown in FIG. 3, and the write clock generator shown in FIG. 2 is constructed as a whole.

The vertical synchronization signal 1g separation circuit 43 functions to separate only the vertical synchronization signal component from the synchronization signal component S.

The vertical synchronization period gate signal generation circuit 44 generates a vertical synchronization period gate signal VC that includes a vertical synchronization signal and represents a predetermined period in which an equalization pulse appears (this is referred to as a vertical synchronization period).
It works to generate something.

The counter 46 functions to count down the 6-input clock CL() to make it a signal of L!q, which is the same as the H rate signal.

The monostable multivibrator 47 performs phase shifting and shaping of the output of the counter 45, and functions to generate a reference H rate signal.

FIG. 6 is a diagram showing details of the determination circuit 45 and gate circuit 48. The determination circuit 45 is constructed of a D7 lip with 70 tubes, and the gate circuit 48 is constructed of a Nant gate. In addition,
As described above, the H rate circuit 41 is composed of a monostable multivibrator.

Next, the operation of this embodiment will be explained.

Since the D 71J knob 70 constituting the discrimination circuit M45 has its data input 1111: H rate signal, and the reference H rate signal ho is input to the clock input C, its Q output is the reference H rate signal. .

The result of sampling the H rate signal appears.

Also, since the vertical gate signal VC is input to the set manual S of this discriminating circuit 45, the Q of this discriminating circuit 45 is
The output can change to "0" or "1°" only during the vertical synchronization period depending on the state of data input and clock input C, but outside the vertical synchronization period, the output can change to "0" or "1 degree" depending on the state of data input or clock input C. “1° will always be output regardless of the state.

On the other hand, since the gate circuit 48 is composed of a Nandt gate, while any one of its inputs is fixed at "Oa", its output is fixed at "11".
When the Q output q of the discrimination circuit 45 is "1@", the polarity of the H rate signal is inverted and appears at the output, but when the output q becomes "0°", nothing appears as the H rate signal h°. In the end, it ends up working as a prohibition gate for the H rate signal.

Therefore, we have selected the trivial time and number of pulses of the monostable multivibrator 47 kappa appropriately, and by doing so, the AFC
The phase of the write clock CL appearing at the output of the L path 42 (the reference H rate signal ha thus created) is as shown in FIG. Therefore, it is determined that there will be a good relationship.

Then, since the vertical synchronization period gate signal VG is 0° during periods other than the vertical synchronization period, the D output of the discrimination circuit 45 is 1", and as a result, the gate circuit 48
outputs an H rate signal h″, which causes the AFC
The circuit 42 generates a write clock CL (phase-locked to the horizontal synchronization signal H), so that the time axis correction operation is performed correctly.

Next, if we enter the vertical synchronization period, the vertical synchronization period gate signal VG becomes 10" at this time, so the 0 output of the discrimination circuit 45 is now applied to the clock input O as the reference H rate signal. It changes to "l" or "01" depending on the state of data input at the time.

Now, as shown in Fig. 5 (α), if no equalization pulse is missing in the synchronization signal component S in the reproduced video signal, Fig. 5 (b) As shown, no missing portion appears in the H rate signal, and as a result, the standard H rate signal shown in FIG. The H rate signal is m1w'' at any timing when the signal appears.

Therefore, at this time, the signal q of the Q output of the discrimination circuit 45
As shown in Figure 5 (), the level "l" is maintained during the entire period, and accordingly, the gate circuit 48 also continuously outputs the H rate signal h°, and the AFO circuit 42 A time axis correction operation is performed by generating a write clock Ck whose phase is properly locked.

Next, as shown in FIG. 5C, it is assumed that an equalization pulse is missing in the synchronization signal component S at time 1G after the vertical synchronization period has started.

As a result, as shown in FIG. 5(d), H
After this time to, a phase shift of one equalization pulse appears in the rate signal, so that at time t.

Thereafter, all the levels of the H rate signals become "0" when the reference H rate signal ho is generated, and each time the clock power C of the discrimination circuit 45 becomes h1", the data power becomes "0".
It ends up in a state where it shows 0゛.

Therefore, at this time, the vertical synchronization period gate signal VG is again at the level “to” when the equalization pulse is missing.
1'', the determination circuit 45
The Q output signal q becomes "0" as shown in FIG. The period from time t. to tl is AF Cff;!Circuit 4
With the time constant of 2-, the write clock ck in the phase locked state at time t0 is continuously generated from the AFC circuit 42.

As a result of the above, according to this embodiment, as long as there is no dropout in the equalization pulse, it operates in the same way as the conventional example and generates a write clock in the correct phase lock state, and also when there is no dropout in the equalization pulse. If this occurs, phase locking by the H rate signal is immediately prohibited, and this suppresses the sudden change in the phase of the write clock, resulting in a stable time axis without causing a phase shift in the vertical force direction. Corrections can be made.

〔Effect of the invention〕

As explained above, according to the present invention, even if a dropout occurs in the equalization pulse of the video signal to be corrected in the time axis, there is no risk of causing a sudden phase shift in the write pulse for time axis correction. Therefore, it is possible to eliminate the drawbacks of the prior art and easily provide a time axis correction device that can be applied to consumer VTRs and the like and can sufficiently improve image quality.

Further, according to the present invention, since there is no need to add a control function regarding switching positions to the VTR, the range of applicable VTRs can be expanded, and the cost of the VTR itself can be reduced. .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the write clock generator of the time axis correction device according to the present invention, FIG. 2 is a block diagram showing the general configuration of the time axis correction device, and FIG. 3 is the write clock generator. A block diagram showing a conventional example of a generator, Fig. 4 is a block diagram showing a general configuration of a memory address controller, Fig. 5 is a time chart for explaining operation, and Fig. 6 shows discrimination in the actual example of Fig. 1. It is a detailed explanatory diagram of a circuit. 1...A/D, 2...Memory, 3...
...D/A. 4...Write clock generator, 5...Memory address controller, 6...Read clock generator, 4o...Synchronization minute ti (9) Road, 41...
...H rate circuit, 42...AF'C circuit,
43... Vertical synchronization signal separation circuit, 44...
...Vertical synchronization period gate signal generation circuit, 45...
・Discrimination time M, '46...Counter, 47...
... Monostable Ma Figure 1 Figure 2

Claims (2)

[Claims] (1) Digital time axis in which video signals are written to and read from digital memory using a write clock that is phase-locked to the horizontal synchronization signal in the input video signal and a read clock that is phase-locked to the reference horizontal synchronization signal, respectively. The correction device is provided with a determining means for detecting the omission of the equalization pulse included in the vertical synchronization period of the input video signal, and the period from when the equalization pulse is omitted until the vertical synchronization signal ends is: A time axis correction device characterized in that it is configured to prohibit phase locking by a horizontal synchronization signal with respect to the write clock. (2) In claim 1, the determining means detects a missing equalization pulse by comparing a horizontal synchronizing signal extracted from the input video signal and a horizontal synchronizing signal extracted from the write clock. A time axis correction device comprising: