JP3173128B2 - Time axis fluctuation correction circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time axis generated at a constant period included in an input signal including at least a first synchronization signal and a second synchronization signal for subdividing the first synchronization signal. Regarding the time axis fluctuation correction circuit that corrects the fluctuation,
For example, the present invention relates to an impact error correction circuit that is included in an input video signal and corrects a so-called impact error that occurs when a rotary head enters and leaves a tape.

[0002]

2. Description of the Related Art Generally, in a VTR (Video Tape Recorder), recording and reproduction of a color video signal is performed using a rotary head. Time axis fluctuation (jitter) may occur in the reproduced video signal due to flutter or the like. For this reason, in a conventional VTR, a reproduced video signal is converted to a TBC (Time Base Correlation).
rector (time axis correction device) to remove time axis fluctuation.

FIG. 7 shows an example of the structure of the TBC. In the TBC 10 shown in FIG. 7, the color video signal Sc reproduced by the VTR is supplied to an A / D (analog / digital) converter 2 via a terminal 1 of the TBC 10. The A / D converter 2 is supplied with an alternating signal Sf from an APC circuit 14 described later as a clock. The alternating signal Sf is a signal synchronized with the horizontal synchronizing pulse Ph and the burst signal Sb in the video signal Sc and having a frequency four times the chrominance carrier frequency fc. The A / D is supplied to the converter 2 as a clock.
In the converter 2, the video signal Sc supplied via the terminal 1 is converted into a digital signal Pc at a speed including a time axis fluctuation of the video signal Sc.

[0006] The digital signal Pc is supplied to a memory 3. The alternation signal Sf is also sent to the address generator 15, so that the address generator 15 generates a write address signal Sw for the memory 3 based on the alternation signal Sf. The write address signal Sw is supplied to the memory 3. Thus, in the memory 3, the digital signal Pc is sequentially written for each sample at a speed including the time axis fluctuation of the video signal Sc and at the address indicated by the write address signal Sw.

At this time, the clock generator 1
7, a reference clock signal Sk having a stable frequency 4fc and phase is formed, and this clock signal Sk is supplied to the address generator 18. In the address generator 18, a read address signal Sr for the memory 3 is formed based on the clock signal Sk, and the read address signal Sr is sent to the memory 3. Thus, the digital signal Pc is read from the memory 3 at a constant speed.

Thereafter, the digital signal Pc read from the memory 3 is converted into a digital / analog (D / A) signal.
It is supplied to the converter 4. The clock signal Sk is supplied to the D / A converter 4 as a clock. Therefore, the digital signal Pc supplied to the D / A converter 4 is converted into an analog color video signal Sc. The video signal Sc from which the time axis fluctuation has been removed by the TBC 10 is taken out from the terminal 5.

Here, the alternating signal Sf from the APC 14 is formed specifically as follows.

That is, the video signal Sc via the terminal 1 of the TBC 10 is also sent to a sync separation circuit 11, where the horizontal sync pulse Ph is extracted from the video signal Sc.

The horizontal synchronizing pulse Ph is generated by a PLL (phase
The signal is sent to the terminal 27 of the locked loop 20. This terminal 2
The horizontal synchronizing pulse Ph via 7 is sent to a phase comparison circuit 21 as a jitter detector. This phase comparison circuit 21 is connected to the subsequent circuits 22, 23, 24, and 25 together with P
The LL (phase locked loop) 20 is formed. In this PLL 20, VOC (voltage contr
An oscillating signal So having a free-running frequency Nfc (4fc) is extracted from an olled oscillator (voltage-controlled oscillator) 24, and the oscillating signal So is sent to a 1 / N frequency dividing (quarter frequency dividing) circuit 25, where it is horizontally Divided into frequency signals. The frequency-divided signal is sent to the phase comparison circuit 21, where the phase comparison circuit 21 compares the phase with the horizontal synchronizing pulse Ph. The comparison output signal Sp is supplied to the low-pass filter 22 to remove unnecessary components. You. The output from the low-pass filter 22 is sent as a control signal of the VCO 24 through the addition circuit 23. Therefore, the VCO 24
, An oscillation signal So synchronized with the horizontal synchronization pulse Ph and having a frequency of 4fc is extracted.

The oscillation signal So is sent to the APC circuit 14 via the terminal 28 of the PLL 20. The APC circuit 14 is also supplied with a burst signal Sb extracted from the video signal Sc at the terminal 1 by the burst gate circuit 13. Note that this A
The PC circuit 14 has, for example, V
The horizontal synchronizing pulse P is composed of a phase comparison circuit of the CO output and the oscillation signal So and the burst signal Sb.
h, in synchronization with the burst signal Sb, to form the alternating signal Sf having a frequency of 4fc.

Therefore, in the TBC 10,
The time axis correction of the color video signal Sc as described above is performed by the alternating signal Sf.

By the way, in a VTR, a time axis fluctuation occurs due to the vibration of the tape which occurs when the rotary head hits the tape and when the head separates from the tape. Such a time axis variation is called an impact error. When the impact error occurs, one horizontal scanning time (1H) of the reproduced video signal changes, and, for example, a vertical line appears to be curved on the monitor screen. become. This impact error is a periodic error having a frequency component of several kHz.

That is, when the drum of the rotary head has a structure as shown in FIG.
Play the oblique recording tracks on P by the recording / reproducing head HD R _{/ P,} assuming that display this reproduced video signal to the monitor screen as shown in FIG. 9, the recording / reproducing head HD R _{/ P} and other of the relative positional relationship between each head as the erase head HD _E and DT (dynamic tracking) head HD _DT, appear certain portion of the monitor screen of FIG. 9 become the image curvature C. In the example of FIG. 9, for example, a vertical line appears to be bent.

However, the PLL 2 of the TBC 10
There is a limit to the response speed of 0, and it is possible to correct only a low frequency jitter such as several hundred Hz. However, since the frequency of the above-described impact error is as high as several kHz, the PLL 20 cannot follow the impact error and cannot correct the impact error.

Therefore, an impact error correction circuit 30 for correcting the impact error is added to the PLL 20 of the TBC 10 described above. The impact error correction circuit 30 determines that the impact error has a frame correlation, and that the comparison output signal Sp of the phase comparison circuit 21 indicates that the phase error φmn of the video signal currently being reproduced (the nth horizontal line of the mth frame) Focusing on the phase error φmn of the horizontal synchronization pulse in the line, the impact error component Si is extracted by accumulating the comparison output signal Sp for each one frame period, thereby changing the phase of the oscillation signal So. It is possible to control and correct the impact error.

That is, in the impact error correction circuit 30, the comparison output signal Sp from the phase comparison circuit 21 of the PLL 20 is supplied to the A / D converter 31 via the terminal 35, and the A / D converter 31 Is converted into a digital signal Pp indicating the phase error φmn of the video signal Sc currently being reproduced for each horizontal synchronization pulse Ph. The digital signal Pp is supplied to the accumulating circuit 32, where the operation shown in the equation (1) is performed for each horizontal line.

Σm, n = aΣm-1, n + φmn (1)

However, in this equation (1), Σm,
n is an accumulated value for the n-th horizontal line up to the m-th frame, where a is a constant of 0 <a <1 and, for example, a = 31/32.

In this case, the value Σm, n is written to an address corresponding to the value n in the memory of the accumulation circuit 32,
It is read out as the value Σm-1, n in the next frame period.

From the accumulating circuit 32, a value Σm, n-1 is taken out as an impact error component of the video signal Sc being reproduced at present, and this is taken as the D / A converter 3
4 to be converted into an analog impact error component Si. This impact error component Si is
Is sent to the addition circuit 23 of the PLL 20 via
The signal is supplied as a control signal to the VCO 24 through the addition circuit 23.

As a result, the TBC 10 also corrects the time axis fluctuation due to the impact error.

The accumulation of the impact error component in the accumulation circuit 32 is specifically realized by the configuration shown in FIG. That is, in FIG. 10, a digital signal Pp from the A / D converter 31 is supplied to a terminal 300 of the accumulating circuit 32, and the digital signal Pp is supplied to the memory 302 via the adding circuit 301 line by line. Written. The digital signal Pp for each line read from the memory 302 is supplied to the amplifier 3
After the level is set to a-times (= 31/32) by 04, the level is sent to the adding circuit 301. That is, the accumulation circuit 32 extracts only the impact error component by applying a digital filter to each line of the video signal.

[0023]

As described above, in detecting the impact error component Si, the jitter obtained from the phase comparison circuit (jitter detector) 21 of the PLL 20 of the TBC 10 is accumulated and held for each line. By doing that. That is, in the TBC 10, the impact error component Si detected by the impact error correction circuit 30 is configured for each line by the addition circuit 23 of the PLL 20 for each line so that the impact error is corrected. I have to.

Here, conventionally, as described above, the impact error of a certain line is added to the same line advanced by one frame, so that a delay of one frame is performed. That is, for example, the number of lines during normal reproduction in a system such as the NTSC system (hereinafter referred to as a 525/60 system) is determined to be, for example, 525, and a system such as the PAL system (hereinafter, a 625/50 system) is used. In this case, the number of lines at the time of normal reproduction is determined to be 625 lines. Therefore, the timing of reading the impact error component of each line in the memory 302 in FIG. 10 may have a fixed delay of one frame. . In other words,
As shown in FIG. 11, when 1H (H: horizontal scanning period) of the sample hold is subtracted from 1H of the filter operation, the written data is stored in the memory 302 as the 525/6.
In the case of the 0 system, it is sufficient to read after 523H, and in the case of the 625/50 system, it is necessary to read after 623H.

However, for example, during variable speed reproduction by a DT (dynamic tracking) head, the trace state of the head changes, so that the number of equivalent lines of the reproduced video signal changes. Cannot add the above-mentioned impact error component of the same line with a delay of 525 lines.
In the 50 system, the impact error component of the same line cannot be added with a delay of 625 lines.

That is, for example, as can be seen from FIG. 12 showing the state of head tracing at the time of variable speed reproduction by the DT head, the scanning locus HS _N of the head at the time of normal reproduction and the scanning locus HS ₂ of the head at the time of, for example, × 2 speed reproduction. Comparing with the above, the time at the time of × 2 speed reproduction is longer than that at the time of normal reproduction. In other words, the track pattern is apparently longer at the time of × 2 speed reproduction than at the time of normal reproduction. Therefore, in such a case, the number of lines is equivalently reduced by the amount of missing lines. Also, for example, the scanning locus HS of the head during still reproduction
_{When S} is compared with the scanning locus HS _N of the head during the normal reproduction, the time at the still speed reproduction is shorter than that at the normal reproduction. In other words, the track pattern is apparently shorter during the still reproduction than during the normal reproduction. Therefore, in such a case, the number of lines equivalently increases as much as the signal is insufficient.

Also, for example, in the case of a system capable of compatible reproduction even if the diameter of the drum of the rotary head is different, the trace state of the head changes. For this reason, in the case of compatible reproduction in VTRs having different drum diameters, for the same reason as described above, it is impossible to correct the impact error even in normal reproduction, for example.

That is, in a system capable of compatible reproduction, for example, a tape recorded with a rotary head A having a certain drum diameter can be reproduced by using a rotary head B having a drum diameter larger than the drum diameter of the rotary head A. When the tape recorded by the rotary head A is reproduced by the rotary head B, the relative speed between the tape and the head increases, and the signal reproduced from the rotary head B is apparently time-compressed. Becomes So, in this case,
The number of lines increases by the amount of time compression.
Conversely, in a system capable of compatible reproduction such that the tape recorded by the rotary head B can be reproduced by the rotary head A having a small drum diameter, the tape recorded by the rotary head B is reproduced by the rotary head A. In this case, the relative speed between the tape and the head is reduced, and the signal reproduced from the rotary head A is apparently expanded in time. Therefore, in this case, the number of lines is reduced by the lengthened time.

From the above, the conventional method of writing data in the memory 302 and then reading the data with a delay of a fixed number of lines as described above cannot cope with a state in which the number of lines changes, and ,
Conventionally, the correction of the impact error has to be limited only at the time of normal reproduction, or the impact error cannot be corrected.

Therefore, the present invention has been proposed in view of the above-described circumstances, and has an impact error even when performing variable speed reproduction with a DT head or compatible reproduction with different drum diameters. It is an object of the present invention to provide an impact error correction circuit, that is, a time axis fluctuation correction circuit, which can correct the above.

[0031]

SUMMARY OF THE INVENTION A time axis fluctuation correction circuit according to the present invention has been proposed to achieve the above-mentioned object, and at least a first synchronization signal and a first synchronization signal are subdivided. A time axis fluctuation correction circuit for correcting a time axis fluctuation occurring at a fixed period included in an input signal including a second synchronization signal to be converted, wherein the time axis fluctuation is corrected in units of the second synchronization signal of the input signal. A memory for accumulating the fluctuation component, an address generating means for counting in units of the second synchronization signal and generating an address of the memory based on the count value, and a timing in accordance with the first synchronization signal Means for associating an address of the memory generated by the address generating means with a unit number corresponding to an order of the second synchronization signal between the first synchronization signals, Only the generated time-axis fluctuation component is accumulated in the memory, and a unit number corresponding to the order of the second synchronization signal between the first synchronization signals is stored in the first synchronization signal. Detecting means for detecting a timing coincident with a predetermined unit number determined in advance based on a signal; and timing of the predetermined unit number determined in advance by the detecting means based on the first synchronization signal If it is earlier than this, after the output of the address from the address generation means to the memory is stopped at the timing detected by the detection means, the output from the address generation means to the memory at the timing of the first synchronization signal is stopped. The address output is restarted, and the timing detected by the detection means is a timing of a predetermined unit number determined in advance based on the first synchronization signal. When the later than are those having a control unit for presetting the address to the memory from the address generating means at a timing of the first synchronization signal to the address corresponding to the predetermined unit number.

[0032]

Further, the time axis fluctuation correction circuit of the present invention
Based on at least the first synchronization signal and the second synchronization signal of the input signal, the address of the memory from the address generating means is determined according to the order of the second synchronization signal between the first synchronization signals. It is also possible to have address control means for performing control to correspond to the unit number.

That is, the time axis fluctuation correction circuit according to the present invention is an impact error correction circuit that corrects an impact error occurring at regular intervals included in an input video signal including at least a vertical synchronizing signal and a horizontal synchronizing signal. A memory for accumulating a jitter component for each horizontal line of the input video signal; and address generating means for counting each horizontal line and generating an address of the memory based on the count value. By controlling the address of the memory from the address generating means to correspond to the line number of the horizontal line based on the synchronization signal, only the impact error component generated in the fixed cycle is accumulated in the memory. Things.

Further, this impact error correction circuit
Detecting means for detecting a timing at which a line number of a horizontal line of the input video signal becomes a predetermined line number determined in advance based on the vertical synchronization signal by counting addresses from the address generating means; When the timing detected by the means is earlier than the timing of the predetermined line number predetermined based on the vertical synchronization signal, the counting by the address generation means is stopped at the timing detected by the detection means, and then the vertical The counting by the address generation means is restarted at the timing of the synchronization signal, and when the timing detected by the detection means is later than the timing of the predetermined line number predetermined based on the vertical synchronization signal, the vertical synchronization is performed. At the timing of the signal, the address of the address generating means is changed to the predetermined line. Control means for presetting to an address corresponding to a number, so that an address of the memory from the address generating means is made to correspond to a line number of the horizontal line based on the vertical synchronization signal. .

Further, the impact error correction circuit makes the address of the memory from the address generating means correspond to the line number of the horizontal line based on at least the vertical synchronization signal and the horizontal synchronization signal of the input video signal. It is also possible to have address control means for performing control.

In other words, the above-described impact error correction circuit controls the address of the memory holding the impact error in units of vertical synchronization, thereby correcting the impact error that has conventionally been operated only with the normal reproduced image, for example, at twice the speed. Phase locked DT like 3x speed
In addition to being possible at the time of reproduction, it is also possible to correct an impact error at the time of compatible reproduction by a model having a different drum diameter.

[0038]

According to the present invention, since the second synchronization signal is obtained by subdividing the first synchronization signal, the number of the second synchronization signals between the first synchronization signals is fixed. Should be. Also, if the time-axis fluctuation components of each second synchronization signal unit between the first synchronization signals are accumulated and stored in correspondence with each address of the memory, only the time-axis fluctuation components that occur at a fixed period are obtained. A large value is accumulated in the memory. Therefore, even if the number of the second synchronization signals between the first synchronization signals increases or decreases, the address to the memory is determined based on the timing of the first synchronization signals. By combining with a unit number corresponding to the order, it becomes possible to extract only a time-axis fluctuation component generated at a constant cycle.

[0039]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of one embodiment of the time axis fluctuation correction circuit of the present invention. In the present embodiment, an impact error correction circuit applied to, for example, the above-described TBC is described as an example of the time axis fluctuation correction circuit. In the present embodiment, for example, the number of lines is 525 (525/60 system) as in the above-described NTSC system, and the number of lines is 625 (625/50 system) as in the PAL system. It can respond.

The impact error correction circuit of the present embodiment
As shown in FIG. 1, a time axis fluctuation occurring at a constant period included in an input video signal including at least a vertical synchronization signal as a first synchronization signal and a horizontal synchronization signal as a second synchronization signal (for example, as described above) And a memory 60 for accumulating jitter as a time axis fluctuation component of the input video signal in units of horizontal lines.
And an address counter 50 which is an address generating means for counting the number of each horizontal line and generating an address of the memory 60 based on the count value. The address counter 50 is provided based on a timing corresponding to the vertical synchronization signal. By controlling the address from the counter 50 to the memory 60 so as to correspond to the line number of the horizontal line (the line number corresponding to the order of the horizontal synchronization signal between the vertical synchronization signals), only the impact error component is reduced. The data is accumulated in the memory 60.

In FIG. 1, for example, a digital signal Pp via the adder circuit 301 shown in FIG. 10 is supplied as a write signal to a terminal 42, and a digital signal Pp read from the memory 60 is supplied from a terminal 43. Is output. That is, the memory 60 of the present embodiment corresponds to the memory 302 of FIG. 10 described above, and therefore, although not shown, the memory 60 of the present embodiment has A circuit, an amplifier, and the like are connected, and these constitute an accumulative operation circuit for an impact error component.

The memory 60 for detecting and holding the impact error component has a capacity of, for example, one frame, and is currently reproducing the jitter (error component) of each horizontal line, that is, the horizontal synchronization pulse Ph. The digital signal Pp indicating the phase error φmn of the video signal Sc is held.

Here, in this embodiment, focusing on the fact that even if the number of horizontal lines increases or decreases, the necessary horizontal lines are from the vertical synchronizing signal of the video signal to a certain number of lines.
The address of the memory 60 is controlled according to the vertical synchronization signal. That is, in this embodiment, the write and read addresses of the memory 60 are controlled at the timing of the vertical synchronization signal for each field, focusing on the vertical synchronization signal at the head of the diagonal recording track on the tape. ing. Specifically, one frame is divided into two fields (for example, an odd field and an even field), and the number of horizontal lines is, for example, 263 lines (odd field) and 262 lines (even field) in a 525/60 system.
For example, in a 625/50 system, the address of the memory 60 is controlled by 313 lines (odd field) and 312 lines (even field).

In this embodiment, the control of the address of the memory 60 according to the timing of the vertical synchronizing signal is realized by the following configuration.

Returning to FIG. 1, a terminal 41 is supplied with a horizontal timing signal TH formed in accordance with the timing of the horizontal synchronizing signal, and a terminal 44 is supplied with a vertical timing signal formed in accordance with the timing of the vertical synchronizing signal. Timing signal TV
However, the terminal 45 is supplied with an O / E signal indicating an odd field and an even field.

Here, the address counter 50 receives the horizontal timing signal T supplied through the terminal 1.
By counting H, an address of the memory 60 is formed and sent to the memory 60. The address from the address count 50 is also sent to the control unit 70.

The control unit 70 is connected to the vertical timing signal TV supplied through the terminal 44 and the terminal 44.
The address counter 50 is controlled so that an address to the memory 60 is made to correspond to a line number of the horizontal line based on the O / E signal supplied through the O / E signal.

That is, the control unit 70 counts the address from the address counter 50, so that the line number of the horizontal line becomes a predetermined line number n determined in advance based on the vertical synchronization signal. And the detected timing is a predetermined line number n determined in advance based on the vertical synchronization signal.
When the timing is earlier than the original timing, the counting operation of the address counter 50 is stopped (disabled) at the detected timing, and then the counting operation of the address counter 50 is restarted at the timing of the vertical synchronization signal. (Enable) When the detected timing is later than the original timing of the predetermined line number n determined in advance based on the vertical synchronization signal, the address of the address counter 50 is changed at the timing of the vertical synchronization signal. This is to preset to an address corresponding to a predetermined line number n.

More specifically, the control section 70 of FIG. 1 has a configuration as shown in FIG. In FIG. 2, the same components as those in FIG. 1 are denoted by the same reference numerals.

In FIG. 2, the control unit 70 of the impact error correction circuit of this embodiment includes a detection block 71
And a determination control block 72.

The detection block 71 counts the address from the address counter 50 so that the line number of the horizontal line of the input video signal becomes a predetermined line number determined in advance based on the vertical synchronization signal. Is to be detected. Specifically, for example, in the case of the 525/60 system, when the O / E signal supplied via the terminal 45 indicates an odd field, the count value of the address from the address counter 50 is, for example, a value. When the O / E signal indicates an even field, the timing at which the count value of the address from the address counter 50 becomes 262 is detected. In other words, when the O / E signal indicates an odd field, a predetermined line number determined in advance based on the vertical synchronization signal is, for example, a line number 263, and the address from the address counter 50 is the line number 263. Detect when it becomes
When the O / E signal indicates an even field, the predetermined line number is set to, for example, the line number 525, and the timing at which the address from the address counter 50 indicates the line number 525 is detected. Further, for example, in the case of the 625/50 system, when the O / E signal indicates an odd field, the timing at which the address count value from the address counter 50 becomes, for example, the value 313 is detected, and the O / E When the signal indicates an even field, the count value of the address from the address counter 50 is 6
25 is to be detected. In other words, when the O / E signal indicates an odd field, the predetermined line number is set to, for example, the line number 313, and the timing at which the address indicates the line number 313 is detected. When an even field is indicated, the predetermined line number is set to, for example, the line number 625, and the timing at which the address indicates the line number 625 is detected.

The output of the detection block 71 is sent to the judgment control block 72. This judgment control block 7
Reference numeral 2 denotes enabling / disabling and presetting of the address counter 50 based on the timing detected by the detection block 71. Specifically, for example, in the case of the 525/60 system, the determination control block 72
The timing detected at 1 is earlier than the original timing of a predetermined line number (for example, the line number 263 for the odd field and the line number 525 for the even field) determined based on the vertical synchronization signal. In some cases, the counting operation by the address counter 50 is disabled at the timing detected by the detection block 71, and then the counting by the address counter 50 is enabled at the timing of the vertical synchronization signal.
That is, in the case of an odd field, the determination control block 72 disables the address counter 50 when the address from the address counter 50 becomes an address corresponding to the line number 263, and then disables the address counter 50 with the vertical timing signal TV. The address counter 50 is enabled and counting is restarted to output from the address corresponding to the line number 264. In the case of an even field,
Disable when the address becomes the address corresponding to the line number 525, and then disable the vertical timing signal TV.
And output from the address corresponding to the line number 1.

Further, in the case of the 525/60 system, the determination control block 72 determines a predetermined line number (for example, the odd field number) whose timing detected by the detection block 71 is predetermined based on the vertical synchronization signal. In the case of the above, the address of the address counter 50 is changed to the predetermined line number (263/525) at the timing of the vertical synchronizing signal when the line number is 263 after the original timing of the line number 525 in the case of the even field. Preset to the address corresponding to. That is, the determination control block 72
Is the vertical timing signal T
V, the address counter 50 is preset to output an address corresponding to the line number 264 from the address counter 50. In the case of an even field, the address counter 50 is changed to the line number 1 by the preset corresponding to the vertical timing signal TV. Output the corresponding address.

The predetermined line number determined based on the vertical synchronizing signal in the determination control block 72 in the case of the 625/50 system is, for example, a line number 313 at the time of the odd field, and a line number 313 at the time of the odd field. Sometimes the line number is 625, and other operations are the same as in the 525/60 system.

As described above, the impact error correction circuit of FIG. 2 (FIG. 1) causes the address of the memory 60 from the address counter 50 to correspond to the line number of the horizontal line based on the vertical synchronization signal. I have to.

As described above, in the impact error correction circuit of this embodiment, for example, as shown in FIG.
In the case where the number of lines is equivalently increased by the period indicated by Li in the drawing as compared with the normal playback such as the still playback of the variable speed playback by the head, as shown in FIGS. Based on the signal TV, a certain horizontal line number (line number n, for example, line number 263 / line number 525 in the case of a 525/60 system, 62
In the case of the 6/50 system, when counting up to the line number 313 / line number 625), the counting of the address counter 50 of the memory 60 is stopped (disabled).
When the vertical synchronizing signal comes again, it is enabled at that timing and the counting is restarted (for example, in the case of a 525/60 system, the line number 264 / line number 1, 62
In the case of the 6/50 system, if line number 313 / line number 1) is used, one frame is always used as 525 or 625 lines as the memory 60, and the concept is completely the same as that in normal reproduction. Will be. Conversely, when the number of lines decreases, as shown in FIG. 4 and FIG. 5, before the address counter 50 is stopped, the vertical timing signal TV is used to perform presetting. 6
Although the number of lines used is smaller than 25, the writing / reading of the error component of a specific line can be considered in exactly the same manner as in normal reproduction.

Further, the above-mentioned impact error correction circuit comprises:
As shown in the other embodiment of FIG. 6, unlike the configurations of FIGS. 1 and 2 described above, a configuration for controlling the address counter 50 (control unit 70 of FIGS. 1 and 2) is provided independently. It is also possible.

That is, as shown in FIG. 6, the impact error correction circuit converts at least a vertical timing signal TV corresponding to the vertical synchronization signal of the input video signal and a horizontal timing signal TH corresponding to the horizontal synchronization signal. It is also possible to have a decode counter 75 as address control means for controlling the address from the address counter 50 to the memory 60 to the line number of the horizontal line.
The decode counter 75 shown in FIG.
4 and a vertical timing signal TV from terminal 45
The horizontal timing signal TH is supplied from the terminal 46 together with the / E signal. The impact error correction circuit according to the other embodiment of FIG. 6 can effectively extract an impact error component with a simple configuration, particularly when the number of lines is increased as described above.

As described above, according to the impact error correction circuit of each embodiment of the present invention, the phase locked DT head including ± 1 × speed, ± 2 × speed,... Impact error correction at the time of reproduction, that is, as an example, improvement of image quality when a tape recorded by a high-speed shooting VTR is reproduced at double speed and viewed as a normal image, or when performing compatible reproduction between systems with different drum diameters It is possible to correct the impact error at the time of normal reproduction and variable-speed reproduction by the DT head, and to improve the image quality of the reproduced image of the digital VTR.

According to the time axis fluctuation correction circuit of the present invention, it is possible to correct not only the above-described impact error correction but also all the time axis fluctuation components (errors) that occur periodically. Becomes

[0062]

As described above, in the time axis fluctuation correction circuit of the present invention, at least the first synchronization signal and the first synchronization signal
And a memory for accumulating a time axis fluctuation component of a second synchronization signal unit of an input signal including a second synchronization signal for subdividing the synchronization signal between the two, and generating a memory address based on the second synchronization signal. Address generating means for generating an address from the address generating means based on the first synchronization signal.
By associating with a unit number corresponding to the order of the second synchronizing signal between the synchronizing signals, it is possible to accumulate and extract only the time-axis fluctuation component generated in a constant cycle in the memory. The component can be corrected. Also,
Even when the number of lines of a frame changes, such as when performing variable speed reproduction with a DT head or compatible reproduction with different drum diameters, it is possible to correct a time axis fluctuation component that occurs in a constant cycle.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing a basic configuration of an impact error correction circuit according to an embodiment of the present invention.

FIG. 2 is a block circuit diagram showing a more specific configuration of FIG.

FIG. 3 is a diagram for explaining an apparent increase in the number of lines during still reproduction by the DT head and address control by the circuit of the embodiment.

FIG. 4 is a diagram for explaining a relationship between a line number and enable / disable of an address counter and preset when the number of lines increases or decreases.

FIG. 5 is a diagram showing a line number and a timing of a vertical synchronization signal.

FIG. 6 is a block circuit diagram showing a configuration of another embodiment.

FIG. 7 is a block circuit diagram showing a schematic configuration of a TBC.

FIG. 8 is a diagram showing an arrangement of a rotary head.

FIG. 9 is a diagram showing a monitor screen for explaining an impact error.

FIG. 10 is a diagram showing a specific configuration of a cumulative circuit of a conventional impact error correction circuit.

FIG. 11 is a diagram for explaining timing of writing / reading of an impact error component of each line in a memory of a conventional accumulation circuit.

FIG. 12 is a diagram for explaining a head scanning locus and a track pattern during normal reproduction, × 2 speed reproduction, and still reproduction.

[Explanation of symbols]

 50 ··· Address counter 60 ··· Memory 70 ··· Controller 71 ··· Detection block 72 ··· Judgment control block 75 ··· Decode counter

Claims (2)

(57) [Claims] 1. A time axis for correcting a time axis variation occurring at a constant period included in an input signal including at least a first synchronization signal and a second synchronization signal for subdividing the first synchronization signal. A variation correction circuit, a memory for accumulating a time-axis variation component in units of the second synchronization signal of the input signal; address generation means for generating an address of the memory based on the second synchronization signal; On the basis of the first synchronization signal, an address of the memory generated from the address generation means is associated with a unit number corresponding to the order of the second synchronization signal between the first synchronization signals .
Means for responding to the sequence of the second synchronization signal between the first synchronization signals.
Is determined in advance based on the first synchronization signal.
Timing that matches the specified unit number
That detecting means and said timing detected by the detecting means of the first synchronization signal
Timing of a predetermined unit number predetermined based on the number
If it is earlier than the
The address from the address generation means to the memory
After stopping the address output, the timing of the first synchronization signal
Address from the address generation means to the memory.
Output is resumed, and on the other hand, the
Is determined in advance based on the first synchronization signal.
When the timing is after the timing of the specified unit number,
The address generation means is provided at the timing of the first synchronization signal.
The address to the memory from
And a control means for presetting to a corresponding address . 2. The method according to claim 1, wherein an address from said address generating means to said memory is stored between said first synchronizing signal and said second synchronizing signal based on at least said first synchronizing signal and said second synchronizing signal of said input signal. 2. The time axis fluctuation correction circuit according to claim 1, further comprising address control means for performing control to make the unit number correspond to a unit number according to the order of the synchronization signal.