JP2001136493A - Video signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a video signal processor that can activate TBC even in the case of special reproduction as well as regular reproduction. SOLUTION: A reset pulse generated by a pulse generating circuit 5 reset the phase of a synchronizing signal tsync generated by a synchronizing signal generating circuit 9 in specific timing every one field or two. Thus, the phase deviation between an input signal and an output signal can be absorbed so as to activate the TBC even in the special reproduction.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing apparatus having a time axis correction circuit (hereinafter abbreviated as TBC) suitable for use in a video tape recorder (hereinafter abbreviated as VTR).

[0002]

2. Description of the Related Art The prior art will be described by taking reproduction processing of a home VTR of the helical scan system as an example.

[0003] Usually, the TBC writes an input signal to a memory based on a write control signal having substantially the same time axis fluctuation as that of the input signal, and converts the input signal into a read control signal substantially synchronized with the synchronization signal cycle of the standard signal. By reading data from the memory based on the data, a time axis error is corrected. Here, a conventional TBC will be described using an example in which a line memory is used as a memory.

FIG. 2 is a block diagram of a conventional video signal processing device having a TBC. A reproduction video signal (hereinafter, simply referred to as an input signal) input from a terminal 1 is digitally converted by an A / D converter 2, subjected to reproduction signal processing such as clamping by a reproduction signal processing circuit 3, and subjected to a synchronization separation circuit 4. , And the memory 6. The sync separation circuit 4 detects the sync signal of the input signal, and generates a composite sync signal pulse (hereinafter, referred to as csync) substantially synchronized with the sync signal of the input signal. The signal csync is input to the pulse generation circuit 5, where an equivalent pulse is removed, and a horizontal synchronizing signal pulse (hereinafter, referred to as hsync) is generated. hsync
Is input to the write control circuit 7 and generates an address indicating the data storage position in the memory 6 based on the input. This address is reset by using hsync as a trigger.

On the other hand, the synchronization generation circuit 9 counts a predetermined value by a counter, thereby obtaining a standard composite synchronization signal (hereinafter, tsync) substantially synchronized with the synchronization signal of the standard signal.
). tsync is the read control circuit 8
, And an address is generated based on tsync so that data stored in the memory 6 is read at intervals substantially in synchronization with the standard signal. Writing to the memory 6 is controlled by hsync having a time axis fluctuation as a trigger, and read control is performed by a tsync not including the time axis fluctuation as a trigger. Therefore, the video signal output from the memory 6 is output on the time axis. The output is output with the fluctuation corrected. The video signal output from the memory 6 is output to the synchronization adding circuit 10 by the tsync generated by the synchronization generation circuit 9.
Is added to the signal read from the memory, and the D / A converter 1
The signal is converted to analog at 1 and output from the terminal 12. Hereinafter, the signal output from the terminal 12 is simply referred to as an output signal.

In the above-described TBC operation, it is necessary to absorb the difference in the period between the input signal including the time axis error and the output signal having the corrected time axis error by the capacity of the memory 6. Here, when the average period of the input signal does not coincide with the period of the standard signal, the deviation amount is gradually accumulated, cannot be absorbed by the capacity of the memory 6, and the TBC operation fails. Come.

A method for avoiding this problem will be described below. The synchronization generation circuit 9 generates a V correction pulse indicating a vertical synchronization signal part of tsync, outputs the V correction pulse from a terminal 13,
This is a servo unit (not shown) that controls the rotating cylinder.
Communicate to In the servo unit, control is performed so that one field of the reproduction signal is a half cycle of the rotating cylinder.
Further, control is performed using the above-described V correction pulse so that the rotation cycle of the rotary cylinder is adjusted to the V correction pulse.
With this control, the input signal input from the terminal 1 becomes ts
Since the servo control is performed such that ync and the field cycle substantially match, the average cycle thereof matches the cycle of the standard signal. This solves the above problem. Hereinafter, the above V
The rotation control of the rotary cylinder by the correction pulse is simply called servo feedback.

[0008]

FIG. 3 is a diagram showing an example of the trajectory of the head during special reproduction (for example, during fast-forward search or rewind search) in the helical scan system. In the helical scan method, the head (not shown) is attached obliquely with respect to the longitudinal direction of the magnetic tape T, so that the track pattern TP is arranged obliquely. At the time of trick play, the tape feed speed is different from the normal speed, so that the track of the head crosses several tracks differently from the normal play as shown in FFS and REWS. If the tape feed speed is different from the normal, the cycle of one horizontal scanning period (hereinafter, referred to as 1H) (hereinafter, referred to as fH) differs from the normal cycle. If fH deviates from the prescribed period, the television cannot receive a signal and cannot display normal images. Therefore, the rotation of the rotary cylinder is controlled so that fH has a substantially prescribed cycle. This is usually called fH correction.

Although the fH has a substantially regular period due to the fH correction, the period of the field differs from the regular period due to the shift of the rotation of the cylinder. In this state, when the above-described servo feedback of the TBC is applied, FIG.
Since the V correction pulse output from the synchronization generation circuit 9 is different from the period of the vertical synchronization signal required for special reproduction, a servo feedback system cannot be established.

It is one idea to intentionally change the cycle of tsync according to the special playback. However, if the playback speed at the time of the special playback changes, it is necessary to perform various switching in accordance with the cycle. Considering that the tape feed speed is unstable, good performance cannot be obtained in practice. For the above reason, the conventional servo feedback system is disclosed in Japanese Patent No. 284.
As described in Japanese Patent No. 4765, the TBC is turned off during special reproduction.

An object of the present invention is to provide a video signal processing device capable of performing a TBC operation not only during normal reproduction but also during special reproduction.

[0012]

According to the present invention, a first video signal including a time axis error is input and stored as a storage video signal, and the stored video signal is read out to correct a second time axis error. Storage means for outputting as a video signal, a synchronization signal receiving means for receiving the first video signal, separating a synchronization signal from the first video signal, and outputting a first synchronization signal; And a write control unit for receiving a first synchronization signal and generating a write control signal for performing control for writing the first video signal to the storage unit based on the first synchronization signal. A synchronization signal generating means for generating a second synchronization signal having a horizontal synchronization interval substantially equal to the synchronization interval, the resetting means including a resetting means for setting the second synchronization signal to a predetermined phase; By resetting the stage at a specific reset timing every one or two fields, the synchronizing signal generating means for generating the second synchronizing signal and the video signal stored in the storage means are synchronized with the second synchronizing signal. A read control means for generating a read control signal for reading at a timing substantially synchronized with the signal; and adding at least a part of the second synchronization signal to the second video signal read from the storage means. And a synchronizing signal adding means for outputting the video signal as a video signal.

That is, to correct the accumulated amount of the time axis error between the input signal and tsync, the phase of the tsync is reset at a specific timing every one or two fields, and the accumulated amount of the time axis error between the input signal and tsync is corrected. Absorb. Thus, it is possible to operate the TBC even during special reproduction in which the number of lines is different from the specified number.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention. 2 is different from the conventional example of FIG.
The output of the servo feedback signal from the synchronizing signal generation circuit 9 disappears, and the terminal 13 is deleted. In FIG. 1, a head switch pulse (hereinafter abbreviated to HSW) of a rotating cylinder (not shown) is output from the terminal 14 in FIG. , And the point where the reset pulse RSP is output from the pulse generation circuit 5 and is input to the synchronization generation circuit 9.

FIG. 7 shows an example of the configuration of the pulse generation circuit 5 of FIG. Csy shown in FIG.
nc, the equivalent pulse removal circuit 52 removes the equivalent pulse, and the terminal 54
Is output as hsync shown in FIG. Further, the csync is input to a vertical synchronization signal detection circuit 55, where the csync is detected, and a vertical synchronization signal portion of the csync is detected.
A pulse VD which is substantially synchronized with the leading edge of the vertical synchronization signal is output. This VD is input to the delay circuit 56, and after being subjected to a predetermined delay, is output as VD_DL.
9 is input. The HSW illustrated in FIG. 1 input from the terminal 57 is detected as an edge by the edge detection circuit 58, output as HSW_EDG, and input to the selector 59. In the selector 59, VD_DL or HSW
One of the pulses of _EDG is selected and output as a reset pulse RSP.

The reset pulse RSP resets the phase of tsync of the synchronization generation circuit 9 in FIG. 1 at a specific timing every one or two fields, and by matching the phases of the two, the input signal and the position of tsync are synchronized. Absorb the phase difference.

As an example, a reset operation will be described with reference to FIGS. 8A and 8B, taking as an example a case where the synchronization generation circuit 9 is configured using a counter. In a conventional synchronization generating circuit, as shown in FIG. 8A, a counter normally runs by itself in a predetermined cycle (for example, one field) and generates a pulse according to the counter value.
Generate tsync.

On the other hand, in the present invention, the counter is
As shown in (B), it is reset by the reset pulse RSP. By generating the reset pulse RSP in accordance with the cycle of the input signal, the cycle of tsync can be matched with the cycle of the input signal, and the phase difference between the input signal and tsync is absorbed. That is, conventionally, the cycle of the input signal is controlled by the servo feedback based on the cycle of tsync.
In the present invention, conversely, tsync is based on the cycle of the input signal.
Is reset, and control is performed so that the cycle of tsync matches the cycle of the input signal. This allows the TBC to operate without servo feedback.

As described above, the phase of the input signal is tsyn
Since the phase difference is absorbed by following the phase on the c-side, the period of the fields matches even when the number of lines per field of the input signal is different, and the TBC function can be operated normally. However, since the phase shift between the two is absorbed by the reset, there is a problem that a signal discontinuity (skew) occurs at the reset timing.

Next, the timing of the phase reset of tsync will be described. FIG. 4 shows an example of a timing chart of reset pulse generation. In FIG. 4, the time difference between when the input signal is written to the line memory and when it is read is approximately 1H.
It is drawn as. At the reset timing, as described above, discontinuity of the video occurs, so that if performed within the effective video period, the video will be disturbed. tsync
This problem can be solved by performing the phase reset of the operation outside the effective video period. The specific reset position is 3H or more and 10H or more from the leading edge t2 of the vertical synchronization signal portion of the output signal in FIG.
It is desirable to set a range shown by the following range (range between t3 and t4 in the figure). If the timing is earlier than t3, it may be possible to see the image on the TV monitor, and if it is later than t4, the equivalent pulse of the vertical synchronizing signal may be lost, which may hinder the operation of the television. There is.

Next, a method of generating the reset pulse will be described with reference to two examples. FIG. 5 shows an example of a reset pulse generation method. The first generation method will be described with reference to FIG. C output from the sync separation circuit 4 of FIG.
Based on the sync, the position of the vertical synchronization signal is detected inside the pulse generation circuit 5 of FIG. 1, and the pulse VD shown in FIG. 5 is generated at a timing substantially coincident with the leading edge of the vertical synchronization signal. In this method, the reset pulse RSP is generated at the above-mentioned reset timing, delayed from the timing by the time Td1. It is the shortest that the delay time Td1 is set to slightly less than one field, which is a preferable setting for increasing the response of the TBC.

However, in the case of a two-head helical scan system, as shown in an example of a helical scan system in FIG. 6, two opposed heads CH1 and CH1 shown in FIG.
CH2, as shown in FIG.
Since the head and track B are alternately scanned on the magnetic tape T such that the head is track CH2 and the recorded data is read, focusing on one head, 2
The data is read for each field. Here, if the heads of CH1 and CH2 are attached to the rotary cylinder RC shown in FIG. 6A so as to be completely opposed to each other by 180 °, the head switching timing of both heads is performed for each field. Are not exactly opposed due to an error in the mounting position. In this case, setting Td1 to be slightly less than one field is an operation of applying a reset pulse to different heads, which is not preferable. Therefore, in this case, it is desirable that Td1 is set to slightly less than two fields, and VD detection and reset pulse generation are performed on the same head.

The second generation method is a method of detecting both edges of the HSW and generating a reset pulse. FIG.
(B) shows an example of a timing chart. Where HSW
Is a pulse generated by detecting the period of the rotating cylinder by detecting the magnetic field generated from a magnet (not shown) attached to the rotating cylinder RC shown in FIG. is there. As shown in FIG. 5B, the pulse is a two-field, one-period pulse. It is also practical to detect both edges of the HSW and generate a reset pulse at a timing substantially synchronized therewith. In particular, during special playback, noise may be added to the vertical synchronization signal portion of the input signal and csync may not be generated properly by the synchronization separation circuit 4 in FIG. 1, but HSW is independent of the signal and the rotation cycle of the rotating cylinder is Therefore, the method in which the reset pulse is generated based on the HSW can generate the reset pulse more stably.

Incidentally, the interval between the HSW and the leading edge of the vertical synchronizing signal of the input signal is, for example, 6.5H ± 1.5H in NTSC of the VHS standard, and a range of about 3H is allowed. The interval between the HSW and the leading edge of the vertical synchronizing signal of the input signal usually varies depending on the recording state on the tape, and may vary within the above-mentioned standard range. Therefore, during normal playback, H
If the reset pulse is generated by the second generation method of generating the reset pulse from both edges of the SW, the display position of the image may move up and down depending on the recording state, and the timing may be such that it just crosses the line. , The image shakes up and down. Therefore, during normal playback,
It is not preferable to generate a reset pulse by the method of generating the reset pulse. On the other hand, in the first generation method of generating a reset pulse with a delay of Td1 from VD, by adjusting Td1, it is possible to set a timing at which pitching is unlikely to occur. The generation method is preferred.

On the other hand, during special reproduction, the period of one field increases or decreases as described above. Therefore, in the first generation method of generating a reset pulse by delaying Vd by Td1, the period of Td1 is increased or decreased in accordance with this. Otherwise, the timing of the reset pulse may be shifted. Further, as described above, there is also a problem that the lack of the vertical synchronizing signal of the input signal interferes with the pulse generation, and it is not preferable to generate the reset pulse by the first generation method. Therefore, during special playback, HS
Second to generate reset pulse based on both W edges
Is more preferable. On the other hand, at the time of normal reproduction, the use of the first generation method is more preferable because the position of the reset pulse with respect to the phase of the input signal is stabilized.

As described above, if the present invention is applied, the TBC operation can be performed not only during normal reproduction but also during special reproduction. Further, it is needless to say that the system switching in which the TBC is operated by the servo feedback during the normal reproduction as in the conventional system and the TBC is operated by the system of the present invention during the special reproduction is effective.

[0027]

According to the present invention, it is possible to operate the TBC during normal reproduction and special reproduction without servo feedback. In particular, it is possible to operate the TBC even during the special reproduction, and it is possible to improve the image quality.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional example.

FIG. 3 is a diagram showing an example of a trajectory of a head during special reproduction in a helical scan method.

FIG. 4 is a diagram showing an example of a timing chart of reset pulse generation.

FIG. 5 is a diagram showing an example of a reset pulse generation method.

FIG. 6 is a diagram showing an example of a helical scan method.

FIG. 7 is a block diagram illustrating an example of a pulse generation circuit.

FIG. 8 is a diagram illustrating an example of a synchronization generation method.

[Explanation of symbols]

 1, 12 terminal, 2 A / D converter, 3 reproduction signal processing circuit, 4 synchronization separation circuit, 5 pulse generation circuit, 6 memory, 7 write control circuit, 8 read control circuit, 9 ... Synchronization generation circuit, 10 ... Synchronization addition circuit, 11 ... D / A converter, 51,54,57,60 ... Terminal, 52 ... Equivalent pulse removal circuit, 55 ... Vertical synchronization signal detection circuit, 56 ... Delay circuit, 58 ... edge detection circuit, 59 ... selector.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04N 5/93 H04N 5/93 A (72) Inventor Hideo Kadani 1410 Inada, Hitachinaka City, Ibaraki Pref. Hitachi Digital Media Products Division (72) Inventor Hideo Nishijima 1410 Inada, Hitachinaka-city, Ibaraki Pref. Hitachi Digital Media Development Headquarters (72) Inventor Katsuyuki Watanabe 1410 Inada, Hitachinaka-shi, Ibaraki Hitachi, Ltd. In the Digital Media Development Division of the Works (72) Nao Horiuchi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture F-term in the Digital Media Development Division of Hitachi, Ltd. (Reference) AA18 AA37 BA03 BA07 BA09 CA13 CA15 5C053 FA21 HA0 4 HA21 HC02 HC05 HC08 JA27 JA28 KA02 KA08 KA18 KA20 KA25 5D080 AA03 BA03 DA04 FA32 GA16

Claims (7)

[Claims] 1. A storage means for receiving a first video signal including a time axis error, storing the first video signal as a storage video signal, reading the stored video signal, and outputting as a second video signal having a corrected time axis error. A synchronization signal separating unit that receives the first video signal, separates a synchronization signal from the first video signal, and outputs a first synchronization signal; Write control means for generating a write control signal for performing control for writing the first video signal to the storage means based on the first synchronization signal; and a horizontal synchronization interval substantially equal to a horizontal synchronization interval of a standard signal. Synchronizing signal generating means for generating a second synchronizing signal, the resetting means for setting the second synchronizing signal to a predetermined phase, wherein the reset means has one or two feeds. By performing a reset operation at a specific reset timing for each mode, the synchronization signal generating means for generating the second synchronization signal, and the video signal stored in the storage means are substantially synchronized with the second synchronization signal. Read control means for generating a read control signal for reading at a timing; and adding at least a part of the second synchronizing signal to the second video signal read from the storage means, as a third video signal. A video signal processing device comprising: a synchronization signal adding means for outputting. 2. The video signal processing device according to claim 1, wherein said reset timing is controlled based on a vertical synchronization signal timing in said first synchronization signal. 3. The reset timing according to claim 2, wherein the reset timing is set at a position delayed by 1.9 fields or more and 2 fields or less from the vertical synchronization signal leading edge timing of the first synchronization signal. A video signal processing device. 4. The apparatus according to claim 1, further comprising a rotary cylinder to which at least one pair of reproducing heads disposed at substantially opposite positions is mounted, wherein the number of lines in one field is reproduced with a number different from the standard signal. In a special playback mode (slow playback, still playback, etc.), a playback video signal restored from the output of the playback head is input to the storage unit as the first video signal. apparatus. 5. The video signal according to claim 4, wherein in the special reproduction mode, the reset timing is controlled based on a head switch pulse generated in synchronization with a rotation phase of the rotary cylinder. Processing equipment. 6. The system according to claim 1, wherein the reset timing is set to 3H or more with respect to a vertical synchronization signal leading edge timing of the third video signal.
A video signal processing apparatus, wherein the video signal is generated in a range of timing earlier than 0H (H is a horizontal scanning cycle). 7. The video signal processing apparatus according to claim 1, wherein said storage means is constituted by a line memory.