JPH0527310B2 - - Google Patents

Description

[Detailed description of the invention]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time axis correction device used for correcting time axis fluctuations associated with recording and reproducing video signals. Conventional configuration and its problems Video tape recorder (hereinafter referred to as VTR)
The playback signal is subject to time axis fluctuations due to tape vibration, tape elongation, uneven rotation of the video head, and geometric distortion of the head assembly.A device that removes this time axis fluctuation is called a time axis correction device. It is generally abbreviated as TBC, which stands for Time Base Collector. Figure 1 shows the general configuration of a conventional TBC. The horizontal synchronization signal (hereinafter referred to as
A clock generator 2 generates a clock whose phase is locked to the PBH (referred to as PBH). A write address generator 3 generates a memory address in one-to-one correspondence with the horizontal position of the video signal using this PBH and the clock, and the A/D converter 4 writes the A/D converted video signal into the memory 5. On the reading side, a clock whose phase is locked to the reference synchronization signal is generated by the clock generator 6, and the read address corresponding to the horizontal synchronization signal of the reference synchronization signal is read out using this clock and the reference synchronization signal (hereinafter referred to as reference HD). The image signal is generated by the address generator 7, read out from the memory 5, and subjected to D/A conversion by the D/A converter 8, thereby obtaining a time-axis corrected video signal. However, this type of TBC requires a more complex circuit to generate a stable write clock than PBH, which has a fluctuating time axis, and a phase lock loop (hereinafter referred to as PLL) circuit is generally used. . By the way, in general, helical scan
In a VTR, the video signal for one field is recorded on one or more tracks, and there is a point at which the signal played from one track is switched to the signal played from the next track (hereinafter referred to as the head switching point). It has been well known that the reproduced video signal becomes temporally discontinuous in the case of a video signal (referred to as "skew"). Traditional
Various formats such as VHS, Beta and C formats
Skew occurs in VTRs as well, so the switching point is set at the beginning of vertical blanking to prevent skew from appearing on the screen. Therefore, TBCs for VTRs such as VHS, Beta, and C formats only need to respond within the vertical retrace period, and TBCs were used as shown in FIG. On the other hand, in order to make VTRs smaller and wider, it is possible to reduce the cylinder diameter and increase the rotation speed, and B format (SMPTE type B1
Segment type VTRs such as inch VTRs can be considered. However, in segment-based VCRs, skew appears on the screen, so a TBC with fast response speed is required. In conventional segment type VTRs, the difference between the VTR playback signal and the reference signal is detected using HSYNC,
There is also an analog TBC that instantly switches the delay time of the video signal delay line, but there are limitations on wideband and correction range, and the circuit is complicated. On the other hand, as shown in FIG. 2, there is a digital TBC that does not have a feedback loop and is called a feedback type TBC. The A/D converter 4 A/D converts the VTR playback signal,
PBH is detected and created in the tape H creator 9,
Writing to the memory 5 is performed at this PBH timing. Here, it is assumed that the clock of the A/D converter 4 is phase-locked with the reference HD. Therefore, time axis fluctuations are corrected within one clock at the time the data is written to the memory. Next, based on memory 5
By applying a clock phase-modulated by a clock phase modulator 12 to a digital signal read out at the same timing as the HD in a clock phase modulator 12 according to the phase difference between the PBH detected by a phase detector 10 and the clock, to the D/A converter 8. , corrects time axis fluctuations of one clock or less. The memory control 11 controls writing and reading. We are currently reproducing the n-th line video signal, and if a certain position from the PBH is A, the video signal at a certain position from this PBH is A ₊₁ for the n+1 line, and A +1 for the n+2 line E.
A ₊₂ is written to a fixed location on the memory as shown in FIG. Therefore, if the PBH is lost due to skew or dropout, it becomes difficult to write the reproduced signal into the memory 5. Furthermore, in order to increase the recording density, the recording wave on the tape is generally shortened, which tends to increase dropout, and as mentioned above, it is expensive to write to memory only from PBH or PBH and one burst. TBC for density recording VTR
It is unstable. OBJECTS OF THE INVENTION It is an object of the present invention to provide a time base correction device with a fast response speed that can be sufficiently used in segment type VTRs. Configuration of the Invention The present invention provides an A/D for quantizing a reproduced signal.
a converting means, a main memory means for storing the quantized reproduction signal, a D/A converting means for converting the quantized signal read from the main memory means into an analog signal, and controlling reading and writing to the main memory means. A memory control means, an H error detection means for detecting the phase difference between the reproduced signal and the reference signal, and an H error detection means for detecting the previous and subsequent positions by referring to the dropout signal and the head switch signal when HSYNC is lost due to dropout or skew. H error correction means that calculates or complements from the phase difference;
and address storage means for storing an output signal of the error correction means, the memory control means writes to the memory using an absolute address, and reads from the memory according to the phase error amount of the H error detection means. This is a time axis correction device configured to perform correction using relative addresses corrected by . Description of Examples Examples of the present invention will be described below. FIG. 6 is a block diagram of a time axis correction device according to an embodiment of the present invention, and in order to simplify the explanation, the parts excluding processes such as dropout and missing HSYNC will be explained first in the block diagram in FIG. 4. , FIG. 5 is a memory configuration diagram. The VTR playback signal that has been A/D converted by the A/D converter 4 is processed by a reference HD and a clock (hereinafter simply referred to as a clock) that is phase-synchronized with this HD.
It is written into main memory 5. On the other hand, PBH and standards
The phase error amount with respect to the HD is detected by the H error detector 13 and written into the address memory 14. Therefore, let n be the horizontal scanning line of the reproduced signal, and use the reference
If the sampling point of the reproduced signal based on HD is X, the reference point A of the reproduced signal based on PBH is written in the main memory 5 as shown in FIG. The address of the point is written. Next, on the reading side, reading is performed so that the address point (X ₂ ) written in the address memory 14 matches the phase of the reference HD. In other words, memory control 1
In 1, writing is done using an absolute address,
Reading is performed using a relative address according to the difference between the PBH and the reference HD. Therefore, the configuration is such that the difference between the PBH and the reference HD only needs to be determined before reading out that line. Further, the main memory 5 is configured to have an address with a margin corresponding to the amount of phase error rather than one horizontal period. Note that one horizontal period here and 1H in FIG. 5 are sufficient as an effective scanning period excluding the blanking period. Note that in this embodiment, the H error is detected by A/D.
Although the PBH is detected after the converter 4, the PBH may be created before the A/D converter 4. In addition, in FIG. 4, jitter correction for less than one clock is omitted;
Modulating the clock during D/A conversion, D/A
There are methods such as correcting using a variable address delay line after conversion. The part that excludes the processing for dropout and HSYNC loss was explained above using the block diagram in Figure 4. When HSYNC is lost due to dropout or skew, the previous and subsequent positions are determined by referring to the dropout signal and the head switch signal. The H error correction means for calculating or interpolating from the phase difference will be explained below with reference to the block diagram of FIG. The A/D converter 4, main memory 5, D/A converter 8, address memory 14, and memory control 11 have the same functions as in the first embodiment, and their explanations will be omitted. In the H error detector 13, the difference between PBH and reference HD is 1.
It detects a phase difference greater than one clock, and also detects a phase difference less than one clock from the burst signal included in the reproduced signal. The amount of error detected in this way is due to dropout or skew.
When HSYNC is missing, it is inaccurate, and this is corrected by the H error corrector 16. To perform the correction, two signals are added to the H error corrector 16: a DOP signal that indicates that a dropout has occurred, and a HEADSW signal that indicates which head is playing back and where the switching point is. There is. Let the phase error amount of a certain line be (Xn±x), and the current error be (Xn)
Then, the output of the H error corrector 16 is expressed as shown in the table below.

[Table] ((Xn+2) to (Xn-2) are the phase errors from two lines before to two lines after, respectively.)
The time axis fluctuations that occur in a VTR are caused by tape 5
0, vibration and mechanical distortion of the cylinder 51, and each of the heads 52 and 53 during compatible tape playback.
Due to variations in the mounting position between VTRs, it is as shown in Figure 8. In other words, most of the low frequency components of time-axis fluctuations have a fixed pattern, and the random jitter (generally referred to here as the standard - the fluctuation ratio of one horizontal period of the reproduced video signal to the horizontal period) is 0.01 to 0.001. It takes advantage of the fact that it is small, about %. Therefore, the correction to be applied to the H error corrector 16 may be performed by a method other than that shown in the above table, as long as it is calculated or complemented from the phase error amount of the previous and succeeding lines by referring to the HEADSW signal when a PBH or burst is missing. Next, a phase error amount of one clock or less is written into the phase difference memory 15, and a phase error amount corresponding to the read line of the main memory 5 is read out and added to the clock phase modulator 12. In this way, the clock of the D/A converter 8 is changed to correct time axis fluctuations within one clock. As mentioned above, when PBH or burst is missing,
The phase error amount is corrected after referring to the HEADSW signal, resulting in stable operation. Next, a second embodiment of the present invention is shown in FIG. In this embodiment, H-
It is characterized by having PLL. In FIG. 9, the write timing signal PLL- which is phase synchronized with PBH in H-PLL ₂₁
Creating H. The write controller 22 controls the write to the main memory so that the write to the main memory 5 is performed at the timing of this PLL-H. Also, in the H error detector 13, PBH
The phase difference between PLL-H and PLL-H is detected. The readout is controlled by the readout controller so that it is performed at the timing of the reference HD, similar to the first embodiment shown in the block diagram of FIG. Furthermore, memory control 11 in Fig. 6
Other than that, the configuration is the same and the explanation will be omitted. As described above, in this embodiment, PBH and PLL-H
Since the difference between the PLL and the PLL is taken as the phase error amount, only the time axis fluctuation of the high frequency component to which the PLL cannot respond is the phase error amount. Therefore, even if a time axis variation ΔT occurs between the reference HD and the PBH as shown in FIG. 10, the amount of phase error will be approximately Δt. Therefore, the remaining memory capacity for the horizontal period of the main memory 5 described in the configuration of the present invention can be reduced,
It is suitable for systems that require a large TBC window width, such as VTRs with large time axis fluctuations and portable VTRs. Effects of the Invention According to the present invention, the difference between PBH and reference HD is
It only needs to be determined before starting to read the memory corresponding to the corresponding line in order to output the video signal from the TBC.
Sufficient processing time is secured for missing H, SYNC, or burst signals in the VTR playback signal, and when PBH or burst is missing,
The amount of phase error is corrected after referring to the HEADSW signal, and unlike the conventional TBC that uses a PLL to create a clock for writing to memory, the TBC response is instantaneous and is free from dropouts and missing burst signals. It becomes very stable.

[Brief explanation of drawings]

1 and 2 are block diagrams showing the configuration of a conventional time axis correction device, FIG. 3 is a diagram for explaining the configuration of a memory section in the conventional example, and FIG. 4 is an embodiment of the present invention. 5 is a block diagram showing the configuration of the time axis correction device in the same embodiment, FIG. 6 is a block diagram of the time axis correction device in another embodiment of the present invention, FIG.
FIG. 8 is a diagram for explaining phase fluctuations of PBH in a segment-type VTR, FIG. 9 is a block diagram for explaining memory control in still another embodiment of the present invention, and FIG. 10 is a diagram for explaining phase fluctuations. It is a figure for explanation. 5...Main memory, 11...Memory control, 1
3...H error detector, 14...address memory.

Claims (1)

[Claims] 1. A/D conversion means for quantizing the reproduced signal, main memory means for storing the quantized reproduction signal, and D/A conversion means for converting the quantized signal read from the main memory means into an analog signal. and,
A memory control means for controlling reading and writing to the main memory means, an H error detection means for detecting the phase difference between the reproduced signal and the reference signal, and a
H error correction means for calculating or compensating from the phase difference before and after referring to the dropout signal and the head switch signal when HSYNC is missing; and address storage means for storing the output signal of the H error correction means; The memory control means
A time axis correction device characterized in that writing to a memory is performed using an absolute address, and reading from the memory is performed using a relative address corrected by an H error correction means to a phase error amount of an H error detection means.