JPS59221186A - Time axis correcting device - Google Patents

Abstract

PURPOSE:To obtain a time axis correcting device having fast response speed by using an absolute address for the write to a memory and using a relative address in response to the phase error amount between a reference synchronizing signal and a reproduced horizontal synchronizing signal for the read. CONSTITUTION:A reproduced signal for a VTR A/D-converted by an A/D converter 4 is written in a main memory 5 by the reference synchronzing signal HD and a phase locked clock of this signal HD. On the other hand, the amount of phase error between a reproduced horizontal synchronizing signal PBH and the reference signal HD is detected by an H error detector 13 and written in an address memory 14. Further, the read from the main memory 5 is conducted so that the address point of the address memory 14 and the phase of the reference signal HD are made coincident. That is, the write is conducted by using the absolute address in a memory control 11 and the read is performed by the relative address in response to the horizontal synchronizing signal PBH and the reference signal HD.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a time axis correction device used for correcting time axis fluctuations associated with recording and reproducing video signals.

Conventional configuration and its problems The playback signal of a video tape recorder (hereinafter referred to as VTR) is subject to time axis fluctuations due to tape vibration, tape elongation, uneven rotation of the video head, and geometric distortion of the head assembly. A device that removes this time base variation is called a time base correction device, and is generally referred to as a time base collector (TBC).

FIG. 1 shows the general configuration of a conventional TBC.

Sync separator 1 from the VTR playback signal on the writing side of the memory.
A clock generator 2 generates a clock that is phase-locked to horizontal synchronization number 41 (hereinafter referred to as PBH) separated by PBH. A write address generator 3 generates a memory address in one-to-one correspondence with the horizontal position of the video signal using this PBH and the clock, and the A/D converter 4 writes the A/D converted video signal into the memory 5. On the reading side, the clock generator 6 generates a clock phase-locked to the reference synchronization signal, and uses this clock and the reference synchronization signal (hereinafter referred to as reference HD) to read out the read address corresponding to the horizontal synchronization signal of the reference synchronization signal. Generated by address generator 7,
By reading the signal from the memory 5 and performing D/A conversion with the D/A converter 8, a time-axis corrected video signal is obtained.

However, this method of TBC is based on PB whose time axis fluctuates.
A more complicated circuit is required to generate a more stable write clock than H, and a phase-locked loop (hereinafter referred to as PLL) circuit is generally used. By the way, in general, in a helical scan VTR, the video signal for one field is recorded on one or two tracks.
It is well known that the reproduced video signal becomes temporally discontinuous at the point where the signal reproduced from one track switches to the signal reproduced from the next track (hereinafter referred to as the head switching point), and is generally referred to as skew. It is called. Conventional VHS.

Skew also occurs in VTRs of various systems such as Beta and C formats, so the switching point is set at the beginning of vertical blanking to prevent skew from appearing on the screen. Therefore, VH3, Beta,
TBCs for VTRs of systems such as C format only need to respond within the vertical retrace period, and a TBC as shown in FIG. 1 was used.

On the other hand, in order to reduce the size and widen the band of a VTR, it is possible to reduce the cylinder diameter and increase the rotation speed, and a segment type VTR such as the B format (SMPTE type B 1-inch VTR) may be considered. However, in segment type VTRs, skew appears on the screen, so a TBC with a fast response speed is required.

Conventional segment type VTRs use analog TBs that detect the difference between the VTR playback signal and the reference signal using H8YNC and immediately switch the delay time of the video signal delay line.
C is also available, but it has limitations in wideband and correction range, and the circuit is complicated.

On the other hand, as a digital TBC, as shown in FIG. 2, there is a TBC which does not have a feedback loop and is called a feedforward type TBC. The A/D converter 4 A/D converts the VTR playback signal, and the tape H creator 9 converts it into a P.
BH is detected and created, and memory 5 is created at the timing of this PBH.
I am writing to. Here, it is assumed that the clock of the A/D converter 4 is phase-locked with the reference HD. Therefore, at the time the data is written to the memory, the time axis variation is corrected to within one polygon. Next, the digital signal read out from the memory 6 in synchronization with the ID (reference) is phase-modulated in the clock phase modulator 12 according to the phase difference between the PBH and the clock detected by the phase detector 10/ζ clock By adding the signal to the /A converter 8, time axis fluctuations of one clock or less are corrected.

The memory control 11 controls writing and reading. Now, the video signal of the nth line is generated p), and if a certain position from PBH is 8, then this PB
The video signal at a certain position from H is A+ on the n+1th line.
1. On the n+2th line, A+2 is written at a fixed position on the memory as shown in FIG. Therefore, if the PBH is lost due to skew or dropout, it becomes difficult to write the reproduced signal to the memo IJ 5.

Unfortunately, in order to increase the recording density, the recording wavelength on the tape tends to be shorter, which tends to increase dropouts, and as mentioned above (PB'H or PBH and the timing to write to memory only from one burst is available). Otherwise, it will be unstable as a TBC for high-density recording VTRs.

OBJECTS OF THE INVENTION It is an object of the present invention to provide a time base correction device with a fast response speed that can be sufficiently used in segment type VTRs.

Structure of the Invention The present invention is configured such that writing to the memory is performed using an absolute address, and reading from the memory is performed using a relative address according to the amount of phase error between the reference synchronization signal and the horizontal synchronization signal separated from the reproduction signal. This is a time axis correction device.

Description of examples Examples of the present invention will be described below.

FIG. 4 is a block diagram of a time axis correction device according to an embodiment of the present invention, and FIG. 6 is a memory configuration diagram.

The reproduced signal of the VTR that has been A/D converted by the A/D converter 4 is written into the main memory 5 using a clock (hereinafter simply referred to as a clock) that is phase-synchronized with the reference HD and this iD. On the other hand, the amount of phase error between PBH and reference H'D is H
It is detected by the error detector 13 and written into the address memory 14. Therefore, if the horizontal scanning line of the reproduced signal is n and the sampling point of the reproduced signal with reference to the reference HD is X, then the reference point A of the reproduced signal with PBH as the reference is the main memory 6 as shown in FIG. The address of point A is written in the address memory 14. Next, on the reading side, reading is performed so that the address point (x2) written in the address memory 14 matches the phase of the reference HD. That is, in the memory control 11, writing is performed using an absolute address, and reading is performed using a relative address according to the difference between the PBH and the reference HD. Therefore, the configuration is such that the difference between the PBH and the reference HD need only be determined before reading out that line. The main memory 6 is configured to have addresses with a margin equivalent to one horizontal period and an amount equivalent to the amount of phase error.

In this embodiment, the H error is detected by the A/D converter 4.
Although this is done by detecting the PBH after the A/D converter 4, the PBH may be created before the A/D converter 4. Also the fourth
In the figure, correction of jitter of one clock or less is omitted, but there are methods such as modulating the clock during D/A conversion or correction using an analog variable delay line after D/A conversion.

FIG. 6 is a block diagram of a second embodiment of the invention.

A/D converter4. The main memory 5, the D/A converter 8, the address memory 14, and the memory control 11 have the same functions as in the first embodiment, and their explanation will be omitted.

The H error detector 13 detects a phase difference of one clock or more between the PBH and the reference HD, and detects the burst signal included in the reproduced signal. A phase difference of less than l11 clocks is detected. The amount of error detected in this way is inaccurate when H8YNC is missing due to dropout or skew, and this is corrected by the H error correctors 1 and 6. In order to perform correction here, two signals are used: the DOP signal to notify that a dropout has occurred, and the EADS'W signal (to notify which head is playing back and where the switching point is). The phase error amount of a certain line is added to the corrector 16.
Xn+x) and the current error is (Xn), the output of the H error corrector 16 is expressed as shown in the table below.

((Xn+2)-(Xn-2) is 2 lines before each
This is the amount of phase error after two lines. ) This means that the time axis fluctuations that occur in a helical scan VTR as shown in FIG.
1 vibration and mechanical distortion, and in compatible tape playback,
This is due to variations in the mounting positions of the heads 52 and 63 among the VTRs, as shown in FIG. In other words, most of the low frequency components of time axis fluctuations have a certain pattern, and the random thick (the commonly referred to standard here - the fluctuation ratio of one horizontal period of the reproduced video signal to the horizontal period) is 0.01. ~o, oo takes advantage of the fact that it is only about 1%.

Therefore, the correction in the H error corrector 16 can be applied to PBH or burst loss in addition to those shown in the table above.
Any method may be used as long as it refers to the signal and calculates or complements the amount of phase error of the previous and subsequent lines.

Next, a phase error amount of one clock or less is written into the phase difference memory 16, and a phase error amount corresponding to the read line of the main memory 6 is read out and added to the clock phase modulator 12. In this way, by changing the clock of the D/A converter 8, time axis fluctuations within one clock are corrected.

As mentioned above, when PBH-4 or burst is missing, HEA
The phase error amount is corrected after referring to the DSW signal, and stable operation is performed.

Next, a third embodiment of the present invention is shown in FIG.

In this embodiment, H-PL is installed in the memory control section of FIG.
It is characterized by having an L.

In FIG. 9, a write timing signal PLL-H is generated in H-PLL 21 in phase synchronization with PBH. The write controller I/roller 22 controls the write to the main memory so that the write to the main memory 5 is performed at this timing of P L L-H. The H error detector 13 detects the phase difference between PBH and PLLH.

The readout is controlled by the readout controller so that the readout is performed at the timing of the reference HD as in the second embodiment.

Note that the configuration other than the memory control 11 in FIG. 6 is the same, and a description thereof will be omitted.

As described above, in this embodiment, since the difference between PBH and PLL-H is used as the phase error amount, only the time axis fluctuation of the high frequency component to which the PLL cannot respond becomes the phase error amount. Therefore, as shown in FIG. 10, even if a time axis variation ΔT occurs between the reference HD and the PBH, the phase error amount is approximately Δt. Therefore, the memory capacity margin corresponding to the horizontal period of the main memory 5 described in the configuration of the present invention can be reduced, and it can be used for VTRs with large time axis fluctuations and portable VTs.
It is suitable for systems such as R that require a large TBC window width.

Effects of the Invention According to the present invention, the difference between the PBH and the reference HD need only be determined before reading out the memory corresponding to the line in question in order to output the video signal from the TBC. Sufficient processing time is ensured for missing H, 5YNC or burst signals in the VTR reproduction signal, and the response of the TBC is instantaneous, unlike the conventional TBC which uses a PLL to create a write clock to the memory.

[Brief explanation of the drawing]

1 and 2 are block diagrams showing the configuration of a conventional time axis correction device, FIG. 3 is a diagram for explaining the configuration of a memory section in the conventional example, and FIG. 4 is an embodiment of the present invention. A block diagram showing the configuration of the time axis correction device in the example, FIG. 6 is a diagram showing the memory configuration in the same example, FIG. 6 is a block diagram of the time axis correction device in another example of the present invention,
Figure 7. FIG. 8 is a diagram for explaining phase fluctuations of PBH in a segment type VTR, FIG. 9 is a block diagram for explaining memory control in still another embodiment of the present invention, and FIG. 10 is a diagram for explaining phase fluctuations of PBH in a segment type VTR. This is a diagram for illustration purposes only. 5...Main memory, 11...Memory control, 13...H error detector, 14...Address memo 9 Name of agent Patent attorney Toshio Nakao and 1 other person Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 d Figure 7 Figure 8 = 551 Figure 9 Clock Figure 10

Claims (1)

[Claims] A time axis correction device characterized in that writing to a memory is performed using an absolute address, and reading from the memory is performed using a relative address according to the amount of phase error between a reference synchronization signal and a horizontal synchronization signal separated from a reproduction signal.